Read-Only Memories. L25 Outline. Two-dimensional decoding. Larger example, 32Kx8 ROM

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1 L25 Outline Read-Only Memories Read-only memories Static read/write memories Dynamic read/write memories Program storage Boot ROM for personal computers Complete application storage for embedded systems. Spring 2002 EE/CoE 243 1/L25 Spring 2002 EE/CoE 243 2/L25 Two-dimensional decoding Larger example, 32Kx8 ROM Spring 2002 EE/CoE 243 3/L25 Spring 2002 EE/CoE 243 4/L25 1

2 Typical commercial EEPROMs Microprocessor EPROM application Spring 2002 EE/CoE 243 5/L25 Spring 2002 EE/CoE 243 6/L25 ROM control and I/O signals ROM timing Spring 2002 EE/CoE 243 7/L25 Spring 2002 EE/CoE 243 8/L25 2

3 ROM Applications In addition to storing program code, ROMs have other uses: Look-up Tables (LUT) for constants Symbol conversion Fixed address translation Next state logic Arbitrary combinational logic The ROM address is the input; the stored data is the output. Spring 2002 EE/CoE 243 9/L25 ROM vs. PLA How does implementing combinational logic using a ROM compare to a PLA? A ROM stores the entire truth table, whereas a PLA implements implicants. Direct area comparisons depend upon the relative sizes of a ROM cell vs. a PLA cell and how many implicants are required. In general, a PLA will be smaller. Spring 2002 EE/CoE /L25 Read/Write Memories SRAM a.k.a. RAM (Random Access Memory) Volatility Most RAMs lose their memory when power is removed NVRAM = RAM + battery Or use EEPROM SRAM (Static RAM) Memory behaves like latches or flip-flops DRAM (Dynamic Memory) Memory lasts only for a few milliseconds Must refresh locations by reading or writing Spring 2002 EE/CoE /L25 Spring 2002 EE/CoE /L25 3

4 SRAM operation Individual bits are D latches, not edge-triggered D flip-flops. Fewer transistors per cell. Implications for write operations: Address must be stable before writing cell. Data must be stable before ending a write. SRAM array Spring 2002 EE/CoE /L25 Spring 2002 EE/CoE /L25 SRAM control lines SRAM read timing Similar to ROM read timing Chip select Output enable Write enable Spring 2002 EE/CoE /L25 Spring 2002 EE/CoE /L25 4

5 SRAM write timing Bidirectional data in and out pins Address must be stable before and after write-enable is asserted. Data is latched on trailing edge of (WE & CS). Use the same data pins for reads and writes Especially common on wide devices Makes sense when used with microprocessor buses (also bidirectional) Spring 2002 EE/CoE /L25 Spring 2002 EE/CoE /L25 SRAM devices Similar to ROM packages Synchronous SRAMs Use latch-type SRAM cells internally Put registers in front of address and control (and maybe data) for easier interfacing with synchronous systems at high speeds E.g., Pentium cache RAMs 28-pin DIPs 32-pin DIPs Spring 2002 EE/CoE /L25 Spring 2002 EE/CoE /L25 5

6 DRAM (Dynamic RAMs) SRAMs typically use six transistors per bit of storage. DRAMs use only one transistor per bit: 1/0 = capacitor charged/discharged DRAM read operations Precharge bit line to V DD /2. Take the word line HIGH. Detect whether current flows into or out of the cell. Note: cell contents are destroyed by the read! Must write the bit value back after reading. Spring 2002 EE/CoE /L25 Spring 2002 EE/CoE /L25 DRAM write operations DRAM charge leakage Take the word line HIGH. Set the bit line LOW or HIGH to store 0 or 1. Take the word line LOW. Note: The stored charge for a 1 will eventually leak off. Typical devices require each cell to be refreshed once every 4 to 64 ms. During suspended operation, notebook computers use power mainly for DRAM refresh. Spring 2002 EE/CoE /L25 Spring 2002 EE/CoE /L25 6

7 64K x 1 DRAM DRAM-chip internal organization RAS/CAS operation Row Address Strobe, Column Address Strobe n address bits are provided in two steps using n/2 pins, referenced to the falling edges of RAS_L and CAS_L Traditional method of DRAM operation for 20 years. Now being supplanted by synchronous, clocked interfaces in SDRAM (synchronous DRAM). Spring 2002 EE/CoE /L25 Spring 2002 EE/CoE /L25 DRAM read timing DRAM refresh timing Spring 2002 EE/CoE /L25 Spring 2002 EE/CoE /L25 7

8 DRAM write timing Spring 2002 EE/CoE /L25 8