State Variable Model for Considering the Parasitic Inductor Resistance on the Open Loop Performance of DC to DC Converters

Transcription

1 Jurnal f Cmputer and Cmmunicats, 04,, 4-48 Published Onle Nvember 04 SciRes. State ariable del fr Cnsiderg the Parasitic Inductr Resistance n the Open p Perfrmance f C t C Cnverters Carls Albert zan Espsa Pntificia Universidad Javeriana, Santiag de Cali, Clmbia [email protected] Received 7 Octber 04 Abstract This paper shws C and small-signal circuit mdels fr the PW C t C buck, bst and back/ bst cnverters with the equivalent series resistance f the ductr. The C vltage transfer funct and the efficiency f the cnverter are derived frm the C mdel. Small-signal pen-lp characteristics are derived frm the small-signal mdel based n a state variable mdel. A design example prves the perfrmance f the circuit and verificat f the mdel. Keywrds C t C Cnverter, Parasitic Resistance f Inductr, Small Signal Analysis, Buck Cnverter, Bst Cnverter, Buck-Bst Cnverter. Intrduct any papers abut small signal analysis f a C t C buck-bst cnverter can be fund literature that clude parasitic resistances ductr and capacitrs and vltage drp pwer switch and dide []-[5]. Usually, the signal mdel representat is btaed frm an equivalent circuit [4], r ther cases, usg a state variable mdel [3]. Any mdel can be calculated based n the cntuus cnduct mde r a nn-cntuus cnduct mde but have different results because the frmer has cntrl ver the duty cycle and the latter has cntrl ver the frequency. The bjectives f this paper are: t bta a C and small-signal lear circuit mdels f PW buck, bst and buck/bst C-C cnverter, takg t accunt parasitic resistance f the ductr; t derive the C vltage transfer funct and efficiency; t derive small-signal pen-lp put-t-utput transfer funct usg a state variable mdel; and t demnstrate, by a design cnsiderat, the perfrmance f a real circuit.. Wrk escript In ann ideal C t C cnverter, it is necessary t cnsider pwer lsses frm parasitic resistance f the ductr, parasitic resistance f capacitrs and pwer lsses semicnductr switch and dide. Figure shws sme real C t C cnverters with parasitic resistance ductr. Hw t cite this paper: Espsa, C.A.. (04) State ariable del fr Cnsiderg the Parasitic Inductr Resistance n the Open p Perfrmance f C t C Cnverters. Jurnal f Cmputer and Cmmunicats,,

2 C. A.. Espsa Figure. C t C Cnverters: (a) Bst; (b) Buck; (c) Buck-bst. ltage drp switch and dide can be neglected the analysis f the circuit if the vltage put is much greater than the drp vltage switch, and vltage drp dide. Als, the parasitic resistance series with capacitr can be reduced by sme parallel capacitrs. Neglectg vltage drp switch and dide and parasitic resistance capacitr, when switch is ON, the fllwg equats represent the behavir f the circuit buckbst Figure (c). di + ir + = 0 () dt And, when switch is OFF, d = C () R dt di + ir + = 0 (3) dt i R d dt The state matrixes f these equats are: When switch is ON, And when switch is OFF = C (4) d i R / 0 i / dt = + 0 / RC 0 d i R / / i 0 dt = + / C / RC 0 Addg bth states, fr ton = T and toff = ( T ) (5) (6) 4

3 C. A.. Espsa d i R / ( ) / i / dt = + ( ) / C / RC 0 Usg aplace t slve this first rder equat, the vltage put-t-utput transfer funct is, G v ( s) ( ) = = R C s + + s+ (( ) + ) RC C (7) (8) R where =. The crner frequency is R In steady state, the transfer funct is, aximum ga ccurs when, That is, f ( ) + α = (9) π C C = = ( ) + ( ) ( ) (( ) ) + = = 0 + (0) () = ( + ) ( + ) () Figure shws the maximum ga f the circuit fr values f α between 0.0 and 0.. As seen, lwer values f α give bigger values f ga and the circuit gets clser t an ideal circuit. Cnsiderg this, buck-bst C t C cnverter perates cntuus cnduct mde it is necessary t make sure the lwest ductr current is abve cer: Figure. ltage ga vs. R /R f a buck-bst cnverter. 43

4 C. A.. Espsa I i = I > (3) m 0 If this cndit is nt cnsidered, the ductr current will have times with zer current and the circuit will wrk nn cntuus mde. Here i = Imax Im, the peak currents f the ductr, and I is the average ductr current. The average ductr current is, When switch is pen, Then, The put current is, I I = = ( ) R( ) (4) ( ) + i = (5) f ( ) + ( ) Frm this equat, the C current transfer funct is, R R > (6) f I IC Efficiency is calculated frm the equat: = I (7) I ( ) = = (8) I I η = = C IC = I + α ( ) Fr validatg these equats a circuit with sme practical characteristics is designed and simulated. This circuit is a 000 watts buck-bst C t C cnverter with an put vltage = 70 vlts, utput vltage = 30 vlts, frequency f = 50 khz and 5% f vltage ripple. α can g up t 0.09, as seen n Figure. Wrkg with α = 0.05, (9) + = (0) With this equat duty cycle culd be r As the Figure 3 shws, small parasitic resistance ductance prduces mre vltage ga, but a maximum vltage ga des nt mean a maximum efficiency. S, rder t have a gd efficiency-ga relatship, it is better t wrk values f befre the maximum peak f ga, that is, the left side f the curve. Als, as seen n /, the vltage ga curve has less slpe with between zer and n the maximum ga than the rest f the curve, which means that a significant change vltage ga ccurs with varyg between at the maximum ga and ne, where the system becmes unstable r mre difficult t cntrl. In the same Figure 3, it is shwn the efficiency f the circuit which achieves arund 70% fr = and clse t 0% with = The values f resistances are R = 5.9 fr the lad and R =.645 f the permitted parasitic resistance f the ductr, s that, > 70.4 uh 80 uh () T calculate the capacitr, an equat derived frm an ideal circuit analysis, mst seen n any pwer electrnics bks, can be used, sce parasitic resistance f the ductr des nt terfere with the ripple vltage at the utput f the circuit. C = = 5uf () Rf ( ) 44

5 C. A.. Espsa Figure 3. Efficiency and vltage ga f a nn-ideal buck-bst cnverter with α = Simulat f the circuit, usg PSI, is shwn Figure 4 (with the ripple utput vltage). In the same Figure 4, it is shwn a simulat atlab f the step respnse f the transfer funct f the circuit (cntuus le). Bth simulats curves are superimpsed t demnstrate the same respnse and the validat f the equats with respect t simulats. Small values f parasitic resistances fr the ductr will have faster respnses but with sme versht, as the case f an ideal circuit. Als, bigger values f parasitic resistance fr the ductr will have mre lsses s that the efficiency will be lwer and the vltage ga will be reduced. Usg same prcedure, equats fr buck and bst cnverters can be btaed and they are shwn Table and Table. Fr the bst cnverter the curve f vltage ga vs. α is shwn Figure 5. The efficiency fr maximum ga vltage fr each value f α is 50%. Efficiency is versely prprtal t α, s that rder t have a better efficiency with a reasnable vltage ga, it is necessary t reduce α by creasg the switchg frequency r cnstruct the ductance with a thicker wire. Figure 6 shws vltage ga and efficiency f a bst cnverter fr α = 0.0. With a lwer value f α higher efficiency can be btaed with higher vltage ga. Fr this example 90% efficiency can be achieved with a vltage ga f 3 and α = 0.0. When α = 0.05, fr a 90% efficiency nly it is pssible t have a vltage ga f.7. Figure 7 shws vltage ga varyg duty cycle fr different values f α. 3. Cncluss This analysis has cncentrated n fdg the ac mdel f C t C buck, bst and buck-bst cnverters, nly takg t accunt the parasitic resistance f the ductr. This is because large vltage cnvers, vltage drp semicnductr switch and dide can be neglected and the parasitic resistance f the capacitr can be easy reduced by many parallel. A buck-bst C t C cnverter has been designed fr verificat f the perfrmance f the circuit and cmparisn between the mdel and circuit simulat. As shwn, the vltage utput f the circuit clse fllw the equat btaed as a mdel. Als, the implicat f the value f the parasitic resistance f the ductr with respect t the value f the lad is shwn a curve fr maximum ga, maximizg the ga f the circuit with the duty cycle as the variable t be cntrlled. 45

6 C. A.. Espsa Figure 4. Cmparisn f circuit simulat and step respnse f transfer funct f a nn-ideal buck-bst cnverter. Figure 5. ltage ga vs. R /R fr bst cnverters with α between 0.00 and 0.. Figure 6. ltage ga and efficiency fr a bst cnverter with α =

7 C. A.. Espsa Figure 7. ltage ga vs. duty cycle fr a buck cnverter with α = 0.05, 0. and 0.. Table. Small signal mdel equats fr bst cnverter. Bst Cnverter Gv ( s ) C R s + + s+ (( ) + ) RC C f ( ) +α π C C ( ) + IC η + α ( ) ax Ga at = Table. Small signal mdel equats fr buck cnverter. Buck Cnverter Gv ( s ) f C IC η C R s + + s + ( + ) RC C + α π C

8 C. A.. Espsa Equats fr buck and bst cnverters are als shwn usg the same prcedure as buck-bst cnverter. References [] Kazimierczuk,. and Cravens, R. (994) Open-p C and Small-Signal Characteristics f PW Buck-Bst Cnverter fr CC. Aerspace and Electrnics Cnference, Prceedgs f the IEEE,, [] Wang, J.H., Zhang, F.H. and Gng, C.Y. and Chen, R. (0) delg and Analysis f a Buck/ Bst Bidirectal Cnverter with evelped PW Switch del. 0 IEEE 8th Internatal Cnference n Pwer Electrnics and ECCE Asia (ICPE & ECCE), ay 0, [3] Neacsu,., Bnnice, W. and Hlmansky, E. (00) On the Small-Signal delg f Parallel/Interleaved Buck/Bst Cnverters. 00 IEEE Internatal Sympsium n Industrial Electrnics (ISIE), July 00, [4] Wang, Q., Shi.X. and Chang, C.Y. (008) Small-Signal Transfer Functs fr a Sgle-Switch Buck-Bst Cnverter Cntuus Cnduct de. 008 ICSICT 9th Internatal Cnference n Slid-State and Integrated-Circuit Technlgy, Beijg, 0-3 Octber 008, [5] Ortiz, C. (005) Circuit Oriented Average delg f Switchg Pwer Cnverters. 005 Eurpean Cnference n Pwer Electrnics and Applicats,