Application Note AN-1162

Transcription

1 Applicatin Nte AN-6 mpensatr Design Prcedure fr Buck nverter with ltage-mde Errr-Amplifier By: Amir M. ahimi, Parviz Part, and Peyman Asadi Table f ntents Page. Intrductin t Synchrnus Buck nverter.... Lp Gain f the System...5. Step by Step mpensatr Design Prcedure Type II mpensatr Design Design Example f Type II mpensatr Type III mpensatr Type III- A mpensatr Design Example f Type III-A mpensatr Type III- B mpensatr Design Example f Type III-B mpensatr nclusin... Appendices: Designing the Pwer Stage f the Synchrnus Buck nverter...4 Sme Special ases f mpensatr Design...8 Lp espnse Measurement... AN-6

2 mpensatr Design Prcedure fr Buck nverter with ltage-mde Errr-Amplifier Synchrnus buck cnverters have received great attentin in lw vltage D/D cnverter applicatins because they can ffer high efficiency; prvide mre precise utput vltage and als meet the size requirement cnstraints. Internatinal ectifier Inc. has develped a series f integrated buck regulatrs (SupIBuck TM ) t accmmdate all the abve. These regulatrs cmbine I s latest MOSET technlgy with high perfrmance prcess technlgy fr I cntrller. These regulatrs use a PWM vltage mde cntrl scheme with external lp cmpensatin t prvide gd nise immunity and maximum flexibility in selecting inductr values and capacitr types. The switching frequency can be prgrammed frm 50kHz t abve.5mhz t prvide the capability f ptimizing the design in terms f size and perfrmance. In this applicatin nte stabilizing the buck cnverter with vltage-mde errr amplifier is discussed. The gal is t highlight the advantage f this cntrl scheme and illustrate hw a high perfrmance feedback lp that allws fast lad transient respnse and accurate steady state utput can be achieved.. Intrductin t Synchrnus Buck nverter with ltage-mde Errr- Amplifier A buck cnverter with vltage-mde cntrl and vltage-mde errr amplifier can be stabilized with a prprtinal-integral (PI) type f cmpensatr. Hwever, t have high perfrmance a mre sphisticated cmpensatin netwrk is required, especially when ML (Multi Layer eramic apacitr) capacitrs are used. ML capacitrs are widely used at the utput f lw vltage D/D cnverters because f their lw equivalent series resistance (ES) and lw equivalent series inductance (ESL). Lw ESL, which results in high resnance frequency, makes the ML capacitrs desirable at high switching frequencies. Besides, lw ESL and lw ES make the utput vltage switching ripple smaller which is very desirable. On the ther hand, stabilizing a D/D cnverter AN-6

3 with ML utput capacitrs requires mre attentin as cmpared t stabilizing a cnverter with electrlytic utput capacitrs. Depending n the type/size f the cmpnents f utput filter which are used and the design parameters (switching frequency, bandwidth, etc), different cmpensatin netwrks might be required. In additin, t achieve the desired perfrmance, the parameters f the cmpensatin netwrk must be adjusted prperly. This dcument prvides guidelines t design apprpriate cmpensatin netwrk in varius cnditins. In additin, the prcedure f cmpensatr design has been explained with examples. igure shws a typical synchrnus buck cnverter with vltage-mde cntrl and vltage-mde errr-amplifier. ntrl ET Output Inductr L L ut + - in Sync ET Output apacitr ES Lad Gate Drivers mpensatin Netwrk + - sc PWM Generatr e - + ref Errr Amplifier igure - Simplified circuit diagram f a synchrnus buck cnverter with a vltagemde errr-amplifier In igure, L is the inherent resistance f the utput inductr and ES is the equivalent series resistance f the utput capacitr. T make the analysis simpler, the ESL f the utput capacitrs is neglected. The circuit shwn in igure can be mdeled with three blcks as presented in igure. The pwer stage (G p (s)) includes the switches, the drivers and the utput inductr and capacitr. The mdel f the PWM generatr is simply / sc [], where sc is the peak t peak amplitude f the scillatr vltage (saw-tth) AN-6

4 listed in the datasheet. The cmpensatr blck (H(s)) represents the errr-amplifier with the cmpensatin netwrk. ref + - mpensatr H(s) e d (duty cycle) sc PWM Generatr G(s) G P (s) Pwer Stage ut k igure - The blck diagram mdel f the synchrnus buck cnverter The transfer functin f the pwer stage can be simplified as fllws: G ( s ) P ut ( s ) d L s ( Lad Lad ( ES s ) ES ) s ( L Lad ES ) Lad in () The s indicates that the transfer functin varies as a functin f the frequency. r simplicity the transfer functins f the PWM generatr and the pwer stage can be cmbined: G( s ) GP( s ) () sc Therefre, G(s) is usually referred t as the transfer functin f the pwer stage. The rts f the plynmial in the denminatr f () are called the ples f the transfer functin f the pwer stage. Similarly the rts f the numeratr f () are the zers f the transfer functin f the pwer stage. The transfer functin f the pwer stage is a secnd rder system with a duble ple at the resnance frequency (f the L filter) and a zer prduced by the ES f the utput capacitr. The resnance frequency and the zer frequency assciated with the ES are given by () and (4). The apprximate Bde plt f the pwer stage is sketched in igure. The duble ple causes the gain t fall with a slpe f -40dB/dec up t the zer frequency ( ES ) which cmpensates ne f the ples. The zer frequency is a characteristic parameter f the utput capacitr and is dependant n the type f the capacitr used. This frequency can be as lw as a few khz AN-6 4

5 fr an electrlytic capacitr t as high as a few MHz fr a ceramic capacitr. Mre infrmatin abut designing the pwer stage is prvided in Appendix A. L π L (frequency f the duble ples) () ES π ES (frequency f the zer) (4) i n sc L Magnitude -40dB ES -0dB 0 Phase igure - The bde plt f the pwer stage f the buck cnverter. Lp Gain f the system The lp gain f system is defined as the prduct f transfer functins alng the clsed cntrl lp. Using igure, the lp gain is defined as: M( s ) Where H( s ) k sc GP( s ) H( s ) G( s ) k k represents the gain f the resistr divider which is used in the feedback lp (5) when. r sme cnfiguratins f cmpensatin netwrk, as the nes ut ref discussed in the next sectins, this term ( k ) is canceled ut and des nt appear in the lp-gain equatin. The bde plts f pwer stage and desired lp gain is shwn in igure 4, where 0 is the zer crssver frequency defined as the frequency when lp gain equals unity. 0 is als called the bandwidth f the lp r the bandwidth f the system. AN-6 5

6 Typically, 0 can be set t /0~/5 f the switching frequency. The speed f the system respnse t lad transients is determined by 0. In ther wrds, the higher the crssver frequency, the faster the lad transient respnse wuld be. Hwever, the crssver frequency shuld be lw enugh t allw attenuatin f switching nise. The slpe f the lp gain at 0 shuld be abut 0dB in rder t ensure a stable system. The phase margin shuld be greater than 45º fr verall stability. i n sc igure 4 - Bde plt f the pwer stage, desired lp gain, and lp phase. Step by step cmpensatr design prcedure As mentined in the Intrductin, t have a stable clsed lp buck cnverter with apprpriate perfrmance, a prperly designed cmpensatr is required. The typical prcedure f cmpensatr design is as fllws: Step - llect system parameters such as input vltage, utput vltage, maximum lad/utput current, switching frequency, input and utput capacitance, and utput inductance. Step - Using () and (4) determine the pwer stage ples and zer Step - Determine the zer crssver frequency f the lp, 0. Usually this frequency is chsen equal t /0 t /5 f the switching frequency. AN-6 6

7 0 ( / 0 ~ / 5 ) (6) S Step 4 - Determine the cmpensatin type. The cmpensatin type is determined by the lcatin f zer crssver frequency and characteristics f the utput capacitr as shwn in Table. Step 5 - Determine the desired lcatin f the ples and zers f the selected cmpensatr (this will be explained fr each type f cmpensatr). Step 6 - alculate the real parameters (resistrs and capacitrs) fr the selected cmpensatr s that the desired ples/zers are achieved. hse the standard values fr resistrs and capacitrs such that they are as clse t the calculated values as pssible. Table - The cmpensatin type and lcatin f zer crssver frequency. mpensatr Type elative lcatin f the crssver and pwer-stage frequencies Typical Output apacitr Type II (PI) L ES 0 S / Electrlytic, POS-ap, SP-ap Type III-A (PID) / POS-ap, SP-ap Type III-B (PID) L L 0 ES S 0 / eramic S ES 4. Type II mpensatr Design Type II cmpensatin is used fr applicatins where the frequency f the zer caused by utput capacitr and its ES ( ES ) is smaller than the clsed lp bandwidth ( 0 ) as shwn belw: L (7) ES 0 S / This cnditin is usually met when the utput capacitr is f electrlytic type. The ES (refer t (4)) fr this type f capacitr is in the range f a few khz. The schematic f the type II cmpensatr is depicted in igure 5. AN-6 7

8 Zc ut c c c f f - + E/A e ref igure 5 - Type II cmpensatr Assuming the gain/band-width f the errr-amplifier (E/A) is very high, the transfer functin f this cmpensatr is given by: H( s ) e s ( s ) (8) ut f s ( ) ( s ) The capacitr is chsen s that. Therefre: H( s ) s (9) s ( s ) f The rt f the numeratr in (8) is the zer f cmpensatr and the rts f the denminatr are the ples f the cmpensatr. Therefre, the cmpensatr has a ple at the rigin (an integratr) and anther ple and ne zer as given belw: Z P π (0) π () The apprximate bde-plt f the pwer stage, the Type II cmpensatr, and the desired lp gain has been drawn in igure 6. AN-6 8

9 igure 6 - Bde plt f the buck cnverter pwer stage, desired lp gain, and Type II cmpensatr Each ple makes the phase f the lp drp by 90º and each zer makes the phase rise by 90º. The phase change f a zer/ple starts at abut decade belw the frequency f the zer/ple and ends abut decade abve it. It shuld be nted that due t negative feedback (minus sign f H(s)) initially there is 80º phase-shift in the cmpensatr. The phase change due t ples and zers are added t this 80º. Hence, t have a stable system, the verall phase f the lp shuld never becme 60º/0º (r clse t it) when the gain is greater than (0dB). Especially, at crssver frequency ( 0 ), the phase shuld be at least 45º (45º phase margin). Since the cmpensatr has a ple at the rigin, the zer f the cmpensatr shuld be placed at a frequency lwer than the duble ples f the L filter t make sure the phase f the lp des nt drp clse t 0º arund L. Usually the fllwing equatin is used: Z L () The secnd ple f the cmpensatr shuld be placed higher than the crss-ver frequency s that its lagging phase (phase drp) des nt decrease the phase margin f the lp. On the ther hand, it shuld be placed lwer than the switching frequency, s that enugh attenuatin at the switching ripple is btained. The fllwing equatin gives a reasnable cmprmise: P S () / AN-6 9

10 After Z and p are selected the values f the cmpnents f the cmpensatr can be calculated. There is ne degree f freedm in calculating the values f the parameters f the cmpensatr. The prcedure can be started by selecting a reasnable value fr f. A value f a few kω shuld be a gd starting pint. Since f and utput vltage (igure 5), f can be calculated using the fllwing equatin: f are used t set the f ref f (4) ( ) ut ref The transfer functin frm the utput f the errr amplifier t the utput vltage is: G ( ES s ) ut in Lad ( s) ( s) (5) e sc L s ( Lad ES) s ( L Lad ES) Lad In the abve equatin, sc is the amplitude f the saw-tth/triangular mdulatr signal The amplitude f the lp-gain at crssver frequency is equal t ne. Therefre, H ( s) G( s) (6) f 0 Using the (9), (5), and (6) is calculated: f ES sc 0 (7) in L Since Z was chsen and was calculated, can be calculated: π Z. 5π L (8) Similarly, can be calculated: π P π S (9) AN-6 0

11 4. Design example f Type II cmpensatr r this design an I840 regulatr is used. The schematic f the design is given in igure 7. in = 4.5 <cc< K 6.8K in = 4 X 0 u + 0 u PG 0K PGd SS 0. u t.k u cc PGd Seq t SS / SD Enable I840 Gnd in Bt SW OSet b mp PGnd 6 0. u 50nH cc.8 4.7n c OSet.4k c 68p L 7.5kΩ c f.kω % f 768Ω % ut =x470µ, 0mΩ each POSAP + - igure 7 - Applicatin f I840 with type II cmpensatr fr a A,.8 regulatr Step - llect the system infrmatin such as input and utput vltage and the switching frequency: L ES( ) 0m each in ut ref sc nH 470μ 600KHz I (max) A S Step - alculate the ples and zer f the pwer stage. Using (), the duble ple f the pwer stage is at: L 7. KHz π L π 50nH 940μ AN-6

12 The zer caused by the ES f the utput capacitr can be calculated using (4):. khz ES π ES π 0m 470μ 8 Step - Select crssver frequency t be /0 f the switching frequency: 0 60KHz Step 4 - Select the type f cmpensatr. Since, Type II L ES 0 S / cmpensatr is suitable fr this applicatin. Step 5 - Select the ple and zer f the cmpensatr. Using () and (): Z P S L khz 5. khz / 600kHz / 00kHz Step 6 - alculate the parameters (resistrs and capacitrs) f the cmpensatr. Select. K f. f f is calculated using (4):.k ( ) Select f 768. alculate using (7):. k. 8kHz. 8 60kHz 7. 4k ( 7. khz ) hse 7. 5k. alculate using (8): 4. n π 7. 5k 5. khz hse 4. 7n. alculate using (9): p π 7. 5k 00kHz 74 hse 68p. The experimentally measured Bde plt f the lp fr this design is shwn in igure 8. The resulting crssver frequency is abut 6kHz and the phase margin is abut 54º. AN-6

13 igure 8 - The bde plt f the lp fr the example with Type II cmpensatr 5. Type III mpensatr r a general slutin fr uncnditinal stability fr any type f utput capacitrs, and a wide range f ES values, lcal feedback shuld be implemented with a type III cmpensatin netwrk. Specially, when 0 ES type II cmpensatr is nt useful and type III cmpensatr must be used. The typically type III cmpensatin netwrk which is used fr a vltage-mde PWM cnverter is shwn in figure 9. ut Zc c f c c f f f Z f - E/A OUT e + ref igure 9 - Type III cmpensatr The transfer functin f type III cmpensatr is given by: e Z H ( s) (0) Z ut f AN-6

14 4 AN-6 ) ( )] ( [ ) ( )] ( [ ) ( ) ( f f f f f f s s s s s s H () The ple which is generated by and is usually set at a much higher frequency as cmpared with the frequency f the zer generated by and. This means:. Therefre: ) ( ) ( )] ( [ ) ( ) ( f f f f f f s s s s s s H () The cmpensatr has tw zers and three ples as given belw: Z () ) ( f f f Z (4) p 0 (5) f f p (6) p (7) Depending upn the relative lcatin f ES, type III cmpensatr design is divided int tw categries: Type III-A and Type III-B cmpensatrs. 5. Type III- A mpensatr If the zer cased by the ES is belw half f the switching frequency, that is if (8) is valid, Type III-A cmpensatin methd is used. / 0 S ES L (8) nditin (8) might happen when OSON, POS-cap r SP-ap types f capacitrs are used at the utput f the D/D cnverter. If this happens, the ples and zers f the cmpensatr will be placed as fllws:

15 (9) Z L Z 0.75 Z L (0) () p ES / () p S The apprximate bde-plt f the pwer stage fr the Type III-A cmpensatr and the desired lp gain has been drawn in igure 0. L Pwer Stage -40dB ES Desired Lp Gain -0dB -0dB 0-40dB Type III-A mpensatr -0dB -0dB Z Z p p = S / igure 0 - Bde plt f the buck cnverter pwer stage, desired lp gain, and Type III-A cmpensatr The first zer f the cmpensatr ( Z) cmpensates the phase lag f the ple which is at the rigin. The secnd zer ( Z ) is t cmpensate fr ne f the ples f the L filter s that at 0 the slpe f the bde plt f the lp is abut -0dB/dec. The secnd ple f the cmpensatr ( p ) and the zer f the ES f the capacitr ( ES ) cancel each ther and the third ple ( p ) is t prvide mre attenuatin fr frequencies abve S /. The parameters f the cmpensatr can be calculated as fllws. irst a value fr f is selected (.n can be a gd start). Using (6) f is calculated: AN-6 5

16 f f p () Using (4) f is calculated: f f Z f (4) Using (4), f is calculated and is calculated using the fllwing equatin: 0 L in f sc (5) Using () calculate : Z (6) Using (7) calculate : p (7) 5. Design example f Type III-A cmpensatr r this design, as shwn in igure, I840 regulatr is used. in = 4.5 <cc<5.5 PG 0K PGd SS 0. u t.k PGd Seq t SS / SD Enable Gnd in in = 4 X 0 u + 0 u Bt cc L 560nH cc ut.8 u 49.9K 6.8K I840 SW OSet b mp PGnd 6 0. u.4k OSet.9n c f.n f 40Ω 4.kΩ c 0p c f 4.64kΩ % f.94kω % =x00µ, 8mΩ each SP-ap EESL0E0 igure - Applicatin f I840 with type III-A cmpensatr fr a A,.8 regulatr AN-6 6

17 Step - llect the system infrmatin such as input and utput vltage and the switching frequency: L ES( in Out ref sc nH 0μ 600KHz I (max) A S ) 8m each Step - Using () and (4) calculate the ples and zer f the pwer stage: L 4. 4KHz π 560nH 0μ khz ES π (8m / ) 0μ 80 Step - Selected crssver frequency t be abut /8 f the switching frequency: 0 80KHz Step 4 - Select the type f cmpensatr. Since /, Type III-A L 0 ES S cmpensatr is suitable fr this applicatin. Step 5 - alculate the ples and zers f the cmpensatr. Using (9) t () the ples and zers can be calculated: Z L 4. 4kHz Z kHz 0. 8kHz p ES 80kHz p 600kHz / 00kHz Step 6 - alculate the values f the parameters f the cmpensatr. hse Using (): 40 π. n 80kHz 9 f. f. n. AN-6 7

18 hse 40. Use (4) t calculate f : f f. π. n. khz Select f 4. 64k. Using (4), f can be calculated: 4. 64k 0. 7 f. 95k ( ) Select f. 94k. Use (5) t calculate : π 80k 560nH 0μ k. n hse 4. k. Use (6) t calculate :. n π 4. k 0. 8k 49 hse. 9n. Use (7) t calculate : p π 4. k 00k 5 hse 0 p. The experimentally measured bde plt f the lp fr this design is shwn in igure which shws the lp crssver frequency is phase-margin is abut 5º. 0 77kHz and a igure - The bde plt f the lp fr the example with Type III-A cmpensatr AN-6 8

19 5. Type III- B cmpensatr If the zer cased by the ES is abve half f the switching frequency, that is if (8) is valid, Type III-B cmpensatin methd is used. L 0 S / ES (8) nditin (8) happens when ML capacitrs are used at the utput side f the cnverter. Smetimes, using POS-ap r SP-ap types f capacitrs results in a type III-B system as well. If this happens, the ples and zers f the cmpensatr will be placed as fllws: / (9) p S Z and p pair (secnd ple and secnd zer f the cmpensatr) are cnsidered as a lead-cmpensatr and are lcated s that the maximum phase lead f this pair results at crssver frequency ( 0 ). The fllwing frmulas can be used t lcate Z and p in rder t get a maximum phase lead f θ at crssver frequency []: Z Sinθ 0 (40) Sinθ p Sinθ 0 (4) Sinθ θ is usually chsen t be 70º and this is abut the maximum practical phase-lead btainable frm a lead cmpensatr. The ther zer f the cmpensatr is chsen using the fllwing frmula: (4) Z 0. 5 Z The apprximate bde-plt f the pwer stage, the desired lp gain and the type III-B cmpensatr has been drawn in igure. Smetimes, the value f p calculated by (4) falls abve p. The rder f the ples is nt imprtant, hwever, the imprtant fact is that there are always tw cmpensatr ples abve 0 as shwn in igure. Z cmpensates the phase lag f the ple which is at rigin. Z and p frm a leadcmpensatr and prvide their maximum leading phase at crssver frequency and p prvides further attenuatin fr frequencies abve /. S AN-6 9

20 Similar t the calculatin fr type III-A cmpensatr, the parameters f the cmpensatr can be calculated. That is, a value fr f is selected and then using () t (7) the parameters f the cmpensatr are calculated. Pwer Stage -40dB ES L -0dB Desired Lp Gain -0dB 0-40dB Type III-A mpensatr -0dB -0dB Z Z p p igure - Bde plt f the buck cnverter pwer stage, desired lp gain, and Type III-B cmpensatr 5.4 Design example f Type III-B cmpensatr r this design, as shwn in igure 4, I84 regulatr is used. in = 4.5 <cc<5.5 PG 0K PGd SS 0. u t.k 49.9K 6.8K Seq t SS / SD Enable Gnd in in = X 0 u + 0 u Bt cc cc L.5µH SW ut.8 u PGd f I84.n f OSet.87k f 4.0kΩ % OSet 7Ω b mp PGnd 6 0. u 6.8n c.74kω c 80p c f.55kω % =4xµ, mω each ML EJB0J6M igure 4 - Applicatin f I84 with type III-B cmpensatr fr a 4A,.8 regulatr AN-6 0

21 Step - llect the system infrmatin such as input and utput vltage and the switching frequency: L ES( in Out ref sc μH 40. 8μ 600kHz I (max) 4A S ) m each It shuld be nted here that the value f the capacitance used in the cmpensatr design must be the small signal value. eramic capacitrs lse sme prtin f their capacitance as their biasing vltage increases. The ML capacitrs which are used in this example have µ nminal capacitance. Hwever, at the biasing vltage and 600kHz their capacitance drps t abut 0.8µ. It is this value that must be used fr all cmputatins related t the cmpensatin. The small signal value may be btained frm the manufacturer s datasheets, design tls r SPIE mdels [4]. Alternatively, they may als be inferred frm measuring the pwer stage transfer functin f the cnverter and measuring the duble ple frequency ( L ) and using equatin () t cmpute the small signal value (refer t Appendix ). Step - Using () and (4) calculate the ples and zer f the pwer stage: L ES π 4. μ. 5μH 9. 7kHz 4. 9MHz π m 0. 8μ Step - Selected crssver frequency t be /6 f the switching frequency: 0 00kHz Step 4 - Select the type f cmpensatr. Since L 0 S / ES, type III-B cmpensatr is suitable fr this applicatin. Step 5 - alculate the ples and zers f the cmpensatr. Using (40) and (4): AN-6

22 Sin70 Z 00kHz 7. 6kHz Sin70 Sin70 p 00kHz 567kHz Sin70 Using (4): Z kHz 8. 8kHz Using (9): p 600kHz / 00kHz Step 6 - alculate the values f the parameters f the cmpensatr. hse Using (): f. π. n k hse f 7. Use (4) t calculate f : f. n. 7. k π. n 7. 6k 98 f Select f 4. 0k. Using (4), f can be calculated: 4. 0k 0. 7 f. 56k ( ) hse f. 55k. Use (5) t calculate : π 00k. 5μ 4. μ k. n hse. 74k. Use (6) t calculate : 6. n π. 74k 8. 8k 6 hse 6. 8n. Use (7) t calculate : p π. 74k 00k 9 hse 80 p. The bde plt f the lp has been sketched in igure 8 which shws the clsed lp system has a crssver frequency f 0 05kHz and the phasemargin f abut 5º. AN-6

23 igure 8 - The bde plt f the lp fr the example with Type III-B cmpensatr 6. nclusin The cntrl lp design based n regular vltage-mde errr-amplifier was discussed fr synchrnus buck cnverter. When electrlytic capacitr r lw perfrmance tantalum capacitrs are used a simple type II cmpensatr can be emplyed. r ceramic, r high perfrmance POS-cap r SP-ap utput capacitrs, a type III cmpensatr is usually required. Althugh I840 and I84 regulatrs were taken as examples in this applicatin nte, the prpsed design methd als applies t applicatins using ther types f buck regulatr/cntrl Is which utilize a vltage-mde errr-amplifier. eferences [] M. Qia, P. Part, and. Amirani, Stabilize the Buck nverter with Transcnductance Amplifier, I-applicatin nte AN-04, 00. [] Ned Mhan, Tre M. Undeland, and William P. bbins, Pwer Electrnics: nverters, Applicatins, and Design, New Yrk: Jhn Wiley & Sns, ISBN: , 00. []. W. Ericksn, D. Maksimvic, undamentals f Pwer Electrnics, New Yrk: Springer Science + Business Media, ISBN: , 00. [4] P. Asadi, Y. hen, P. Part, Optimal Utilizatin f Multi Layer eramic apacitrs fr Synchrnus Buck nverters in Pint f Lad Applicatins, PIM hina, Shanghai, hina, June 00, pp AN-6

24 Appendix A: Designing the Pwer Stage f the Synchrnus Buck nverter The first step in designing a switching D/D cnverter is designing the pwer stage. The pwer stage includes the utput L filter f the cnverter as well as the switches and their drivers. Many factrs are invlved in designing the pwer stage including, efficiency, cst, space, EMI, acceptable utput vltage ripple, transient respnse requirement, etc. The design requirements usually cmpete with each ther. r example, t decrease the utput vltage ripple the designer might increase the value f the inductr and/r capacitr. Increasing the value f the capacitr increases the cst and increasing the value f the inductr can decrease the efficiency and can make the transient respnse slwer. On the ther hand, the utput vltage ripple can be decreased by increasing the switching frequency. Hwever, higher switching frequency may result in less efficiency due t increased switching lsses. Therefre, the designer has t find a trade ff between different design requirements by ging thrugh a few design iteratins. Switching frequency is usually the first parameter which is selected. In selecting the switching frequency different factrs including efficiency, EMI requirements, required clsed-lp bandwidth, etc are invlved. The switching frequency might even be dictated by the system that the cnverter is ging t be a part f. In this appendix the prcedure f designing the pwer stage is briefly discussed with an example. Suppse that the switching frequency as well as the maximum utput current and the input and utput vltages are given. Depending n the maximum utput current the apprpriate switching regulatr is selected. The list f I s integrated switching regulatrs and their specificatins can be fund n I s website. Amng the design requirements, usually the inductr ripple current is given. If nt, starting with a 40% current ripple is reasnable: I 40 % (A) Lripple I Lad _ Max The inductr value can be calculated using the fllwing equatin: L in ut ut (A) I Lripple in S AN-6 4

25 The amplitude f the versht/undersht f the transient respnse f the cnverter as well as the utput vltage ripple determine the value f the utput capacitr. The amplitude f the switching ripple is usually much smaller than the permissible value if an apprpriate utput capacitr cmbinatin is utilized. The minimum required amunt f utput capacitr is given by the fllwing equatin: _ Min L I Lad _ Step ut ut _ Max (A) where I Lad _ Step is the maximum step lad in Amps and ut _ Max is the maximum permissible utput vltage change due t transients/switching. Equatin (A) is based n having ideal utput capacitrs (n ES) and infinite cntrl-lp band-width. The required amunt f utput capacitance is usually higher than the value given by (A) especially when the utput capacitrs have a cnsiderable amunt f ES. Hwever, the value calculated by (A) is a gd starting pint t chse the utput capacitr. Suppse the designer intends t use a type f capacitr with the value f. If the ES f the capacitr culd be neglected, the number f capacitrs which is required wuld have been: N Min ( ES 0 ) (A4) _ Min E Hwever, if each capacitr has an ES equal t ES E, the minimum number f required capacitrs t have a satisfactry transient respnse is: N ES L I E ut Lad _ Step Min I Lad _ Step ( ESE E ) (A5) ut _ Max E L ut _ Max ut Usually the first integer which is greater than the value given by (A5) shuld be cnsidered. r mre infrmatin abut (A5) refer t [A]. The input capacitr f the cnverter shuld be able t handle the input current ripple: E I in _ ripple I D ( D ) (A6) Lad _ Max where D is the duty cycle f the cnverter. If the input capacitr is cmprised f multiple capacitrs cnnected in parallel, we have: in N (A7) in E _in AN-6 5

26 If the current ripple that each f the capacitrs can handle is given by I number f capacitrs which shuld be parallel t frm I in are: _ ripple _ max, then the in _ ripple Nin (A8) I _ ripple _ max It is wrth mentining that values f capacitrs change as temperature, bias vltage, and perating frequency change. r example ML capacitrs lse a cnsiderable prtin f their capacitance as their bias vltage is increased. Therefre, in all calculatins thrughut this dcument the effective value f the capacitrs at the given perating cnditin shuld be cnsidered. Design example f pwer stage nsider the fllwing data is given: I I I in ut S KHz Lad _ Max Lad _ Step ut _ Max Lripple A 6A 54m 4. 55A (A9) Using (A) the value f the inductr is calculated: L 560nH (A0) K Using (A) the minimum required utput capacitance is calculated: 560n 6 _ Min 0μ (A). 8 54m Suppse the fllwing capacitrs are ging t be used: E ES 0μ E m (A) Since E _ Min, it seems that ne capacitr shuld be enugh, hwever using (A5) suggests: AN-6 6

27 N Min m n 6 6 ( m 0μ). 7 (A) 54m 0μ 560n 54m. 8 Therefre, capacitrs with the specificatins given in (A) shuld be used: 0μ 660μ m ES 6m (A4) Suppse the capacitrs which are ging t be used in input side are.µ capacitrs which can handle a maximum f.a. The input current ripple is: I. 8 / (. 8 / ) 4. Arms (A5) in _ ripple 8 N in 4. 8 /. 4. (A6) Therefre, the minimum numbers f capacitrs which shuld be paralleled at the input are 4 capacitrs. eferences: [A]. Qia, J. Zhang, P. Part, and D. Jauregui, Output apacitr mparisn fr Lw ltage High urrent Applicatins, in Prc. IEEE 5 th Pwer Electrnics Specialists nference, Aachen, Germany, June 004, pp AN-6 7

28 Appendix B: Sme Special ases f mpensatr Design The guidelines prvided earlier in this dcument n cmpensatr design are general guidelines which result in apprpriate values fr the cmpensatr parameters in mst cases. Hwever, smetimes fine tuning might be desirable. That is, the designer might want t adjust the lcatins f the zers and ples f the cmpensatr (by a few design iteratins) t get better/ptimized results. There might be extreme cnditins where fine tuning is necessary. In this appendix, ne extreme cnditin in which the designer must adjust the cmpensatin is discussed by an example. In sme extreme cnditins, the values f inductr and capacitr in the pwer stage may becme t large s that the resnance frequency, L, becmes t lw cmpared t the crss ver frequency ( 0 ). In such cnditins, if the cmpensatr type III-B is used, the resulting bde-plt f the lp might nt be apprpriate. Therefre, sme mdificatins in the design prcedure are required. Such cases are demnstrated by an example. nsider a synchrnus buck cnverter with the parameters given by (B). The designer has been cnservative in keeping the inductr current ripple and utput vltage ripple/transient very lw. in 6 ut. 5 ref 0. 7 sc. 8 L 4. 7μH L m 9 47μ ES( ) m each S 600KHz IO _ Max A 0 00kHz (B) At the specified utput vltage, the effective value f each utput capacitr is abut 6µ. Therefre: AN-6 8

29 L 6. khz (B) π 4. 7μH 9 6μ. M ES π 6μ m (B) Since L 0 S / ES, type III-B cmpensatr is used. Using (9)-(4) the ples and zers f the cmpensatr are calculated as fllws: Sin70 Z 00kHz 7. 6kHz (B4) Sin70 Sin70 p 00kHz 567kHz (B5) Sin70 Z kHz 8. 8kHz (B6) p 600kHz / 00kHz (B7) Nw the values f the parameters f the cmpensatr are calculated. If the value f.n is selected fr f, the fllwing values are resulted: f π. n k (B8) 7 4. k π. n 7. 6k 0 f (B9) π 00k 4. 7μ 44μ. 8. 5k (B0) 6. n 0. n π 8. 8k. 5k 8 (B) p π. 5k 00k 4 (B) It is nticed that the value f is relatively large (>0kΩ) whereas and are relatively small. If a larger value fr f had been chsen, mre reasnable values fr,, and wuld have been resulted. Apart frm this, cnsidering the bde plt f the lp, which is btained by simulatin and is presented in igure B, it is clear that the behavir f the phase f the lp is nt apprpriate. The phase drps t belw 0º at abut 9kHz which makes the system cnditinally stable. AN-6 9

30 It shuld be nted that the bde-plt sketched in igure B is based n the average mdel fr the buck cnverter. Therefre, it is valid nly up t half f the switching frequency Gain (db) , ,000 0,000 00,000,000,000 requency (Hz) Phase (Degree) igure B - The bde plt f the lp fr the example with Type III-B cmpensatr shws a bandwidth f 95.7kHz and a phase margin f 50º The reasn fr the phase drp at abut 9kHz is that the ple and zer selectin has been dne t secure enugh phase-margin at the lp crss-ver frequency. The crss-ver frequency is much higher than the resnance frequency ( L r duble-ple frequency). nsequently, bth zers f the cmpensatr are abve the resnance frequency where the duble ple causes 80 degrees phase-drp. Technically, it is required t have the zers at abut L r even at lwer frequencies. Therefre, when the prcedure f type III-B cmpensatr design is fllwed, if the calculated zers f the cmpensatr are bth abve L, mdificatins in the prcedure are required as fllws: - Design fr lwer lp Bandwidth (/0 f the switching frequency). - Place the zers f the cmpensatr accrding t type III-A cmpensatr design prcedure. There are tw reasns t design fr lwer lp bandwidth. irst, due t relatively large value f the selected utput capacitrs, usually there is n need t design fr a high lp AN-6 0

31 bandwidth t achieve satisfactry transient respnse. Secnd, when the resnance frequency f the regulatr is much lwer than the designed lp bandwidth, a relatively high gain-bandwidth is demanded frm the errr amplifier. Therefre, t avid running int the gain-bandwidth-prduct limitatin f the errr amplifier, it is recmmended t design fr a lwer lp bandwidth. In this case, we design the lp fr a BW f 60kHz. Placing the zers f the cmpensatr accrding t the type III-A cmpensatr design prcedure, mves the zers t lwer frequencies. This, in turn, reduces the gain at lw frequencies. Hwever, accrding t igure B, the lw-frequency gain is relatively large (G(00Hz)>60dB), therefre, reducing the lw-frequency gain is acceptable. Equatins (B5) r (4) can still be used t calculate the lcatin f the secnd ple f the cmpensatr. The ples and zers f the cmpensatr which is ging t be designed are: Z 6. khz (B) p 40kHz (B4) Z khz 4. 65kHz (B5) p 600kHz / 00kHz (B6) The design prcedure is started with can be calculated: f f f f. n 5. 5k 4. 4k. 4k. 7n 4p f. n. Nw, the values f the cmpnents (B7) With the abve cmpnent values fr the cmpensatr, the bde plt f the lp is measured and presented in igure B. The bde plt shws that the phase-dip arund 9kHz des nt g belw 45º and the phase margin has increased by 9º. AN-6

32 igure B - The bde plt f the lp fr the example with mdified Type III cmpensatr shws a bandwidth f 6kHz and a phase margin f 59º AN-6

33 Appendix : Lp espnse Measurement A prperly measured lp respnse will allw measurement f cntrl bandwidth and phase margin. In additin, it allws estimatin f actual r effective utput capacitance in a circuit. ntrl bandwidth indicates the speed f the system in respnding t lad transients and phase margin is a very imprtant indicatin f rbustness f stability f the clsed lp system. A PWM D-D cnverter exhibits time-varying effects abve half f the switching frequency and any measurements at such frequencies have n basis fr cmparisn with averaged mdel designs and predictins which d nt accunt fr the time-varying effects. This implies that it des nt serve any purpse t measure the lp respnse at frequencies appraching r exceeding half f the switching frequency. At very lw frequencies and at very high frequencies, the measurement is susceptible t nise, because f the very high and very lw lp gains respectively. r typical values f L and used in POL designs, the L resnant ples lie between khz and 0 khz, and any lp measurement must clearly shw this regin. r a switching frequency f 600 khz, used in I s integrated buck regulatr designs (SupIBuck TM ) fr mst POL applicatins, lp respnse measurement in the range f khz -50 khz is sufficient. igure shws the general schematic fr a family f SupIBucks. This schematic is used t shw hw the lp respnse in measured. The measurement technique can similarly be used fr any ther I s SupIBucks. The three test pints (A, B, and ) which are used fr lp-respnse measurement have been indicated by slid circles. T measure the lp respnse the fllwing steps shuld be taken: Using a netwrk analyzer, apply a 5m-0m perturbatin signal between test pints A and B. Set up the netwrk analyzer t measure v(b)/v(a). Set the frequency range f measurement between khz and 50 khz. Measure the cntrl bandwidth as the frequency at which the lp gain respnse crsses 0 db. AN-6

34 Measure the phase margin as the lp phase respnse at the lp gain crssver frequency. 8 Seq./DDQ u in u 8 4 U Seq/p B OMP AGnd 4 Enable Bt I84x/x 0 in SW 0 PGnd L u ut t SS Oset cc PGd AGnd + + cc- cc u 5 Q A B igure - The typical schematic f a family f I s SupIBucks and the assciated test pints which are used fr frequency respnse measurements. igure shws the result f a typical frequency respnse measurement. The figure shws that the cntrl lp bandwidth is 00.98kHz and the phase-margin is º. ntrl bandwidth=00.98 khz Phase margin = igure - The result f lp frequency-respnse measurement fr a typical POL applicatin which is the amplitude and phase f v(b)/v(a) versus frequency AN-6 4

35 Ideally the lp frequency respnse shuld nt depend n the utput current f the rail. Hwever, due t the dead-times f the switches and sme ther factrs, the frequency respnse changes with lad current t sme extent. Usually the lp respnse shuld be measured at nminal current f the rail. In additin, at the current that the lp respnse is measured the cnverter must perate withut jitter. Anther frequency respnse which prvides useful infrmatin is the pwer stage frequency respnse. T measure the frequency respnse f the pwer stage the fllwing prcedure shuld be fllwed: Using a netwrk analyzer, apply a 5m-0m perturbatin signal between test pints A and B. Set up the netwrk analyzer t measure v(b)/v(). Set the frequency range f measurement between khz and 50 khz. Measure the resnant frequency f L f the L utput filter. Measure the amplitude f the frequency respnse at lw frequencies (G_Pwer_Stage_D). This value is measured in db scale. With L knwn, cmpute the effective value f utput capacitance using (). Use () t estimate the amplitude f the ramp signal in the mdulatr. () 4π f L L sc in () 0 G _ Pwer _ Stage _ D ( ) 0 Using () the effective / small-signal value f the utput capacitance is btained. This value shuld be used in all cmputatins related t cmpensatr design. Obtaining the effective value f the utput capacitance is especially imprtant when ceramic capacitrs are used, since ceramic capacitrs cnsiderably lse their capacitance as bias vltage is increased. The small signal value f the utput capacitrs may als be btained frm the manufacturer s datasheets and design tls. The amplitude f the ramp signal, sc, is als required in the prcess f cmpensatr design. This value can be btained frm the datasheet as well. igure shws the frequency respnse f a typical pwer stage. AN-6 5

36 igure - The frequency respnse f a typical pwer stage shwing the resnance frequency If, fr instance, a µh inductr is used, the effective value f the utput capacitance is: 04μ () 4π (5.6kHz) μh igure shws that at lw frequencies the gain f the pwer stage is abut 6.98dB. Therefre, assuming the input vltage is, the amplitude f the ramp signal will be: sc. 7 (4) ( ) 0 AN-6 6