The PWM and Analog Dimming Solution to Implement 0.05% to 100% Dimming Range Based on UCC28810/11 Constant Current Buck

Transcription

1 Applicat Reprt SLUA701 January 2014 The PWM and Analg Dimmg Slut t Implement 0.05% t 100% Dimmg Range Based n UCC28810/11 Cnstant Current Buck Richard Yang Lv Jian Cha Pwer FAE ABSTRACT In this paper, the cmbed dimmg slut (PWM and 1- t 10-V analg) based n the UCC28810/11 device is prvided t meet tday s wider dimmg range specificat fr the LED ceilg lamp applicat. This slut is different frm the tradital 10% t 100% PWM dimmg, and it divides the dimmg range t tw parts: fr the first part, 5% t 100% LED current dimmg will be implemented by 1- t 10-V analg dimmg signal; fr the secnd part, 0.05% t 5% LED current dimmg will be implemented by 1% t 100% PWM dimmg signal. Cntent 1 Intrduct Prciple Analysis Based n UCC28810/11 Buck Cnstant Current Slut The Orig f UCC28810/11 Cnstant Current Buck Ideal Operat Analysis f UCC28810/11 Device Cnstant Current Buck Practical UCC28810/11 Device Cnstant Current Prciple Analysis Cnstant Current Analysis fr the Tradital Operat The Imprved UCC28811 Cnstant Output Current Slut The PWM and Analg Dimmg Design Analysis The 5% t 100% Analg Dimmg Slut The Imprved 0.05% t 5% PWM Dimmg Slut The Practical Design Example % t 100% Analg Dimmg and 0.05% t 5% PWM Dimmg Design Result % t 100% Analg Dimmg Design Result % t 5% PWM Dimmg Design Measurement Result % t 100% Analg Dimmg Design Measurement Result fr the Output Current Cncluss References Figures Figure 1. Internal Blck Diagram f the UCC28810/11 Device and Its Multiplier Funct... 3 Figure 2. Internal 1.7-V Creatg Funct fr the UCC28810/11 Device... 3 Figure 3. Basic Buck Cnstant Current Slut with the Internal 1.7-V Reference... 4 Figure 4. Wavefrm Analysis fr the Steady Operat... 6 Figure 5. Slut fr the Tight Output Current Cntrl When Output Vltage Varies... 7 Figure 6. UCC28810/11 Analg Dimmg Slut... 8 Figure 7. Imprved Slut fr the UCC28810/11 PWM Dimmg

2 Figure 8. Curve f Frequency versus L Figure 9. Calculated Output Current When Analg Dimmg Figure 10. Calculated Frequency Curve When V anlg Out Vltage Varies Figure 11. ISNS P Vltage Cmparisn Between With Imprved Circuit and Withut Imprved Circuit Figure 12. Circuit t Imprve Analg Dimmg Perfrmance Figure 13. Spice Simulat Result t Meet the 180-ns Delay Specificat Figure 14. Measured Wavefrms fr the 5% t 100% Analg Dimmg Cntrl Figure 15. Figure 16. Operat Frequency Curve Cmparisn Between Measurement and Calculat19 Curve f Output Current Cmparisn Between Measurement and Calculat When Analg Dimmg is Cnducted Figure 17. Measured Wavefrms When PWM Dimmg is Cnducted Figure 18. Measured Output Current Wavefrms When Analg Dimmg is Cnducted Intrduct With the creasg strgent dimmg cntrl tendency fr the ceilg lamp, the sgle tradital analg dimmg r PWM dimmg cannt meet the current market requirement. Instead, the cmbed mde f PWM and analg dimmg is a gd chice. Hwever, deeper and wider dimmg remas the challenge due t the fluences f parasitic effect n the junct capacitr fr the MOS and utput dide. An addital challenge is meetg the gd learity specificat between the LED utput current and dimmg signal. In this paper, the cmbed analg dimmg and PWM dimmg slut based n the UCC28810/11 device is prvided t meet this specificat. Due t a cntribut f pwer-factr crrect (PFC) utput r Flyback utput the frnt f AC put, this paper the UCC28810/11 device will be prvided by the DC put vltage. Fr a better understandg f this slut, this paper prvides the detail theretical analysis and practical design with extensive experiment data. This paper prves that the design calculat matches with the experiment very well. 2 The PWM and Analg Dimmg Slut t Implement 0.05% t 100% Dimmg Range Based n UCC28810/11 Cnstant Current Buck

3 2 Prciple Analysis Based n UCC28810/11 Buck Cnstant Current Slut 2.1 The Orig f UCC28810/11 Cnstant Current Buck T implement cnstant current, the lgic circuit side the UCC28810/11 device must be changed due t the fluence f the ternal multiplier (see Figure 1). Because the utputclamped vltage f this multiplier is 1.7 V, we can create a simple external circuit t let the multiplier stabilize at 1.7 V; that is, the ternal reference vltage f 1.7 V can be created this way. Figure 1. Internal Blck Diagram f the UCC28810/11 Device and Its Multiplier Funct The ternal reference vltage f 1.7 V can be created as shwn Figure 2. Settg the external circuit parameters t make the utput f current reference generatr saturated The utput will be 1.7V Figure 2. Internal 1.7-V Creatg Funct fr the UCC28810/11 Device The PWM and Analg Dimmg Slut t Implement 0.05% t 100% Dimmg Range Based n UCC28810/11 Cnstant Current Buck 3

4 Figure 3. Basic Buck Cnstant Current Slut with the Internal 1.7-V Reference 2.2 Ideal Operat Analysis f UCC28810/11 Device Cnstant Current Buck The LED utput current will be 0.5 times the peak current gg thrugh the BUCK MOS due t the critical perat mde fr the UCC28810/11. As mented Sect 2.1, the ternal reference vltage will be 1.7 V, and then the current thrugh MOS will be: 1. 7 I PP = Rs (1) Then the utput current will be: I = Rs (2) The turn-n time and turn-ff time will be T n 2 I L = V V T ff 2 I = V L (3) The switchg frequency will be: F sw = ( V V ) 2I V L V (4) 4 The PWM and Analg Dimmg Slut t Implement 0.05% t 100% Dimmg Range Based n UCC28810/11 Cnstant Current Buck

5 3 Practical UCC28810/11 Device Cnstant Current Prciple Analysis 3.1 Cnstant Current Analysis fr the Tradital Operat In practical perat, the resnance between the junct capacitr f the MOS and Dide and the ductance f the BUCK ductr ccurred when the current f BUCK ductr decreased t zer. Durg this prcess, the V DS f MOS decreases gradually. Hwever, this vltage may cme t zer at sme certa put cndit shwg that the ZVS cndit is realized cmpletely. Hwever, it must be pted ut that the negative current f ductr current will be discvered due t this resnance mechanism. This causes the ttal average current thrugh the BUCK ductr t vary slightly frm the ideal perat BUCK current. This variance means the practical LED current frmula must be recalculated based n this resnance cnsiderat. Due t the cmplicated frmula f junct capacitance f the MOS and Dide, it can be defed as C ss fr simplificat but nt affectg ur analysis result. S the ductance f the BUCK ductr can be defed as L. We can bta Equat 5, as referenced Figure 4: Durg the stage f T d_ff: The junct capacitr f the MOS and Dide will be discharged gradually, which makes the current thrugh ductr g reverse when the BUCK ductr current decreases t zer. The vltage f MOS will be: V DS _ MOS = V V + V cs( ω t) 1 ω = (5) L C ss The T d_ff stage will cme t the end when the vltage f MOS decreases t V V, (see Figure 4), then we have: π T _ = (6) d ff 2ω The PWM and Analg Dimmg Slut t Implement 0.05% t 100% Dimmg Range Based n UCC28810/11 Cnstant Current Buck 5

6 Figure 4. Wavefrm Analysis fr the Steady Operat Accrdg t the similar analysis, the fllwg frmulae can be btaed as: V _ n = (7) Td 1 S the entire peridic can be btaed as: ( V V ) ω L Tn = 1. 7 (8) 1 Rs V V T ff L = 1. 7 (9) 1 Rs V Ts T + T + T + T = (10) d _ n1 d _ ff The switchg frequency can be btaed as: d _ n1 d _ ff 1 F sw = π + 2ω ( V V ) V ω Rs V L V Rs L V (11) The ultimate LED utput current can be btaed as: π V V V I = V ω C (12) ss Rs Rs π V 1.7 L 1.7 L ω ω ( ) ω 2 V V Rs V V Rs V 6 The PWM and Analg Dimmg Slut t Implement 0.05% t 100% Dimmg Range Based n UCC28810/11 Cnstant Current Buck

7 Frm Equat 12, it can be seen that LED current is nt dependent n the sgle parameter; stead, it is fluenced by several parameters such as Rs, V, V, L, and C ss. In practical design, we can knw the parameters f Rs, L, and C ss, but V and V must be evaluated. Frm Equat 12, we can see LED utput current is mimally affected with sme certa put vltage variat. Hwever, the LED current will be affected when utput vltage is varied. S, the cmpensat circuit must be determed t tightly stabilize the utput current when the LED vltage changed. 3.2 The Imprved UCC28811 Cnstant Output Current Slut Because a variat utput vltage affects LED current, the simple cmpensat slut is prpsed by cnnectg a large-value resistr, R L, frm the ISNS p f the UCC28811 device t the negative termal f the LED. Figure 5. Slut fr the Tight Output Current Cntrl When Output Vltage Varies Shwn as Figure 5, the ttal utput current can be calculated by Equats 13 and 14: The vltage f the ISNS p f the UCC28810/11 device will be: Visns ( V V ) Then the LED utput current can be btaed as: m = Ipp Rs + (13) R m R + R L The PWM and Analg Dimmg Slut t Implement 0.05% t 100% Dimmg Range Based n UCC28810/11 Cnstant Current Buck 7

8 I = 0.5 Ipp Ipp = ( V V ) R Rm + RL Rs ( Ipp + V ω C ) m ss π + 2ω π V + 2 V V + Ipp L V ( V V ) ω ( V V ) V V ω (14) The switchg frequency will be: Fsw = π + 2ω V 1 + Ipp L V ( V ) ( ) V ω V V V (15) 4 The PWM and Analg Dimmg Design Analysis 4.1 The 5% t 100% Analg Dimmg Slut Per the nrmal requirement, a wide range f analg dimmg frm 5% t 100% must be met. Figure 6 is shwn t achieve this. D1 and R2 are added t cmpensate the ISNS p f the UCC28810/11 device, and the external varied analg signal is prvided t change the LED utput current. Figure 6. UCC28810/11 Analg Dimmg Slut 8 The PWM and Analg Dimmg Slut t Implement 0.05% t 100% Dimmg Range Based n UCC28810/11 Cnstant Current Buck

9 Referrg t Figure 6, if we designate resistr R8 as R L, resistr R2 as R dim, resistr R7 as Rs, and the external 5-V supply as V ang, we can have the fllwg frmulae: The LED utput current when cnductg analg dimmg can be btaed as: ( ) = 0.5 Ipp( V ) 0.5 Ipp( ang) I V ang ang Ipp V ( + V ω C ) ss π + 2ω ( V V ) V π V + 2 V V + Ipp V ω ( Vang V f 1.7) RL 1.7 Rdim ( ) = ( V ang. 7 + V f ) ang Rs L V ( ) ω ( ) ang V V V 1 (16) The switchg frequency can be btaed as fllws: Fs ( V ) ang = π + 2 ( V V ) V ω + Ipp V L V ω ( ang ) ( V V ) V (17) In practical applicat, the external V ang will be prvided by the micrchip, which will prduce the utput vltage varied frm V f t 5 V. Durg this range, the utput current will be le with V ang, and the le rati is maly dependent n R L and R dim. We can achieve the ptimized le rati accrdg t the design specificat. The experiment verified that the 5% t 100% analg dimmg can be easy t implement when the external V ang varied frm 5 V t V f. Actually, cncern abut the fluence f V f is nt necessary, because very little vltage variat ccurs durg the actual 0 C-t-75 C temperature variat if a lw frward dide, such as BAT54, is chsen. 4.2 The Imprved 0.05% t 5% PWM Dimmg Slut First f all, nte that the rigal PWM dimmg slut shwn Figure 7 (Q4, R14, and R15) will nt wrk well due t a flickerg issue. This issue is primarily caused because the deep PWM dimmg range is extremely wide, therefre the UCC28810/11 device cannt easily detect the ISNS signal due t the fluence f the junct capacitr f MOS. The junct capacitr will nt let the UCC28810/11 device have the stable cntrl if the peak vltage f ISNS dmates the entire perid f sense vltage recgnized by the cntrller. Figure 7 shws the imprved slut. The PWM and Analg Dimmg Slut t Implement 0.05% t 100% Dimmg Range Based n UCC28810/11 Cnstant Current Buck 9

10 Figure 7. Imprved Slut fr the UCC28810/11 PWM Dimmg In Figure 7, the circuit f Q1, Q3, R13, and Q6 is added t mve ut the peak vltage f ISNS at the begng f its risg stage. Extensive experimentat prves that this circuit wrks well t prvide gd dimmg perfrmance frm 0.05% t 100% dimmg range even acrss a wide temperature range. 5 The Practical Design Example T verify the previus slut, see the fllwg table f design specificats. Fr the practical applicat f this slut: The put is always 90 VAC t 130 VAC. Nnislated slut is chsen. PFC is used. PFC utputs apprximately 200 VDC. The design parameters are shwn as the fllwg table: 10 The PWM and Analg Dimmg Slut t Implement 0.05% t 100% Dimmg Range Based n UCC28810/11 Cnstant Current Buck

11 Table f Design Specificat Dimmg design specificat: PWM dimmg and analg dimmg are prvided by the external signals. Hwever, 0 t 10 V will be cnverted t the 2- t 5-V analg signal thrugh the micrchip, and 1% t 100% PWM dimmg signal culd have the direct cntrl f the UCC28810/11 device. Accrdg t the design requirement, the analg dimmg is as described Sect 4.1, and PWM dimmg is as described Sect 4.2. The detail design prcedure is presented as fllws. Step 1: Chse the ductance f the BUCK ductr accrdg t the efficiency specificat. T achieve the 94% efficiency, the mimum perat frequency f 30K is chsen. Given the ttal MOS and Dide junct capacitance f 200 pf, V is with 200 VDC, V is with 130 V, Rs is first chsen with 3.7R. The frmula and curve f frequency versus L can be btaed as fllws: Fs ( L) = π + 2 V 1 L Cc L V ( V V ) Rs ( V V ) V L Cc (18) The curve f frequency versus L is shwn frm Figure 7. The PWM and Analg Dimmg Slut t Implement 0.05% t 100% Dimmg Range Based n UCC28810/11 Cnstant Current Buck 11

12 Figure 8. Curve f Frequency versus L It can be seen that the value f ductance f the BUCK ductr must be chsen as 3.0 mh. S Step 1, we bta: Rs = 3.7R L = 3.0 mh Step 2: Chse the analg dimmg resistr R dim and the ISNS buffer resistr R L. Accrdg t the analg dimmg design bjective, a 2-V t 5-V analg signal will make the utput current vary frm 20 t 10 ma. If we first chse R L as 910 R, then R dim can be slved frm Equat 19: 10 ma = 0.5 Ipp 0.5 ( 5 2) ( Ipp + V ω C ) ss π + 2ω π V + 2 V V + Ipp L V ( V V ) ω ( V V ) V V ω RL 1.7 Rdim Ipp = (19) Rs The value f R dim can be slved as 1.9 K if the frward vltage f dimmg dide is 0.3 V. As a result, the analg dimmg curve can be pltted as shwn Figure The PWM and Analg Dimmg Slut t Implement 0.05% t 100% Dimmg Range Based n UCC28810/11 Cnstant Current Buck

13 Figure 9. Calculated Output Current When Analg Dimmg Check the perat frequency durg analg dimmg accrdg t Equat 20: Fs( Vang) = π + 2ω ( ) Ipp Vang 1.7 = ( V V ) V π V + 2 V V + Ipp Vang ω ( Vang Vf 1.7) R Rs dim L V V V ( ) ω ( ) R L V (20) Figure 10. Calculated Frequency Curve When V anlg Out Vltage Varies The PWM and Analg Dimmg Slut t Implement 0.05% t 100% Dimmg Range Based n UCC28810/11 Cnstant Current Buck 13

14 The frequency can g up t 300K when cmg t 5% dimmg, which means it will be gd fr PWM dimmg, especially 1% PWM dimmg. But efficiency may be lwer. S step 2, we bta the fllwg: R L = 910 R R dim = 1.9 K Step 3: Chse the parameters fr the PWM dimmg imprvement circuit Due t the fluence f the junct capacitr f the MOS and Dide, the UCC28810/11 device may detect the wrng frmat n the ISNS p when cmg t 5% dimmg (see Figure 10). Figure 11. ISNS P Vltage Cmparisn Between With Imprved Circuit and Withut Imprved Circuit In practical design, we measure the wavefrm f ISNS t determe hw much delay must be prduced by the imprved circuit (refer t Figure 11). S, it is recmmended t make a simple spice simulat regardg the setup f the C13, R51, and R46 circuit. 14 The PWM and Analg Dimmg Slut t Implement 0.05% t 100% Dimmg Range Based n UCC28810/11 Cnstant Current Buck

15 Figure 12. Circuit t Imprve Analg Dimmg Perfrmance Fr example, if we need t prduce a 180-ns delay fr the abve-mented circuit, the precedg parameters can meet the requirement; Figure 12 shws its wavefrm. Figure 13. Spice Simulat Result t Meet the 180-ns Delay Specificat Step 4: Design PWM dimmg circuit. PWM dimmg is very easy t implement because the UCC28810/11 device prvides the drive turn-ff funct when Vsense is latched dwn t 0.57 V. Shwn as Q4 Figure 7, PWM dimmg cntrl can be dne with a simple external transistr cnnected t the Vsense p f the UCC28810/11 device. Hwever, the external duty cycle D f the PWM signal will prduce the dimmg perfrmance with a duty cycle f 1-D fr this slut The PWM and Analg Dimmg Slut t Implement 0.05% t 100% Dimmg Range Based n UCC28810/11 Cnstant Current Buck 15

16 6 5% t 100% Analg Dimmg and 0.05% t 5% PWM Dimmg Design Result 6.1 5% t 100% Analg Dimmg Design Result Analg dimmg is critically imprtant because the utput current must be very stable and nt have any flickerg issue. Fr a better understandg f this design, the wavefrms f ISNS p vltage f the UCC28810/11 device and the current f the BUCK ductr are vestigated. These wavefrms must be stable durg the entire dimmg prcess. Wavefrms f channel 2 ISNS p vltage f the UCC28810/11 device Wavefrms f channel 4 Current f the BUCK ductr 10-mA utput (V_analg = 4.99 V, Fsw = 171K) 20-mA utput (V_analg = V, Fsw = 134K) 30-mA utput (V_analg = V, Fsw = K) 40-mA utput (V_analg = 4.4 V, Fsw = 101K) 16 The PWM and Analg Dimmg Slut t Implement 0.05% t 100% Dimmg Range Based n UCC28810/11 Cnstant Current Buck

17 50-mA utput (V_analg = V, Fsw = 84K) 60-mA utput (V_analg = V, Fsw = 78K) 70-mA utput (V_analg = V, Fsw = 68.5K) 80-mA utput (V_analg = V, Fsw = 61.73K) 90-mA utput (V_analg = V, Fsw = 57.8K) 100-mA utput (V_analg = V, Fsw = 53.76K) The PWM and Analg Dimmg Slut t Implement 0.05% t 100% Dimmg Range Based n UCC28810/11 Cnstant Current Buck 17

18 120-mA utput (V_analg = V, Fsw = 45.8K) 140-mA utput (V_analg = V, Fsw = 40.32K) 160-mA utput (V_analg = V, Fsw = 35.8K) 200-mA utput (V_analg = 2 V, Fsw = 30K) Figure 14. Measured Wavefrms fr the 5% t 100% Analg Dimmg Cntrl Frm the measured wavefrms Figure 14, we can see the imprvement n the vltage f the ISNS p f the UCC28811 device. The rigal peak vltage n this p disappears, which keeps the lp stable durg the fllwg PWM dimmg. Additally, we must verify the design calculat frmula regardg the perat frequency. In Figure 15, Fsw(Vanlg) represents the calculat result, and Fs_measure (Vanlg) represents the measurement result. It can be seen that the calculat matches very well with the measurement. 18 The PWM and Analg Dimmg Slut t Implement 0.05% t 100% Dimmg Range Based n UCC28810/11 Cnstant Current Buck

19 Figure 15. Operat Frequency Curve Cmparisn Between Measurement and Calculat Because analg dimmg is critical, the dimmg curve must be lear with the signal f Vanlg. Figure 16 shws the cmparisn between the practical measurement and calculat result. In Figure 16, I(Vanlg) represents the calculat result based n Equat 16. I_measure (Vanlg) represents the measurement result abve. Figure 16. Curve f Output Current Cmparisn Between Measurement and Calculat When Analg Dimmg is Cnducted The PWM and Analg Dimmg Slut t Implement 0.05% t 100% Dimmg Range Based n UCC28810/11 Cnstant Current Buck 19

20 It can be seen that the calculat matches very well with the measurement % t 5% PWM Dimmg Design Measurement Result The 0.05% t 5% PWM dimmg starts after the analg dimmg cmes t 5% dimmg level fr this slut. The fllwg measured wavefrms present the PWM dimmg perfrmance. Wavefrms f channel 1 Output current when PWM dimmg Wavefrms f channel 2 ISNS p vltage f the UCC28811 device Wavefrms f channel 3 UCC28811 device put PWM dimmg signal Wavefrms f channel 4 Current f the BUCK ductr 1% PWM dimmg (I = 67 µa) 2% PWM dimmg (I = 220 µa) 5% PWM dimmg (I = 490 µa) 10% PWM dimmg (I = 897 µa) 20 The PWM and Analg Dimmg Slut t Implement 0.05% t 100% Dimmg Range Based n UCC28810/11 Cnstant Current Buck

21 20% PWM dimmg (I = 1.9 ma) 40% PWM dimmg (I = 3.95 ma) 50% PWM dimmg (I = 7.87 ma) 60% PWM dimmg (I = 5.88 ma) 70% PWM dimmg (I = 7.07 ma) 80% PWM dimmg (I = 8.14 ma) The PWM and Analg Dimmg Slut t Implement 0.05% t 100% Dimmg Range Based n UCC28810/11 Cnstant Current Buck 21

22 90% PWM dimmg (I = 9.07 ma) 99% PWM dimmg (I = 9.73 ma) Figure 17. Measured Wavefrms When PWM Dimmg is Cnducted It can be seen that the dimmg perfrmance is very gd due t the cntribut f imprved circuit fr the analg dimmg % t 100% Analg Dimmg Design Measurement Result fr the Output Current The utput current must be measured durg the analg dimmg prcess. Durg this prcess, the dimmg perfrmance is very gd due t the cntribut f imprved circuit fr the analg dimmg. Wavefrms f channel 1 Output current when analg dimmg Wavefrms f channel 2 Current f the BUCK ductr Wavefrms f channel 3 ISNS p vltage f the UCC28810/11 device 22 The PWM and Analg Dimmg Slut t Implement 0.05% t 100% Dimmg Range Based n UCC28810/11 Cnstant Current Buck

23 10-mA utput with analg dimmg 50-mA utput with analg dimmg 100-mA utput with analg dimmg 150-mA utput with analg dimmg Figure 18. Measured Output Current Wavefrms When Analg Dimmg is Cnducted 7 Cncluss This paper prvides the entire analysis, design, and experiment data regardg the cmbe dimmg mde design. The result prves that the design idea is feasible fr practical applicat. 8 References [1] UCC28811 LED Lightg Pwer Cntrller [2] Usg the UCC28810 EVM-003 User s Guide [3] Usg the UCC28810 EVM-002 A 0.9 A Cnstant Current Supply with PFC fr 100-W LED The PWM and Analg Dimmg Slut t Implement 0.05% t 100% Dimmg Range Based n UCC28810/11 Cnstant Current Buck 23

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