±15kV ESD Protected, +3V to +5.5V, 1µA, 250kbps, RS-232 Transmitters/Receivers

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1 ±kv ESD Protected, V to.v, µa, 0kbps, RS- Transmitters/Receivers ICLE, ICLE, ICLE, ICLE, ICL4E, ICL4E The Intersil ICLxxE devices are.0v to.v powered RS- transmitters/receivers which meet ElA/TIA- and V.8/V.4 specifications, even at =.0V. Additionally, they provide ±kv ESD protection (IEC Air Gap and Human Body Model) on transmitter outputs and receiver inputs (RS- pins). Targeted applications are PDAs, Palmtops, and notebook and laptop computers where the low operational, and even lower standby, power consumption is critical. Efficient on-chip charge pumps, coupled with manual and automatic power-down functions (except for the ICLE), reduce the standby supply current to a µa trickle. Small footprint packaging, and the use of small, low value capacitors ensure board space savings as well. Data rates greater than 0kbps are guaranteed at worst case load conditions. This family is fully compatible with.v-only systems, mixed.v and.0v systems, and.0v-only systems. The ICL4XE are -driver, -receiver devices that provide a complete serial port suitable for laptop or notebook computers. Both devices also include noninverting always-active receivers for wake-up capability. The ICLE, ICLE and ICL4E, feature an automatic power-down function which powers down the on-chip power-supply and driver circuits. This occurs when an attached peripheral device is shut off or the RS- cable is removed, conserving system power automatically without changes to the hardware or operating system. These devices power up again when a valid RS- voltage is applied to any receiver input. Table summarizes the features of the devices represented by this data sheet, while Application Note AN98 summarizes the features of each device comprising the ICLxxE V family. Features ESD Protection for RS- I/O Pins to ±kv (IEC000) Drop in Replacements for MAXE, MAXE, MAXE, MAXE, MAX4E, MAX4E, SP4E ICLE is a Low Power, Pin Compatible Upgrade for V MAXE ICLE is a Low Power, Pin Compatible Upgrade for V MAX4E, and SPE ICLE is a Low Power Upgrade for HINE, ICL and Pin Compatible Competitor Devices RS- Compatible with =.7V Meets EIA/TIA- and V.8/V.4 Specifications at V Latch-Up Free On-Chip Voltage Converters Require Only Four External 0.µF Capacitors Manual and Automatic Power-Down Features Guaranteed Mouse Driveability (ICL4xE Only) Receiver Hysteresis For Improved Noise Immunity Guaranteed Minimum Data Rate kbps Wide Power Supply Range.... Single V to.v Low Supply Current in Power-Down State..... µa Pb-Free Available (RoHS Compliant) Applications Any System Requiring RS- Communication Ports - Battery Powered, Hand-Held, and Portable Equipment - Laptop Computers, Notebooks, Palmtops - Modems, Printers and other Peripherals - Digital Cameras - Cellular/Mobile Phones Related Literature Technical Brief TB Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs) ICLE, ICLE, ICLE, ICLE, ICL4E, ICL4E FN490. CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures INTERSIL or Copyright Intersil Americas LLC , , 00, 0. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners.

2 TABLE. SUMMARY OF FEATURES PART NUMBER NUMBER OF Tx NUMBER OF Rx NUMBER OF MONITOR RECEIVERS (R OUTB ) DATA RATE (kbps) RECEIVER ENABLE FUNCTION? READY OUTPUT? MANUAL POWER-DOWN? AUTOMATIC POWER- DOWN FUNCTION? ICLE 0 0 Yes No Yes Yes ICLE 0 0 Yes No Yes No ICLE 0 0 Yes No Yes Yes ICLE 0 0 No No No No ICL4E 0 Yes No Yes No ICL4E 0 No No Yes Yes Typical Operating Circuits TTL/CMOS LOGIC LEVELS ICLE C (OPTIONAL CONNECTION, NOTE).V 0.µF C C 0.µF V C 4 0.µF C- C C 0.µF V- 7 C 4 C- 0.µF T TIN T OUT R OUT 9 R kω 8 R IN RS- LEVELS EN FORCEOFF FORCEON INVALID 0 TO POWER CONTROL LOGIC 4 NOTE: THE NEGATIVE TERMINAL OF C CAN BE CONNECTED TO EITHER OR FN490.

3 Typical Operating Circuits (Continued) ICLE.V 0.µF 7 C C 0.µF 4 C- C C 0.µF C- T T IN V V- C (OPTIONAL CONNECTION, NOTE) C 0.µF 7 C 4 0.µF T OUT T IN T 8 T OUT TTL/CMOS LOGIC LEVELS R OUT R kω 4 R IN RS- LEVELS R OUT 0 EN R kω 9 R IN SHDN 8 NOTE: THE NEGATIVE TERMINAL OF C CAN BE CONNECTED TO EITHER OR ICLE.V C 0.µF C 0.µF T IN 0.µF 4 C C- C C- 9 T V V- 7 7 C 0.µF C 4 0.µF T OUT T IN T 8 T OUT TTL/CMOS LOGIC LEVELS R OUT R kω R IN RS- LEVELS R OUT 0 EN 9 R kωω 0 FORCEOFF R IN 4 FORCEON INVALID 8 TO POWER CONTROL LOGIC FN490.

4 Typical Operating Circuits (Continued) ICLE.V 0.µF C (OPTIONAL CONNECTION, NOTE) C 0.µF C 4 0.µF T IN C C- C C- T V V- 4 NOTE: THE NEGATIVE TERMINAL OF C CAN C BE CONNECTED TO EITHER OR 0.µF C 4 0.µF T OUT TTL/CMOS LOGIC LEVELS T IN R OUT 0 T 7 T OUT R IN RS- LEVELS R kω R OUT 9 8 R IN R kω 4 FN490.

5 Typical Operating Circuits (Continued) TTL/CMOS LOGIC LEVELS ICL4E R OUTB R OUT R OUT R OUT R4 OUT R OUT EN SHDN R R R R 4 R kω kω kω kω kω 4 R IN R IN R IN 7 R4 IN 8 R IN RS- LEVELS.V TTL/CMOS LOGIC LEVELS C 0.µF C 0.µF T IN T IN T IN R OUTB R OUT R OUT R OUT R4 OUT R OUT TO POWER CONTROL LOGIC 0.µF ICL4E C.V 0.µF 8 7 C C V C 0.µF 0.µF 4 C- C C V- C 4 0.µF C- 0.µF T 4 9 T IN T OUT T 0 T IN RS- T OUT LEVELS T T IN T OUT R OUTB C- C C- T T V 7 C 0.µF C 4 0.µF T OUT T OUT T R R R R 4 R FORCEON FORCEOFF INVALID V- kω kω kω kω kω T OUT R IN R IN R IN R4 IN R IN RS- LEVELS RS- LEVELS FN490.

6 Pin Configurations ICLE ( LD SSOP, TSSOP) TOP VIEW ICLE (8 LD PDIP, SOIC) TOP VIEW EN FORCEOFF EN 8 SHDN C VCC C 7 VCC V 4 V C- 4 TOUT C- 4 TOUT C FORCEON C 4 RIN C- TIN C- ROUT V- 7 0 INVALID V- 7 TIN RIN 8 9 ROUT TOUT 8 TIN RIN 9 0 ROUT ICLE (0 LD SSOP, TSSOP) TOP VIEW ICLE (0 LD SSOP, TSSOP) TOP VIEW EN 0 SHDN EN 0 FORCEOFF C 9 VCC C 9 VCC V 8 V 8 C- 4 7 TOUT C- 4 7 TOUT C RIN C RIN C- ROUT C- ROUT V- 7 4 NC V- 7 4 FORCEON TOUT 8 TIN TOUT 8 TIN RIN ROUT 9 0 TIN NC RIN ROUT 9 0 TIN INVALID ICLE ( LD SOIC, SSOP, TSSOP-) TOP VIEW ICLE (0 LD TSSOP-0) TOP VIEW C VCC NC 0 NC V C 9 VCC C- 4 TOUT V 8 C 4 RIN C- 4 7 TOUT C- ROUT C RIN V- TIN C- ROUT TOUT 7 0 TIN V- 7 4 TIN RIN 8 9 ROUT TOUT RIN 8 9 TIN ROUT NC 0 NC FN490.

7 Pin Configurations (Continued) ICL4E (8 LD SOIC, SSOP, TSSOP) TOP VIEW ICL4E (8 LD SOIC, SSOP, TSSOP) TOP VIEW C 8 C C 8 C C- 7 V C- 7 V V- VCC V- VCC RIN 4 RIN 4 RIN 4 C- RIN 4 C- RIN EN RIN FORCEON R4IN 7 SHDN R4IN 7 FORCEOFF RIN 8 ROUTB RIN 8 INVALID TOUT 9 0 ROUTB TOUT 9 0 ROUTB TOUT 0 9 ROUT TOUT 0 9 ROUT TOUT 8 ROUT TOUT 8 ROUT TIN 7 ROUT TIN 7 ROUT TIN R4OUT TIN R4OUT TIN 4 ROUT TIN 4 ROUT Pin Descriptions PIN FUNCTION VCC System power supply input (.0V to.v). V Internally generated positive transmitter supply (.V). V- Internally generated negative transmitter supply (-.V). Ground connection. C External capacitor (voltage doubler) is connected to this lead. C- External capacitor (voltage doubler) is connected to this lead. C External capacitor (voltage inverter) is connected to this lead. C- External capacitor (voltage inverter) is connected to this lead. TIN TOUT RIN ROUT ROUTB INVALID EN SHDN FORCEOFF FORCEON TTL/CMOS compatible transmitter Inputs. kv ESD Protected, RS- level (nominally.v) transmitter outputs. kv ESD Protected, RS- compatible receiver inputs. TTL/CMOS level receiver outputs. TTL/CMOS level, noninverting, always enabled receiver outputs. Active low output that indicates if no valid RS- levels are present on any receiver input. Active low receiver enable control; doesn t disable R OUTB outputs. Active low input to shut down transmitters and on-board power supply, to place device in low power mode. Active low to shut down transmitters and on-chip power supply. This overrides any automatic circuitry and FORCEON (see Table ). Active high input to override automatic power-down circuitry thereby keeping transmitters active (FORCEOFF must be high). 7 FN490.

8 Ordering Information PART NUMBER (Note ) PART MARKING TEMP RANGE ( C) PACKAGE PKG. DWG. # ICLECA ICL ECA 0 to 70 Ld SSOP M.09 ICLECA-T (Note ) ICL ECA 0 to 70 Ld SSOP M.09 ICLECAZ (Note ) ICL ECAZ 0 to 70 Ld SSOP (Pb-free) M.09 ICLECAZ-T (Notes, ) ICL ECAZ 0 to 70 Ld SSOP (Pb-free) M.09 ICLECAZA (Note ) ICL ECAZ 0 to 70 Ld SSOP (Pb-free) M.09 ICLECAZA-T (Notes, ) ICL ECAZ 0 to 70 Ld SSOP (Pb-free) M.09 ICLECV ECV 0 to 70 Ld TSSOP M.7 ICLECVZ (Note ) ECVZ 0 to 70 Ld TSSOP (Pb-free) M.7 ICLECVZ-T (Notes, ) ECVZ 0 to 70 Ld TSSOP (Pb-free) M.7 ICLEIA ICL EIA -40 to 8 Ld SSOP M.09 ICLEIA-T (Note ) ICL EIA -40 to 8 Ld SSOP M.09 ICLEIAZ (Note ) ICL EIAZ -40 to 8 Ld SSOP (Pb-free) M.09 ICLEIAZ-T (Notes, ) ICL EIAZ -40 to 8 Ld SSOP (Pb-free) M.09 ICLEIVZ (Note ) EIVZ -40 to 8 Ld TSSOP (Pb-free) M.7 ICLEIVZ-T (Notes, ) EIVZ -40 to 8 Ld TSSOP (Pb-free) M.7 ICLECA-T (Note ) ICL ECA 0 to 70 0 Ld SSOP M0.09 ICLECAZ (Note ) ICL ECAZ 0 to 70 0 Ld SSOP (Pb-free) M0.09 ICLECAZ-T (Notes, ) ICL ECAZ 0 to 70 0 Ld SSOP (Pb-free) M0.09 ICLECP ICLECP 0 to 70 8 Ld PDIP E8. ICLECV-T (Note ) ICL ECV 0 to 70 0 Ld TSSOP M0.7 ICLECVZ (Note ) ICL ECVZ 0 to 70 0 Ld TSSOP (Pb-free) M0.7 ICLECVZ-T (Notes, ) ICL ECVZ 0 to 70 0 Ld TSSOP (Pb-free) M0.7 ICLEIAZ (Note ) ICL EIAZ -40 to 8 0 Ld SSOP (Pb-free) M0.09 ICLEIAZ-T (Notes, ) ICL EIAZ -40 to 8 0 Ld SSOP (Pb-free) M0.09 ICLEIB ICLEIB -40 to 8 8 Ld SOIC M8. ICLEIB-T (Note ) ICLEIB -40 to 8 8 Ld SOIC M8. ICLEIBZ (Note ) EIBZ -40 to 8 8 Ld SOIC (Pb-free) M8. ICLEIBZ-T (Notes, ) EIBZ -40 to 8 8 Ld SOIC (Pb-free) M8. ICLEIV ICL EIV -40 to 8 0 Ld TSSOP M0.7 ICLEIV-T (Note ) ICL EIV -40 to 8 0 Ld TSSOP M0.7 ICLEIVZ (Note ) ICL EIVZ -40 to 8 0 Ld TSSOP (Pb-free) M0.7 ICLEIVZ-T (Notes, ) ICL EIVZ -40 to 8 0 Ld TSSOP (Pb-free) M0.7 ICLECA ICL ECA 0 to 70 0 Ld SSOP M0.09 ICLECA-T (Note ) ICL ECA 0 to 70 0 Ld SSOP M0.09 ICLECAZ (Note ) ICL ECAZ 0 to 70 0 Ld SSOP (Pb-free) M0.09 ICLECAZ-T (Notes, ) ICL ECAZ 0 to 70 0 Ld SSOP (Pb-free) M0.09 ICLECV ICL ECV 0 to 70 0 Ld TSSOP M0.7 ICLECVZ (Note ) ICL ECVZ 0 to 70 0 Ld TSSOP (Pb-free) M0.7 ICLECVZ-T (Notes, ) ICL ECVZ 0 to 70 0 Ld TSSOP (Pb-free) M0.7 8 FN490.

9 Ordering Information (Continued) PART NUMBER (Note ) ICLEIAZ (Note ) ICL EIAZ -40 to 8 0 Ld SSOP (Pb-free) M0.09 ICLEIAZ-T (Notes, ) ICL EIAZ -40 to 8 0 Ld SSOP (Pb-free) M0.09 ICLEIV ICL EIV -40 to 8 0 Ld TSSOP M0.7 ICLEIVZ (Note ) ICL EIVZ -40 to 8 0 Ld TSSOP (Pb-free) M0.7 ICLEIVZ-T (Notes, ) ICL EIVZ -40 to 8 0 Ld TSSOP (Pb-free) M0.7 ICLECAZ (Note ) ECAZ 0 to 70 Ld SSOP (Pb-free) M.09 ICLECAZ-T (Notes, ) ECAZ 0 to 70 Ld SSOP (Pb-free) M.09 ICLECBZ (Note ) ECBZ 0 to 70 Ld SOIC (Pb-free) M. ICLECBZ-T (Notes, ) ECBZ 0 to 70 Ld SOIC (Pb-free) M. ICLECBNZ (Note ) ECBNZ 0 to 70 Ld SOIC (Pb-free) M. ICLECBNZ-T (Notes, ) ECBNZ 0 to 70 Ld SOIC (Pb-free) M. ICLECV-Z (Note ) E CV-Z 0 to 70 Ld TSSOP (Pb-free) M.7 ICLECV-Z-T (Notes, ) E CV-Z 0 to 70 Ld TSSOP (Pb-free) M.7 ICLECV-0Z (Note ) ICL ECV-0Z 0 to 70 0 Ld TSSOP (Pb-free) M0.7 ICLECV-0Z-T (Notes, ) ICL ECV-0Z 0 to 70 0 Ld TSSOP (Pb-free) M0.7 ICLEFV-Z (Note ) E FV-Z -40 to Ld TSSOP (Pb-free) M.7 ICLEFV-Z-T (Notes, ) E FV-Z -40 to Ld TSSOP (Pb-free) M.7 ICLEIAZ (Note ) EIAZ -40 to 8 Ld SSOP (Pb-free) M.09 ICLEIAZ-T (Notes, ) EIAZ -40 to 8 Ld SSOP (Pb-free) M.09 ICLEIBZ (Note ) EIBZ -40 to 8 Ld SOIC (Pb-free) M. ICLEIBZ-T (Notes, ) EIBZ -40 to 8 Ld SOIC (Pb-free) M. ICLEIBNZ (Note ) EIBNZ -40 to 8 Ld SOIC (Pb-free) M. ICLEIBNZ-T (Notes, ) EIBNZ -40 to 8 Ld SOIC (Pb-free) M. ICLEIV-Z (Note ) E IV-Z -40 to 8 Ld TSSOP (Pb-free) M.7 ICLEIV-Z-T (Notes, ) E IV-Z -40 to 8 Ld TSSOP (Pb-free) M.7 ICLEIV-0Z (Note ) ICL EIV-0Z -40 to 8 0 Ld TSSOP (Pb-free) M0.7 ICLEIV-0Z-T (Notes, ) ICL EIV-0Z -40 to 8 0 Ld TSSOP (Pb-free) M0.7 ICL4ECAZ (Note ) ICL4 ECAZ 0 to 70 8 Ld SSOP (Pb-free) M8.09 ICL4ECAZ-T (Notes, ) ICL4 ECAZ 0 to 70 8 Ld SSOP (Pb-free) M8.09 ICL4ECBZ (Note ) (No longer available, recommended replacement: ICL4EIVZ) ICL4ECBZ-T (Notes, ) (No longer available, recommended replacement: ICL4EIVZ) ICL4ECBZ 0 to 70 8 Ld SOIC (Pb-free) M8. ICL4ECBZ 0 to 70 8 Ld SOIC (Pb-free) M8. ICL4ECVZ (Note ) ICL4 ECVZ 0 to 70 8 Ld TSSOP (Pb-free) M8.7 ICL4EIAZ (Note ) ICL4 EIAZ -40 to 8 8 Ld SSOP (Pb-free) M8.09 ICL4EIAZ-T (Notes, ) ICL4 EIAZ -40 to 8 8 Ld SSOP (Pb-free) M8.09 ICL4EIBZ (Note ) (No longer available, recommended replacement: ICL4EIVZ) ICL4EIBZ-T (Notes, ) (No longer available, recommended replacement: ICL4EIVZ) PART MARKING TEMP RANGE ( C) PACKAGE PKG. DWG. # ICL4EIBZ -40 to 8 8 Ld SOIC (Pb-free) M8. ICL4EIBZ -40 to 8 8 Ld SOIC (Pb-free) M8. 9 FN490.

10 Ordering Information (Continued) PART NUMBER (Note ) PART MARKING TEMP RANGE ( C) PACKAGE ICL4EIVZ (Note ) ICL4 EIVZ -40 to 8 8 Ld TSSOP (Pb-free) M8.7 ICL4EIVZ-T (Notes, ) ICL4 EIVZ -40 to 8 8 Ld TSSOP (Pb-free) M8.7 ICL4ECAZ (Note ) ICL 4ECAZ 0 to 70 8 Ld SSOP (Pb-free) M8.09 ICL4ECAZ-T (Notes, ) ICL 4ECAZ 0 to 70 8 Ld SSOP (Pb-free) M8.09 ICL4ECBZ (Note ) ICL4ECBZ 0 to 70 8 Ld SOIC (Pb-free) M8. ICL4ECBZ-T (Notes, ) ICL4ECBZ 0 to 70 8 Ld SOIC (Pb-free) M8. PKG. DWG. # ICL4ECVZ (Note ) ICL4 ECVZ 0 to 70 8 Ld TSSOP (Pb-free) M8.7 ICL4ECVZ-T (Notes, ) ICL4 ECVZ 0 to 70 8 Ld TSSOP (Pb-free) M8.7 ICL4EIAZ (Note ) ICL 4EIAZ -40 to 8 8 Ld SSOP (Pb-free) M8.09 ICL4EIAZ-T (Notes, ) ICL 4EIAZ -40 to 8 8 Ld SSOP (Pb-free) M8.09 ICL4EIVZ (Note ) ICL4 EIVZ -40 to 8 8 Ld TSSOP (Pb-free) M8.7 ICL4EIVZ-T (Notes, ) ICL4 EIVZ -40 to 8 8 Ld TSSOP (Pb-free) M8.7 NOTES:. Please refer to TB47 for details on reel specifications.. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 00% matte tin plate plus anneal (e termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-00.. For Moisture Sensitivity Level (MSL), please see device information page for ICLE, ICLE, ICLE, ICLE, ICL4E, ICL4E. For more information on MSL please see techbrief TB. 0 FN490.

11 Table of Contents Typical Operating Circuits Pin Configurations Pin Descriptions Ordering Information Absolute Maximum Ratings Thermal Information Recommended Operating Conditions Electrical Specifications Detailed Description Charge-Pump Transmitters Receivers Low Power Operation Pin Compatible Replacements for V Devices Power-Down Functionality (Except ICLE) Software Controlled (Manual) Power-Down Automatic Power-Down (ICLE, ICLE, ICL4E Only) Receiver ENABLE Control (ICLE, ICLE, ICLE, ICL4E Only) Capacitor Selection Power Supply Decoupling Operation Down to.7v Transmitter Outputs when Exiting Power-Down Mouse Driveability High Data Rates Interconnection with V and V Logic ±kv ESD Protection Human Body Model (HBM) Testing IEC Testing Typical Performance Curves VCC =.V, TA = C Die Characteristics Revision History About Intersil Package Outline Drawing FN490.

12 Absolute Maximum Ratings to V to V V to V to 7V V- to V to -7V V to V V Input Voltages T IN, FORCEOFF, FORCEON, EN, SHDN V to V R IN ±V Output Voltages T OUT ±.V R OUT, INVALID V to 0.V Short Circuit Duration T OUT Continuous ESD Rating See Specification Table Recommended Operating Conditions Temperature Range ICLxxECX C to 70 C ICLxxEFX C to C ICLxxEIX C to 8 C Supply Voltage ( ) V or V Rx Input Voltage V to V Thermal Information Thermal Resistance (Typical, Note 4) Θ JA ( C/W) 8 Ld PDIP Package* Ld Wide SOIC Package Ld Narrow SOIC Package Ld SOIC Package Ld SOIC Package Ld SSOP Package Ld SSOP Package Ld TSSOP Package Ld TSSOP Package Ld SSOP and TSSOP Packages Maximum Junction Temperature (Plastic Package). 0 C Maximum Storage Temperature Range... - C to 0 C Pb-Free Reflow Profile see link below CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTE: 4. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB79 for details. Electrical Specifications Test Conditions: = V to.v, C - C 4 = 0.µF; Unless Otherwise Specified. Typicals are at T A = C. Boldface limits apply over the operating temperature range. PARAMETER DC CHARACTERISTICS TEST CONDITIONS TEMP ( C) MIN (Note ) TYP MAX (Note ) UNITS Supply Current, Automatic Power-Down All R IN Open, FORCEON =, FORCEOFF = (ICLE, ICLE, ICL4E Only) µa Supply Current, Power-Down Supply Current, Automatic Power-Down Disabled FORCEOFF = SHDN = (Except ICLE) µa All Outputs Unloaded, FORCEON = FORCEOFF = SHDN = =.0V, ICL4, ICL ma =.0V, ICL ma =.V, ICL, ICL, ICL, ICL ma LOGIC AND TRANSMITTER INPUTS AND RECEIVER OUTPUTS Input Logic Threshold Low T IN, FORCEON, FORCEOFF, EN, SHDN Full V Input Logic Threshold High Input Leakage Current T IN, FORCEON, FORCEOFF, EN, SHDN T IN, FORCEON, FORCEOFF, EN, SHDN =.V Full V =.0V Full V All but ICLEF Full µa ICLEF Full µa Output Leakage Current (Except ICLE) FORCEOFF = or EN = Full µa Output Voltage Low I OUT =.ma Full V Output Voltage High I OUT = -.0mA All but ICLEF Full V ICLEF Full V FN490.

13 Electrical Specifications Test Conditions: = V to.v, C - C 4 = 0.µF; Unless Otherwise Specified. Typicals are at T A = C. Boldface limits apply over the operating temperature range. (Continued) PARAMETER AUTOMATIC POWER-DOWN (ICLE, ICLE, ICL4E Only, FORCEON =, FORCEOFF = ) Receiver Input Thresholds to Enable Transmitters ICLxxE Powers Up (see Figure ) Full V Receiver Input Thresholds to Disable Transmitters INVALID Output Voltage Low INVALID Output Voltage High Receiver Threshold to Transmitters Enabled Delay (t WU ) Receiver Positive or Negative Threshold to INVALID High Delay (t INVH ) Receiver Positive or Negative Threshold to INVALID Low Delay (t INVL ) ICLxxE Powers Down (see Figure ) Full V I OUT =.ma Full V I OUT = -.0mA Full V µs - - µs µs RECEIVER INPUTS Input Voltage Range - - V Input Threshold Low =.V V =.0V V Input Threshold High =.V -..4 V =.0V V Input Hysteresis V Input Resistance 7 kω TRANSMITTER OUTPUTS Output Voltage Swing All Transmitter Outputs Loaded with kω to Ground Full V Output Resistance = V = V- = 0V, Transmitter Output = V Full 00 0M - Ω Output Short-Circuit Current Full - 0 ma Output Leakage Current MOUSE DRIVEABILITY (ICL4XE Only) Transmitter Output Voltage (see Figure 9) V OUT = V, = 0V or V to.v, Automatic Power-Down or FORCEOFF = SHDN = T IN = T IN =, T IN =, T OUT Loaded with kω to, T OUT and T OUT Loaded with.ma Each TIMING CHARACTERISTICS Maximum Data Rate R L = kω, C L = 000pF, One Transmitter Switching Receiver Propagation Delay Receiver Output Enable Time Receiver Input to Receiver Output, C L = 0pF TEST CONDITIONS TEMP ( C) MIN (Note ) Full - - µa Full - - V Full kbps t PHL µs t PLH µs Normal Operation (Except ICLE) ns TYP MAX (Note ) UNITS FN490.

14 Electrical Specifications Test Conditions: = V to.v, C - C 4 = 0.µF; Unless Otherwise Specified. Typicals are at T A = C. Boldface limits apply over the operating temperature range. (Continued) PARAMETER Receiver Output Disable Time TEST CONDITIONS Normal Operation (Except ICLE) ns Transmitter Skew t PHL to t PLH (Note ) ns Receiver Skew t PHL to t PLH ns Transition Region Slew Rate =.V, C L = 0pF to 00pF 4-0 V/µs R L = kω to 7kΩ Measured from V to -V or -V to V C L = 0pF to 000pF - 0 V/µs ESD PERFORMANCE RS- Pins (TOUT, RIN) Human Body Model - - kv IEC Contact Discharge kv IEC Air Gap Discharge - - kv All Other Pins Human Body Model - - kv NOTES:. Transmitter skew is measured at the transmitter zero crossing points.. Parameters with MIN and/or MAX limits are 00% tested at C, unless otherwise specified. Temperature limits established by characterization and are not production tested. TEMP ( C) MIN (Note ) TYP MAX (Note ) UNITS Detailed Description ICLxxE interface ICs operate from a single V to.v supply, guarantee a 0kbps minimum data rate, require only four small external 0.µF capacitors, feature low power consumption, and meet all ElA RS-C and V.8 specifications. The circuit is divided into three sections: charge pump, transmitters and receivers. Charge-Pump Intersil s new ICLxxE family utilizes regulated onchip dual charge pumps as voltage doublers, and voltage inverters to generate ±.V transmitter supplies from a supply as low as.0v. This allows these devices to maintain RS- compliant output levels over the ±0% tolerance range of.v powered systems. The efficient on-chip power supplies require only four small, external 0.µF capacitors for the voltage doubler and inverter functions at =.V. See Capacitor Selection on page 8 and Table on page 8 for capacitor recommendations for other operating conditions. The charge pumps operate discontinuously (i.e., they turn off as soon as the V and V- supplies are pumped up to the nominal values), resulting in significant power savings. Transmitters The transmitters are proprietary, low dropout, inverting drivers that translate TTL/CMOS inputs to EIA/TIA- output levels. Coupled with the on-chip ±.V supplies, these transmitters deliver true RS- levels over a wide range of single supply system voltages. Except for the ICLE, all transmitter outputs disable and assume a high impedance state when the device enters the power-down mode (see Table ). These outputs may be driven to ±V when disabled. All devices guarantee a 0kbps data rate for full load conditions (kω and 000pF),.0V, with one transmitter operating at full speed. Under more typical conditions of.v, R L = kω, and C L = 0pF, one transmitter easily operates at 900kbps. Transmitter inputs float if left unconnected, and may cause I CC increases. Connect unused inputs to for the best performance. Receivers All the ICLxxE devices contain standard inverting receivers that three-state (except for the ICLE) via the EN or FORCEOFF control lines. Additionally, the two ICL4XE products include noninverting (monitor) receivers (denoted by the ROUTB label) that are always active, regardless of the state of any control lines. All the receivers convert RS- signals to CMOS output levels and accept inputs up to ±V while presenting the required kω to 7kΩ input impedance (see Figure ) even if the power is off (VCC = 0V). The receivers Schmitt trigger input stage uses hysteresis to increase noise immunity and decrease errors due to slow input signal transitions. The ICLE, ICLE, ICLE, ICL4E inverting receivers disable only when EN is driven high. ICL4E receivers disable during forced (manual) power-down, but not during automatic power-down (see Table ). 4 FN490.

15 ICL4E and ICL4E monitor receivers remain active even during manual power-down and forced receiver disable, making them extremely useful for Ring Indicator monitoring. Standard receivers driving powered down peripherals must be disabled to prevent current flow through the peripheral s protection diodes (see Figures and ). This renders them useless for wake up functions, but the corresponding monitor receiver can be dedicated to this task as shown in Figure. R XIN -V V RIN V k R XOUT V ROUT FIGURE. INVERTING RECEIVER CONNECTIONS Low Power Operation These V devices require a nominal supply current of 0.mA, even at =.V, during normal operation (not in power-down mode). This is considerably less than the ma to ma current required by comparable V RS- devices, allowing users to reduce system power simply by switching to this new family. Pin Compatible Replacements for V Devices The ICLE, ICLE, ICLE are pin compatible with existing V RS- transceivers - See the Features section on page for details. This pin compatibility coupled with the low I CC and wide operating supply range, make the ICLxxE potential lower power, higher performance drop-in replacements for existing V applications. As long as the V RS- output swings are acceptable, and transmitter input pull-up resistors aren t required, the IICLxxE should work in most V applications. When replacing a device in an existing V application, it is acceptable to terminate C to as shown on the Typical Operating Circuits on page. Nevertheless, terminate C to if possible, as slightly better performance results from this configuration. RS- SIGNAL PRESENT AT RECEIVER INPUT? ICLE, ICLE, ICLE, ICLE, ICL4E, ICL4E FORCEOFF OR SHDN INPUT FORCEON INPUT TABLE. POWER-DOWN AND ENABLE LOGIC TRUTH TABLE EN INPUT TRANSMITTER OUTPUTS Power-Down Functionality (Except ICLE) The already low current requirement drops significantly when the device enters power-down mode. In power-down, supply current drops to µa, because the on-chip charge pump turns off (V collapses to, V- collapses to ), and the transmitter outputs three-state. Inverting receiver outputs may or may not disable in power-down; refer to Table for details. This micro-power mode makes these devices ideal for battery powered and portable applications. Software Controlled (Manual) Power-Down Most devices in the ICLxxE family provide pins that allow the user to force the IC into the low power, standby state. On the ICLE and ICL4E, the power-down control is via a simple shutdown (SHDN) pin. Driving this pin high enables normal operation, while driving it low forces the IC into its power-down state. Connect SHDN to if the power-down function isn t needed. Note that all the receiver outputs remain enabled during shutdown (see Table ). For the lowest power consumption during power-down, the receivers should also be disabled by driving the EN input high (see next section, and Figures and ). The ICLE, ICLE, and ICL4E utilize a two pin approach where the FORCEON and FORCEOFF inputs determine the IC s mode. For always enabled operation, FORCEON and FORCEOFF are both strapped high. To switch between active and power-down modes, under logic or software control, only the FORCEOFF input need be driven. The FORCEON state isn t critical, as FORCEOFF dominates over FORCEON. Nevertheless, if strictly manual control over powerdown is desired, the user must strap FORCEON high to disable the automatic power-down circuitry. ICL4E inverting (standard) receiver outputs also disable when the device is in manual power-down, thereby eliminating the possible current path through a shutdown peripheral s input protection diode (see Figures and ). RECEIVER OUTPUTS R OUTB OUTPUTS (NOTE 7) INVALID OUTPUT MODE OF OPERATION ICLE, ICL4E N/A L N/A L High-Z Active Active N/A Manual Power-Down N/A L N/A H High-Z High-Z Active N/A Manual Power-Down with Receiver Disabled N/A H N/A L Active Active Active N/A Normal Operation N/A H N/A H Active High-Z Active N/A Normal Operation with Receiver Disabled FN490.

16 RS- SIGNAL PRESENT AT RECEIVER INPUT? FORCEOFF OR SHDN INPUT TABLE. POWER-DOWN AND ENABLE LOGIC TRUTH TABLE (Continued) FORCEON INPUT EN INPUT TRANSMITTER OUTPUTS RECEIVER OUTPUTS R OUTB OUTPUTS (NOTE 7) INVALID OUTPUT MODE OF OPERATION ICLE, ICLE No H H L Active Active N/A L Normal Operation No H H H Active High-Z N/A L (Auto Power-Down Disabled) Yes H L L Active Active N/A H Normal Operation Yes H L H Active High-Z N/A H (Auto Power-Down Enabled) No H L L High-Z Active N/A L Power-Down Due to Auto No H L H High-Z High-Z N/A L Power-Down Logic Yes L X L High-Z Active N/A H Manual Power-Down Yes L X H High-Z High-Z N/A H Manual Power-Down with Receiver Disabled No L X L High-Z Active N/A L Manual Power-Down No L X H High-Z High-Z N/A L Manual Power-Down with Receiver Disabled ICL4E No H H N/A Active Active Active L Normal Operation (Auto Power-Down Disabled) Yes H L N/A Active Active Active H Normal Operation (Auto Power-Down Enabled) No H L N/A High-Z Active Active L Power-Down Due to Auto Power-Down Logic Yes L X N/A High-Z High-Z Active H Manual Power-Down No L X N/A High-Z High-Z Active L Manual Power-Down NOTE: 7. Applies only to the ICL4E and ICL4E. The INVALID output always indicates whether or not a valid RS- signal is present at any of the receiver inputs (see Table ), giving the user an easy way to determine when the interface block should power down. In the case of a disconnected interface cable where all the receiver inputs are floating (but pulled to by the internal receiver pull down resistors), the INVALID logic detects the invalid levels and drives the output low. The power management logic then uses this indicator to power down the interface block. Reconnecting the cable restores valid levels at the receiver inputs, INVALID switches high, and the power management logic wakes up the interface block. INVALID can also be used to indicate the DTR or RING INDICATOR signal, as long as the other receiver inputs are floating, or driven to (as in the case of a powered down driver). Connecting FORCEOFF and FORCEON together disables the automatic power-down feature, enabling them to function as a manual SHUTDOWN input (see Figure 4). POWERED DOWN UART Rx Tx V OUT = SHDN = CURRENT FLOW OLD RS- CHIP FIGURE. POWER DRAIN THROUGH POWERED DOWN PERIPHERAL FN490.

17 TRANSITION DETECTOR POWER MANAGEMENT UNIT MASTER POWER-DOWN LINE 0.µF MΩ TO WAKE-UP LOGIC ICL4XE FORCEOFF FORCEON R OUTB ICLE, ICLE, ICL4E POWERED DOWN UART R X T X V OUT = HI-Z R OUT T IN FORCEOFF = OR SHDN =, EN = R IN T OUT FIGURE. DISABLED RECEIVERS PREVENT POWER DRAIN PWR MGT LOGIC FORCEOFF FORCEON INVALID ICLE, ICLE, ICL4E FIGURE. CIRCUIT TO PREVENT AUTO POWER-DOWN FOR 00ms AFTER FORCED POWER-UP Automatic Power-Down (ICLE, ICLE, ICL4E Only) Even greater power savings is available by using the devices which feature an automatic power-down function. When no valid RS- voltages (see Figure ) are sensed on any receiver input for 0µs, the charge pump and transmitters power-down, thereby reducing supply current to µa. Invalid receiver levels occur whenever the driving peripheral s outputs are shut off (powered down) or when the RS- interface cable is disconnected. The ICLxxE powers back up whenever it detects a valid RS- voltage level on any receiver input. This automatic power-down feature provides additional system power savings without changes to the existing operating system..7v VALID RS- LEVEL - ICLxxE IS ACTIVE CPU I/O UART 0.V INDETERMINATE - POWER-DOWN MAY OR MAY NOT OCCUR INVALID LEVEL - POWER-DOWN OCCURS AFTER 0µs -0.V FIGURE 4. CONNECTIONS FOR MANUAL POWER-DOWN WHEN NO VALID RECEIVER SIGNALS ARE PRESENT With any of the control schemes, the time required to exit power-down, and resume transmission is only 00µs. A mouse, or other application, may need more time to wake up from shutdown. If automatic power-down is being utilized, the RS- device will reenter power-down if valid receiver levels aren t reestablished within 0µs of the ICLxxE powering up. Figure illustrates a circuit that keeps the ICLxxE from initiating automatic power-down for 00ms after powering up. This gives the slow-to-wake peripheral circuit time to reestablish valid RS- output levels. -.7V INDETERMINATE - POWER-DOWN MAY OR MAY NOT OCCUR VALID RS- LEVEL - ICLxxE IS ACTIVE FIGURE. DEFINITION OF VALID RS- RECEIVER LEVELS Automatic power-down operates when the FORCEON input is low, and the FORCEOFF input is high. Tying FORCEON high disables automatic power-down, but manual power-down is always available via the overriding FORCEOFF input. Table summarizes the automatic power-down functionality. 7 FN490.

18 Devices with the automatic power-down feature include an INVALID output signal, which switches low to indicate that invalid levels have persisted on all of the receiver inputs for more than 0µs (see Figure 7). INVALID switches high µs after detecting a valid RS- level on a receiver input. INVALID operates in all modes (forced or automatic power-down, or forced on), so it is also useful for systems employing manual power-down circuitry. When automatic power-down is utilized, INVALID = 0 indicates that the ICLxxE is in power-down mode. The time to recover from automatic power-down mode is typically 00µs. RECEIVER INPUTS TRANSMITTER OUTPUTS INVALID OUTPUT 0 V 0 V- t INVL AUTOPWDN t INVH FIGURE 7. AUTOMATIC POWER-DOWN AND INVALID TIMING DIAGRAMS INVALID } REGION PWR UP Receiver ENABLE Control (ICLE, ICLE, ICLE, ICL4E Only) Several devices also feature an EN input to control the receiver outputs. Driving EN high disables all the inverting (standard) receiver outputs placing them in a high impedance state. This is useful to eliminate supply current, due to a receiver output forward biasing the protection diode, when driving the input of a powered down ( = ) peripheral (see Figure ). The enable input has no effect on transmitter nor monitor (R OUTB ) outputs. Capacitor Selection The charge pumps require 0.µF capacitors for.v operation. For other supply voltages refer to Table for capacitor values. Do not use values smaller than those listed in Table. Increasing the capacitor values (by a factor of ) reduces ripple on the transmitter outputs and slightly reduces power consumption. C, C, and C 4 can be increased without increasing C s value, however, do not increase C without also increasing C, C, and C 4 to maintain the proper ratios (C to the other capacitors). When using minimum required capacitor values, make sure that capacitor values do not degrade excessively with temperature. If in doubt, use capacitors with a larger nominal value. The capacitor s equivalent series resistance (ESR) usually rises at low temperatures and it influences the amount of ripple on V and V-. TABLE. REQUIRED CAPACITOR VALUES (V) C (µf) C, C, C 4 (µf).0 to to to Power Supply Decoupling In most circumstances a 0.µF bypass capacitor is adequate. In applications that are particularly sensitive to power supply noise, decouple to ground with a capacitor of the same value as the charge-pump capacitor C. Connect the bypass capacitor as close as possible to the IC. Operation Down to.7v ICLxxE transmitter outputs meet RS- levels (±.7V), at full data rate, with as low as.7v. RS- levels typically ensure interoperability with RS- devices. Transmitter Outputs when Exiting Power-Down Figure 8 shows the response of two transmitter outputs when exiting power-down mode. As they activate, the two transmitter outputs properly go to opposite RS- levels, with no glitching, ringing, nor undesirable transients. Each transmitter is loaded with kω in parallel with 00pF. Note that the transmitters enable only when the magnitude of the supplies exceed approximately V.. V/DIV V/DIV FORCEOFF =.V C - C4 = 0.µF TIME (0µs/DIV) FIGURE 8. TRANSMITTER OUTPUTS WHEN EXITING POWER-DOWN Mouse Driveability The ICL4E and ICL4E have been specifically designed to power a serial mouse while operating from low voltage supplies. Figure 9 shows the transmitter T T 8 FN490.

19 output voltages under increasing load current. The on-chip switching regulator ensures the transmitters will supply at least V during worst case conditions (ma for paralleled V transmitters, 7.mA for single V- transmitter). The Automatic Power-Down feature does not work with a mouse, so FORCEOFF and FORCEON should be connected to. 4 V OUT =.0V T 0 V OUT - T - ICL4E, ICL4E - -4 T V OUT - V OUT LOAD CURRENT PER TRANSMITTER (ma) FIGURE 9. TRANSMITTER OUTPUT VOLTAGE vs LOAD CURRENT (PER TRANSMITTER, i.e., DOUBLE CURRENT AXIS FOR TOTAL V OUT CURRENT) TRANSMITTER OUTPUT VOLTAGE (V) High Data Rates The ICLxxE maintain the RS- V minimum transmitter output voltages even at high data rates. Figure 0 details a transmitter loopback test circuit, and Figure illustrates the loopback test result at 0kbps. For this test, all transmitters were simultaneously driving RS- loads in parallel with 000pF, at 0kbps. Figure shows the loopback results for a single transmitter driving 000pF and an RS- load at 0kbps. The static transmitters were also loaded with an RS- receiver. C 0.µF C SHDN OR FORCEOFF ICLxxE C C- C V- C C 4 C- T IN R OUT EN T OUT V R IN K 000pF V/DIV T IN T OUT R OUT V/DIV T IN T OUT R OUT =.V C - C4 = 0.µF µs/div FIGURE. LOOPBACK TEST AT 0kbps =.V C - C4 = 0.µF FIGURE. LOOPBACK TEST AT 0kbps Interconnection with V and V Logic The ICLXX directly interface with V CMOS and TTL logic families. Nevertheless, with the ICLXX at.v, and the logic supply at V, AC, HC, and CD4000 outputs can drive ICLXX inputs, but ICLXX outputs do not reach the minimum V IH for these logic families. See Table 4 for more information. TABLE 4. LOGIC FAMILY COMPATIBILITY WITH VARIOUS SUPPLY VOLTAGES SYSTEM POWER-SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) µs/div COMPATIBILITY.. Compatible with all CMOS families. Compatible with all TTL and CMOS logic families. FIGURE 0. TRANSMITTER LOOPBACK TEST CIRCUIT 9 FN490.

20 TABLE 4. LOGIC FAMILY COMPATIBILITY WITH VARIOUS SUPPLY VOLTAGES (Continued) SYSTEM POWER-SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) COMPATIBILITY. Compatible with ACT and HCT CMOS, and with TTL. ICLXX outputs are incompatible with AC, HC, and CD4000 CMOS inputs. ±kv ESD Protection All pins on ICLXX devices include ESD protection structures, but the ICLxxE family incorporates advanced structures which allow the RS- pins (transmitter outputs and receiver inputs) to survive ESD events up to ±kv. The RS- pins are particularly vulnerable to ESD damage because they typically connect to an exposed port on the exterior of the finished product. Simply touching the port pins, or connecting a cable, can cause an ESD event that might destroy unprotected ICs. These new ESD structures protect the device whether or not it is powered up, protect without allowing any latch-up mechanism to activate, and don t interfere with RS- signals as large as ±V. Human Body Model (HBM) Testing As the name implies, this test method emulates the ESD event delivered to an IC during human handling. The tester delivers the charge through a.kω current limiting resistor, making the test less severe than the IEC000 test which utilizes a 0Ω limiting resistor. The HBM method determines an IC s ability to withstand the ESD transients typically present during handling and manufacturing. Due to the random nature of these events, each pin is tested with respect to all other pins. The RS- pins on E family devices can withstand HBM ESD events to ±kv. IEC Testing The IEC000 test method applies to finished equipment, rather than to an individual IC. Therefore, the pins most likely to suffer an ESD event are those that are exposed to the outside world (the RS- pins in this case), and the IC is tested in its typical application configuration (power applied) rather than testing each pin-to-pin combination. The lower current limiting resistor coupled with the larger charge storage capacitor yields a test that is much more severe than the HBM test. The extra ESD protection built into this device s RS- pins allows the design of equipment meeting level 4 criteria without the need for additional board level protection on the RS- port. AIR-GAP DISCHARGE TEST METHOD For this test method, a charged probe tip moves toward the IC pin until the voltage arcs to it. The current waveform delivered to the IC pin depends on approach speed, humidity, temperature, etc., so it is difficult to obtain repeatable results. The E device RS- pins withstand ±kv air-gap discharges. CONTACT DISCHARGE TEST METHOD During the contact discharge test, the probe contacts the tested pin before the probe tip is energized, thereby eliminating the variables associated with the air-gap discharge. The result is a more repeatable and predictable test, but equipment limits prevent testing devices at voltages higher than ±8kV. All E family devices survive ±8kV contact discharges on the RS- pins. Typical Performance Curves =.V, T A = C. TRANSMITTER OUTPUT VOLTAGE (V) TRANSMITTER AT 0kbps OR TRANSMITTERS AT 0kbps V OUT V OUT LOAD CAPACITANCE (pf) SLEW RATE (V/µs) 0 0 SLEW -SLEW LOAD CAPACITANCE (pf) FIGURE. TRANSMITTER OUTPUT VOLTAGE vs LOAD CAPACITANCE FIGURE 4. SLEW RATE vs LOAD CAPACITANCE 0 FN490.

21 Typical Performance Curves =.V, T A = C. (Continued) SUPPLY CURRENT (ma) ICLE 0kbps 0kbps 0kbps SUPPLY CURRENT (ma) ICLE, ICLE, ICLE 0kbps 0kbps 0kbps LOAD CAPACITANCE (pf) FIGURE. SUPPLY CURRENT vs LOAD CAPACITANCE WHEN TRANSMITTING DATA LOAD CAPACITANCE (pf) FIGURE. SUPPLY CURRENT vs LOAD CAPACITANCE WHEN TRANSMITTING DATA SUPPLY CURRENT (ma) ICL4XE 0kbps 0kbps 0kbps SUPPLY CURRENT (ma) ICL4XE NO LOAD ALL OUTPUTS STATIC ICLE, ICLE, ICLE, ICLE ICL4XE LOAD CAPACITANCE (pf) SUPPLY VOLTAGE (V) FIGURE 7. SUPPLY CURRENT vs LOAD CAPACITANCE WHEN TRANSMITTING DATA FIGURE 8. SUPPLY CURRENT vs SUPPLY VOLTAGE Die Characteristics SUBSTRATE POTENTIAL (POWERED UP): TRANSISTOR COUNT: ICLE: 8 ICLE: 8 ICLE: 7 ICLE: 9 ICL4XE: 44 PROCESS: Si Gate CMOS FN490.

22 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. DATE REVISION CHANGE /9/ FN490. Updated Ordering Information table starting on page 8 Updated Products section to About Intersil POD E8. updated from rev to rev. Changes since rev : ) Removed the dimension chart and replaced with new standard format values for each dimension letter. ) Updated D dimension (in side view; length of package) from 0.84(min) : 0.880(max) to 0.880(.7)(min) : 0.90(4.)(max) ) Change JEDEC reference from MS-00-BC issue D to MS-00-AC issue D POD M.7 updated from rev to rev. Changes since rev : Converted to new POD format by moving dimensions from table onto drawing and adding land pattern. No dimension changes. POD M0.7 updated from rev to rev. Changes since rev : Converted to new POD format by moving dimensions from table onto drawing and adding land pattern. No dimension changes. POD M8.7 udpated from rev 0 to rev. Changes since rev : Converted to new POD format by moving dimensions from table onto drawing and adding land pattern. No dimension changes. POD M8. updated from rev 0 to rev. Changes since rev : Added land pattern //0 FN490. Revision history begins with this revision. Converted to new Intersil template. Added new temp grade (F = extended industrial) to ICL. Updated ordering info table, Operating Conditions, and added C specs for input lkg currents, and rcvr output high voltage. Pages 8-0: Removed all withdrawn devices from Ordering Information table. Pages -4: Added "Boldface limits apply over the operating temperature range." to common conditions of Electrical Specs table. Replaced Note "Parts are 00% tested at C. Full temp limits are guaranteed by bench and tester characterization." with "Parameters with MIN and/or MAX limits are 00% tested at C, unless otherwise specified. Temperature limits established by characterization and are not production tested." About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at You may report errors or suggestions for improving this datasheet by visiting Reliability reports are also available from our website at FN490.

23 Package Outline Drawing E8. 8 LEAD DUAL-IN-LINE PLASTIC PACKAGE Rev., / 8 INDEX AREA TOP VIEW 0.80 (7.) 0.40 (.0) 0. (8.) 0.00 (7.) C L SEATING PLANE X 0.00 (0.) MIN 0.90 (4.) (.7) 0.9 (4.9) 0. (.9) -C- 0.0 (0.9) MIN (.) MAX (.8) 0. (.9) (7.) BSC 0.04 (0.) (0.04) 0.40 (0.9) MAX (.77) 0.04 (.) 0.0 (0.8) 0.04 (0.) 0.00 (.4) BSC SIDE VIEW NOTES:. Controlling Dimensions: INCH (Metric dimensions in parentheses).. Dimensioning and tolerancing per ANSI Y4.M-98.. Symbols are defined in the MO Series Symbol List in Section. of Publication No Dimensions are measured with the package seated in JEDEC seating plane gauge GS-.. Dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.00 inch (0.mm).. Dimensions are measured with the leads constrained to be perpendicular to datum -C-. 7. Dimension measured at the lead tips with the leads unconstrained. 8. Maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.00 inch (0.mm). 9. Package outline compliant to JEDEC MS-00-AC ISSUE D. FN490.

24 Small Outline Plastic Packages (SOIC) N INDEX AREA e D B 0.(0.00) M C A M E -B- -A- -C- SEATING PLANE A B S H 0.(0.00) M B A 0.0(0.004) NOTES:. Symbols are defined in the MO Series Symbol List in Section. of Publication Number 9.. Dimensioning and tolerancing per ANSI Y4.M-98.. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.mm (0.00 inch) per side. 4. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.mm (0.00 inch) per side.. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.. L is the length of terminal for soldering to a substrate. 7. N is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width B, as measured 0.mm (0.04 inch) or greater above the seating plane, shall not exceed a maximum value of 0.mm (0.04 inch). 0. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. L M h x 4 C M. (JEDEC MS-0-AC ISSUE C) LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A B C D E e 0.00 BSC.7 BSC - H h L N Rev. /0 4 FN490.

25 Package Outline Drawing M.7 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP) Rev, /0 A.00 ±0.0 9 SEE DETAIL "X" ±0.0 PIN # I.D. MARK 0.0 C B A 8 0. B TOP VIEW END VIEW H REF C SEATING PLANE 0.0 C SIDE VIEW.0 MAX / M C B A / MIN 0. MAX DETAIL "X" GAUGE PLANE ±0. 0. (.4) NOTES: (.) (0. TYP) (0. TYP) TYPICAL RECOMMENDED LAND PATTERN Dimension does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0. per side. Dimension does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed 0. per side. Dimensions are measured at datum plane H. Dimensioning and tolerancing per ASME Y4.M-994. Dimension does not include dambar protrusion. Allowable protrusion shall be 0.08mm total in excess of dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm. Dimension in ( ) are for reference only. Conforms to JEDEC MO-. FN490.

26 Small Outline Plastic Packages (SSOP) N INDEX AREA e D B 0.(0.00) M C A M E -B- -A- -C- SEATING PLANE A B S H 0.(0.00) M B A 0.0(0.004) NOTES:. Symbols are defined in the MO Series Symbol List in Section. of Publication Number 9.. Dimensioning and tolerancing per ANSI Y4.M-98.. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.0mm ( inch) per side. 4. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.0mm ( inch) per side.. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.. L is the length of terminal for soldering to a substrate. 7. N is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension B does not include dambar protrusion. Allowable dambar protrusion shall be 0.mm (0.00 inch) total in excess of B dimension at maximum material condition. 0. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. GAUGE PLANE A M L C M.09 (JEDEC MO-0-AC ISSUE B) LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A A B C D E e 0.0 BSC 0. BSC - H L N Rev. /0 FN490.

27 Small Outline Plastic Packages (SOIC) N INDEX AREA e D B 0.(0.00) M C A M E -B- -A- -C- SEATING PLANE A B S H 0.(0.00) M B A 0.0(0.004) NOTES:. Symbols are defined in the MO Series Symbol List in Section. of Publication Number 9.. Dimensioning and tolerancing per ANSI Y4.M-98.. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.mm (0.00 inch) per side. 4. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.mm (0.00 inch) per side.. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.. L is the length of terminal for soldering to a substrate. 7. N is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width B, as measured 0.mm (0.04 inch) or greater above the seating plane, shall not exceed a maximum value of 0.mm (0.04 inch) 0. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. L M h x 4 C M. (JEDEC MS-0-AA ISSUE C) LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A B C D E e 0.00 BSC.7 BSC - H h L N Rev. /0 7 FN490.

28 Small Outline Plastic Packages (SOIC) N INDEX AREA e D B 0.(0.00) M C A M E -B- -A- -C- SEATING PLANE A B S H 0.(0.00) M B A 0.0(0.004) NOTES:. Symbols are defined in the MO Series Symbol List in Section. of Publication Number 9.. Dimensioning and tolerancing per ANSI Y4.M-98.. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.mm (0.00 inch) per side. 4. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.mm (0.00 inch) per side.. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.. L is the length of terminal for soldering to a substrate. 7. N is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width B, as measured 0.mm (0.04 inch) or greater above the seating plane, shall not exceed a maximum value of 0.mm (0.04 inch) 0. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. L M h x 4 C M8. (JEDEC MS-0-AB ISSUE C) 8 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A B C D E e 0.00 BSC.7 BSC - H h L N Rev. /0 8 FN490.

29 Package Outline Drawing M0.7 0 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP) Rev, /0.0 ±0.0 A 0 0 SEE DETAIL "X" ±0.0 PIN # I.D. MARK 0.0 C B A 9 0. B TOP VIEW END VIEW H REF C SEATING PLANE 0.0 C / M C B A SIDE VIEW.0 MAX / MIN 0. MAX DETAIL "X" GAUGE PLANE ±0. 0. (.4) NOTES: (.) (0. TYP) (0. TYP) TYPICAL RECOMMENDED LAND PATTERN Dimension does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0. per side. Dimension does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed 0. per side. Dimensions are measured at datum plane H. Dimensioning and tolerancing per ASME Y4.M-994. Dimension does not include dambar protrusion. Allowable protrusion shall be 0.08mm total in excess of dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm. Dimension in ( ) are for reference only. Conforms to JEDEC MO-. 9 FN490.

30 Shrink Small Outline Plastic Packages (SSOP) N INDEX AREA e D B 0.(0.00) M C A M E -B- -A- -C- SEATING PLANE A B S H 0.(0.00) M B NOTES:. Symbols are defined in the MO Series Symbol List in Section. of Publication Number 9.. Dimensioning and tolerancing per ANSI Y4.M-98.. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.0mm ( inch) per side. 4. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.0mm ( inch) per side.. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.. L is the length of terminal for soldering to a substrate. 7. N is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension B does not include dambar protrusion. Allowable dambar protrusion shall be 0.mm (0.00 inch) total in excess of B dimension at maximum material condition. 0. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. A GAUGE PLANE 0.0(0.004) A M L C M0.09 (JEDEC MO-0-AE ISSUE B) 0 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A A B C D E e 0.0 BSC 0. BSC H L N deg. 8 deg. 0 deg. 8 deg. Rev. /0 0 FN490.

31 Package Outline Drawing M8.7 8 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP) Rev, /0 A ± 0.0 SEE DETAIL "X" ± 0.0 PIN # I.D. MARK 0.0 C B A 0. 4 B TOP VIEW END VIEW.00 REF C SEATING PLANE 0.0 C H MAX M C B A MIN 0. MAX GAUGE PLANE ±0. 0. SIDE VIEW DETAIL "X" (.4) NOTES:. Dimension does not include mold flash, protrusions or gate burrs. (.) Mold flash, protrusions or gate burrs shall not exceed 0. per side.. Dimension does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed 0. per side.. Dimensions are measured at datum plane H. 4. Dimensioning and tolerancing per ASME Y4.M Dimension does not include dambar protrusion. Allowable protrusion shall be 0.08mm total in excess of dimension at maximum material condition. Minimum space between protrusion and adjacent lead (0. TYP) TYPICAL RECOMMENDED LAND PATTERN (0. TYP). 7. is 0.07mm. Dimension in ( ) are for reference only. Conforms to JEDEC MO-. FN490.

32 Shrink Small Outline Plastic Packages (SSOP) N INDEX AREA e D B 0.(0.00) M C A M E -B- -A- -C- SEATING PLANE A B S H 0.(0.00) M B A 0.0(0.004) NOTES:. Symbols are defined in the MO Series Symbol List in Section. of Publication Number 9.. Dimensioning and tolerancing per ANSI Y4.M-98.. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.0mm ( inch) per side. 4. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.0mm ( inch) per side.. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.. L is the length of terminal for soldering to a substrate. 7. N is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension B does not include dambar protrusion. Allowable dambar protrusion shall be 0.mm (0.00 inch) total in excess of B dimension at maximum material condition. 0. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. GAUGE PLANE A M L C M8.09 (JEDEC MO-0-AH ISSUE B) 8 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A A B C D E e 0.0 BSC 0. BSC - H L N Rev. /0 FN490.

33 Small Outline Plastic Packages (SOIC) N INDEX AREA D e B 0.(0.00) M C A M E -B- -A- -C- SEATING PLANE A B S H 0.(0.00) M B A a 0.0(0.004) L M h x 4o C M8. (JEDEC MS-0-AE ISSUE C) 8 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A B C D E e 0.0 BSC.7 BSC - H h L N o 8 o 0 o 8 o - Rev., / TYPICAL RECOMMENDED LAND PATTERN (.0mm) (9.8mm) (.7mm TYP) (0.mm TYP) NOTES:. Symbols are defined in the MO Series Symbol List in Section. of Publication Number 9.. Dimensioning and tolerancing per ANSI Y4.M-98.. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.mm (0.00 inch) per side. 4. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.mm (0.00 inch) per side.. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.. L is the length of terminal for soldering to a substrate. 7. N is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width B, as measured 0.mm (0.04 inch) or greater above the seating plane, shall not exceed a maximum value of 0.mm (0.04 inch) 0. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO900 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see FN490.