Semiconductor Devices

Transcription

1 emicoductor evices Prof. Zbigiew Lisik epartmet of emicoductor ad Optoelectroics evices room: Uipolar devices IFE T&C

2 JFET Trasistor Uipolar evices - Trasistors asic features : the load curret I flows from the source electrode to the drai electrode - chael the juctio p+ -chael works i the reverse bias mode o carrier ijectio occurs, the carrier desities are equal to their equilibrium values the load curret ca be cosidered as the pure majority oe the device is cotrolled by the gate-source voltage U JFET

3 JFET Trasistor trasfer characteristics I I 1 U P U U is so small that it does ot ifluece the pheomea i the chael. The chael for curret flow is limited by the edges of the CR layers of both the p- juctios. ice N d >>N a the majority part of CR occurs i -chael layer. U = 0 U small I = I 1

4 JFET Trasistor trasfer characteristics I I 1 U P U Whe the magitude of U icreases the CR layers spreads ad the chael width decreases. If chael width is smaller, the chael resistace is larger ad the dre curret I decreases. U p < U < 0 U small I < I 1

5 JFET Trasistor trasfer characteristics I I 1 U P U Whe the magitude of U reaches U P, called pich-off voltage, the CR layers fill the whole chael area ad the chael disappears. If o chael with free curret carriers, i our case electros, exists, o curret betwee source ad dre ca flow. The trasistor is i its off-state. U = U p U small I = 0

6 JFET Trasistor output characteristics liear regio saturatio regio I I U = 0 U = U p U P U The presetatio of the pheomea caused by the icrease of U voltage is doe for the curve correspodig to U =0 (blue lie). At U =0, the maximal available magitude of the dre curret, I, ca be reached. U = 0 U = 0 I = 0

7 JFET Trasistor output characteristics liear regio I I U = 0 U = U p I the liear regio, the chael remais ope although the lateral voltage drop caused by the curret flow leads to chael shape modulatio As log as the discrepacy i chael width at source ad drai sides is egligibly small, the characteristics is liear but whe it becomes cosiderable, the characteristics beds. U P U = 0 U < U p 0 < I < I U

8 JFET Trasistor output characteristics saturatio regio P I I U = 0 U = U p U P U Whe the lateral voltage drop alog the chael reaches the value of pich-off voltage, U = U p, the bias of gate-chael juctio at the drai side is also U p. It meas that the areas of upper ad lower CR are joied ad the chael is iterrupted i this place. U = 0 U = U p I = I

9 JFET Trasistor output characteristics saturatio regio P I I U = 0 U = U p U P U I the saturatio regio, the coditios i chael regio are froze with the costat lateral voltage drop till the poit P of chael iterruptio. It causes the costat chael resistace betwee the source ad the poit P, ad the costat chael curret, I that is collected by CR regio ad trasferred to the drai regio. U = 0 U = U p I = I

10 JFET Trasistor output characteristics saturatio regio I I U = 0 U = U p U P U I the saturatio regio, the icrease of U voltage results i the icrease of CR layer due to the shift of its drai side border without ay chages i the drai curret, I. The magitude of the drai curret is govered by coditios i the remai part of the chael oly. U = 0 U = U p I = I

11 JFET Trasistor output characteristics saturatio regio I I U = 0 U = U p U P U Whe the gate-chael bias exists, U 0, the pich-off effect takes place at the lower U voltage with the larger chael resistace (its width is smaller) ad the lower drai curret. The border betwee liear ad saturatio regios has a parabola-like form determied by relatio: U P = U + U U < 0 U = U p I < I

12 Priciple of MI structure Let cosider the semicoductor resistor with two plaar cotacts, called ad, respectively. U + - L If the voltage U is applied to the resistor, it will result i the flow of curret I that magitude is: I I = U /R where R is the resistace betwee ad cotacts ice the curret flow takes place i the arrow thi layer oly, the resistace R will be determied by the layer dimesios ad resistivity, ad i particular, it is proportioal to the layer thickess L ad electro cocetratio : R ~ /L

13 Priciple of MI structure If the structure is completed by two electrodes: - placed o the botto surface ad called body - placed just above the upper surface ad called gate, it correspod to the itroductio of a ew compoet The ew electrodes itroduce the flat capacitor C with the electrode as the upper plate ad the electrode together with the semicoductor structure as the lower oe. They are separated by the air gap d that plays the role of dielectric layer. If the air gap is arrower, d smaller, the capacitor gather o the plate larger charge, Q at the same U bias.

14 Priciple of MI structure If the voltage U > 0 is applied to the capacitor C, o each of the plates the same charge Q, positive o gate electrode ad egative at the upper surface of semicoductor structure, respectively, is stored Q = U C I the curret carried layer, the electro desity icreases resultig i the degrease of R resistace accompayig by the icrease of I curret at the same U voltage. I the whole semicoductor structure, the equilibrium state coditios occurs - i.e. i the presece of the electro desity icrease, at ay poit 0 p 0 = i 2

15 Priciple of MI structure If the voltage U > 0 is applied to the capacitor C, o each of the plates the same charge Q, positive o gate electrode ad egative at the upper surface of semicoductor structure, respectively, is stored. Q = U C ielectric material I the curret carried layer, the electro desity icreases resultig i the degrease of R resistace accompayig by the icrease of I curret at the same U voltage I the whole semicoductor structure, the equilibrium state coditios occurs - i.e. i the presece of the electro desity icrease, at ay poit 0 p 0 = i 2 -

16 MOFET Trasistor overview Lateral devices the curret flows laterally ad all the cotacts (gate, source, drai) are o upper surface of the semicoductor chip basic applicatios: itegrated circuits ad power semicoductor devices for low power applicatios Verticalal devices the curret flows vertically, the gate ad source cotacts are o upper surface of the semicoductor chip whereas the drai cotact is at the bottom basic applicatios: power semicoductor devices for medium ad high power applicatios

17 MOFET Trasistor overview Itegrate Circuit applicatio substrate MO trasistor iscrete device applicatio + + lateral vertical

18 MOFET Trasistor overview MO trasistors ca be - or p-chael oes p-chael MO trasistors are maufactured i -substrate as i figures p p-chael MO trasistors cosists of two p-islads of source ad drai, respectively, which are separated by the area assiged for the chael the chael ca be build-i (upper figure) or iduced (lower figure)

19 MOFET Trasistor build-i chael p CR uild-i chael itroduces the path for curret flow betwee source ad drai as well as the additioal p- juctio ad its juctio capacitor. imilarly as JFET, it is ormally o trasistor that chael is modulated by the CR layer of reverse biased juctio. Normally o trasistors are called depletio mode trasistors C g C j

20 MOFET Trasistor iduced chael C g No path for curret flow betwee source ad drai is maufactured ad from this poit of view the coectio source-drai forms two ati-parallel coected diodes. The chael ca be formed by the pheomea takig place i semicoductor just below the gate electrode.

21 MOFET Trasistor iduced chael Ideal techology of dielectric layer o chages i semicoductor Q C = 0 U C = 0 Ideal techology processes of dielectric layer that is deposited o ideal semicoductor structure. No ios build-i ito the dielectric layer or coected with the surface state i semicoductor. No build-i charge ad build-i bias at gate-body capacitor

22 MOFET Trasistor iduced chael Real techology of dielectric layer accumulatio layer i semicoductor _ Q C 0 U C > 0 I dielectric layer, the build-i charge of trapped positive ios occurs. It is compesated by a equivalet egative charge of additioal electros collected i thi layer just below the dielectric, which is called a accumulatio layer. The gate-body capacitor bias correspods to the stored charge Q C. It is ormally off ehaced mode trasistor

23 MOFET Trasistor iduced chael Real techology of dielectric layer iversio layer i semicoductor _ Q C 0 U C > 0 I dielectric layer, the build-i charge of trapped egative ios occurs. It is compesated by a equivalet positive charge of holes i thi layer just below the dielectric. If i the layer p 0 > 0, it becomes p-type layer called a iverse layer joiig both the p-islads. The gate-body capacitor bias correspods to the stored charge Q C. It is ormally o depletio mode trasistor

24 MOFET Trasistor iduced chael Ehaced mode trasistor I U T U U = 0 accumulatio layer occurs at the surface the surface electro cocetratio is larger that the bulk oe o curret flows U = 0 U small I = 0

25 MOFET Trasistor iduced chael Ehaced mode trasistor I U T U U = U T (threshold voltage) itrisic coditio at the surface ( 0 =p 0 ), o curret drai U = U T U small I = 0

26 MOFET Trasistor iduced chael Ehaced mode trasistor I U T U U > U T at the surface, p-type iversio layer occurs ad creates the p-chael joiig source ad drai p-islads the drai curret ca flow U > U T U small I > 0

27 MOFET Trasistor trasfer characteristics Ehaced mode trasistor I I U = U T U T U U Trasiet characteristic Family of output characteristics

28 MOFET Trasistor trasfer characteristics epletio mode trasistor I I U = 0 U p U U Trasiet characteristic Family of output characteristics