Implementations of CNN-based image processing and adaptive optic system on FPGA

Transcription

1 Implementations of CNN-based image processing and adaptive optic system on FPGA Ph.D. Theses Zoltán Kincses Supervisor: Péter Szolgay (DSc) University of Pannonia Doctoral School of Information Science and Technology Veszprém 2012

2 1. Introduction, problem statement The CNN (Cellular Neural Array) consists of a rectangular array of fully equivalent analogue processing elements, so-called cells. Cells can only communicate with their neighbors (3x3, 5x5, 7x7) using programmable connections. The strength of the synaptic connections is defined by the weighting factors (templates), which essentially define the program of the CNN structure. Two groups of the templates can be distinguished: linear and nonlinear templates. Linear templates contain only constant values. Nonlinear templates are nonlinear functions of some parameters of the actual cell (input, output, state) or some parameters of the actual and neighboring cell (difference). Therefore, in case of linear templates, the state, the input or the output of the cell should be weighted with the actual template value. However, in case of nonlinear templates, nonlinear template values defined by the nonlinearity are the weighted values of the state, the input or the output of the actual cell. Basically, four implementations of the CNN were developed. These are the analog VLSI (Very Large Scale Integration), the emulated digital VLSI, the optical implementations, and the software simulation. Analog VLSI implementations (Ace400, Ace4K, Ace16k, Xenon, Eye-Ris) have the highest computational speed (8-9 TerraOP), but their accuracy is relatively low and these devices are very sensitive to the small fluctuations of supply voltage and temperature, and only linear templates can be used. In emulated digital VLSI implementations, the ASIC (Application Specific Integrated Circuits) (for example: CASTLE processor) and the FPGA (Field Programmable Gate Array) (for example: FALCON) based implementations can be distinguished. These implementations are slower than the analogue ones, but they are more flexible, easily configurable, they have a shorter design cycle time, they are surface optimized (low dissipated performance), and they are suitable for digital platforms. Optical implementations (for example: POAC, Programmable Optical Array Computer) support extremely high speed and high resolution image processing, realizing the feedback is complicated, it requires a large silicon area, and only linear templates can be used. Software simulation (for example: SimCNN, MatCNN) is the simplest, most flexible implementation of the CNN, in which floating point calculation and 1

3 nonlinear templates can be used, but it is very slow when using the commercially available 2-, 3-, or 4-core desktop computers, even in case of optimized program codes (Intel Core i5, AMD Phenom X2- X4). In the era of software simulation, multiprocessor array computers, which give a much faster solution than the processors used in desktop computers, are increasingly coming to the front. Such a processor is for example the Cell Broadband Engine (CBEA, shortly Cell), which was designed for the Sony PlayStation 3 by the collaboration of IBM, Sony and Toshiba. This array processor consists of one 64 bit PowerPC and eight 128 bit SIMD (Single Instruction Multiple Data) instruction set RISC (Reduced Instruction Set Computing) cores. The IBM Blade Center QS20 system contains two Cell processors communicating via a high bandwidth interface, and its maximal computing performance is 400 GFLOPS (Floatingpoint Operation Per Second). In one Blade center house, seven QS20s can be connected. With this configuration, a 2.8 TFOLPS computational performance can be achieved. Using the newest generations of IBM Blade Center, QS22 blades, a 6.4 TFLOPS single and 3 TFLOPS double precision computing speed can be reached. In the field of the spatiotemporal effects of physics/chemistry, problems where the relationship between the output, input and state variables are nonlinear have a high importance. Such problems are the Euler or Navier-Stokes partial differential equations, which describe non-viscid or viscid fluid flows. Although several studies proved the effectiveness of the application of the CNN to solve partial differential equations, nonlinear templates should be used to solve problems mentioned above. In addition, there are several problems in the field of image processing too, where nonlinear templates should be used in the CNN-based solution. Such problems are the Median-filter, or the computation of the Sum of Absolute Differences (SAD), which is used in the block based motion estimation to determine the optimal fit of the actual and reference image. For the CNN-based solution of both tasks, 3x3 nonlinear D-type templates are required (the relation of the input and the state is nonlinear). However, the present analog/hybrid CNN implementations do not support nonlinear templates. One possible way to be able to handle nonlinear templates 2

4 is extending the capabilities of the emulated digital FALCON processor. I intend to investigate the possibility of the CNN-based solution of nonlinear partial differential equations and the possibility to implement different image processing tasks such as SAD operator using FPGA. This issue is important because the SAD operator is not only usable in the field of block based motion estimation, but it can also be used in one of the most important part of the AO (Adaptive Optic) system, namely in the FPGA based HS (Hartmann-Shack) wavefront sensor. The wavefront of the incoming light distorted by the rapidly changing turbulent media can be dynamically compensated by the AO systems using deformable mirrors (Micro- Electro-Mechanical Systems (MEMs)) or other actuator devices. Wavefront distortion data is measured by the wavefront sensor. The performance of an image processing system can be drastically increased by using an AO system. 3

5 2. Performed investigations, employed methods I studied the CNN Template Library v3.1, and I gave a classification of the nonlinear templates. Using this classification, I investigated the existing FALCON emulated digital CNN-UM implementation, and extended its capabilities to handle two types of nonlinearity. I optimized the area requirement and investigated the performance of the new architecture in case of different computational precisions, and compared it to the original architecture. I used a C-based high level hardware description language called Handle-C, and the Celoxica DK Design Suite development platform to implement the architecture. I implemented the architecture on an RC-203 development board which contains a Xilinx Virtex-II 3000 FPGA designed by the Celoxica. Further on, I implemented the architecture using the VHDL (Very High Speed Integrated Circuit Hardware Description Language) hardware description language in the Xilinx Foundation ISE (Integrated Software Environment) development platform, and tested it using the ModelSim VHDL simulator. I also tested the area requirement and computational performance of this VHDL-based architecture, using some models of the Xilinx Virtex FPGA family (Virtex-6 and Virtex-7). These investigations were required because there are architectural differences in this family (6 input LUT since the Virtex- 5 family), and I investigated the effects of these modifications to the area and performance parameters of the architecture. Area requirement and computational performance of the architectures are carried out by using the Xilinx Foundation ISE tools. In the second half of my research, I dealt with the implementation of an FPGA-based HS wavefront sensor. A compact FPGA-based adaptive optic system was developed in MTA- SZTAKI, which can be seen in Figure 1. The system has three main parts: a high speed CMOS (Complementary Metal-Oxide Semiconductor) sensor, a very high speed LCOS (Liquid Crystal on Silicon) display, and an FPGA, which is responsible for controlling and computing tasks. 4

6 Philips LCOS display Xilinx Spartan-3 FPGA Cypress USB controller Lenslet Micron CMOS sensor Samsung memories Figure 1. Structure of the compact adaptive optic system Distortions of the wavefront of the incoming light is sensed by the CMOS sensor and the FPGA (HS wavefront sensor). Based on these data, the required corrections are computed by the FPGA and are finally displayed by the LCOS display, removing the distortions of the wavefront of the incoming light. I used the SAD operator to implement the FPGA-based wavefront sensor. I designed a nonlinear template which realizes the SAD operator, and implemented it on a nonlinear template runner emulated digital CNN-UM as a wavefront sensor. I optimized the area requirement of this architecture, and investigated its maximal reachable computation performance in case of different size of SAD operators. To improve the performance of the architecture, the special hardware requirement of the adaptive optic board was taken into account. Since the performance of the architecture was below the expectations, I redesigned the architecture and implemented a high-speed architecture which was specialized for this task. Area requirement and computational performance of this architecture was also tested, and compared to other similar systems. The emulated digital CNN-UM-based and the specialized wavefront sensor architecture was designed using the VHDL hardware description language. The ModelSim VHDL simulator and the Xilinx Foundation ISE tool were used during testing and implementation. Although I conducted my investigations using a Xilinx development environment, the VHDL description of the architecture is universal. 5

7 3. New scientific results 1. Thesis group: Implementation of nonlinear template runner emulated digital CNN-UM on FPGA Using present CNN implementations except for the slow software simulation there are no possibilities to use nonlinear templates. In case of some tasks which can be solved by a CNN (for example: gradient intensity estimation, grayscale contour detection), this inadequacy can be eliminated, because nonlinear B templates can be decomposed into a series of linear templates. Naturally, this substitution is more complicated than applying one nonlinear template, even if the result is the same. However, template decomposition cannot be used in case of several tasks (median filter, the previously mentioned SAD operator, grayscale erosion/dilation, histogram generation), where nonlinear A or D-type templates should be applied. Therefore, the only way to solve these tasks is the application of nonlinear templates. In the course of studying the CNN Template Library v3.1, I classified the nonlinear templates based on the nonlinearity defined by the nonlinear template values into two groups. These are the zero- and first-order nonlinear templates. A template is called a zeroorder nonlinear template if the nonlinear function of the template only contains constant sections. A template is called a first-order nonlinear template if the nonlinear function of the template contains first-order linear functions of the variables. I extended the FALCON emulated digital CNN-UM architecture to handle zero- and first-order nonlinear templates taking into account their special requirements. I measured the area requirement and computational speed of these architectures and compared them to the results of the original linear FALCON architecture and the software simulation (MatCNN, Intel Core i5 M GHz). My investigations show that the computational performance of the zeroand first-order FALCON processor is significantly higher than the performance of the software simulation. 6

8 1.1. Implementation of the zero-order nonlinear template runner emulated digital CNN-UM architecture on FPGA I gave the extension of the FALCON emulated digital CNN- UM for the application of zero-order nonlinear templates. I redesigned the template-handling part of the FALCON processor, to make it able to store the constant values of the sections of the zeroorder nonlinearity, and based on these values, to determine the nonlinear template values. I analyzed the area requirement and computating performance of the extended architecture in case of different FPGA families (Virtex-II, Virtex-4, Virtex-6, Virtex-7). I showed that in case of Virtex-6 XC6VS475T and Virtex-7 XC7VX9800T type FPGAs, 168 processors can be implemented on Virtex-6 and 300 processors can be implemented on Virtex-7 independently from the bit width of the state value. I showed that the maximal computational performance is million celliterations/second when implementing a 168 zero-order FALCON processor on Virtex-6 FPGA using 18 bit state width, and the Virtex- 7 FPGA is almost 2-times (1.786) faster. Compared these results to the software simulation, where the maximal computational performance is 13 million celliterations/second, the performance is increased by 3 orders of magnitude Implementation of first-order nonlinear template runner emulated digital CNN-UM architecture on FPGA I gave the extension of the FALCON emulated digital CNN- UM for the application of first-order nonlinear templates. In this case, the template memory of the FALCON processor is also extended with the appropriate adder and multiplier circuits to be able to determine the nonlinear template values. I analyzed the area requirement and computing speed of the extended architecture in case of different FPGA families (Virtex-II, Virtex-4, Virtex-6, Virtex-7). I showed that in case of Virtex-6 XC6VSX475T and Virtex-7 XC7VX9800T type FPGAs, first-order FALCON processors can be implemented on Virtex-6 and first-order FALCON processors can be implemented on Virtex-7, depending on the bit width of the state value. I showed that the maximal computational 7

9 performance is million celliterations/second when implementing 112 first-order FALCON processors using 18 bit state width on Virtex-6 FPGA, while the Virtex-7 FPGA is almost 2-times (1.786) faster. In this case, both FPGAs offer 3 orders of magnitude higher performance compared to the software simulation where the maximal computing speed is 9 million celliterations/second. 2. Thesis group: Implementing a SAD operator-based wavefront sensor architecture on an FPGA-based adaptive optic system. AO systems have a great importance in the field of astronomy. However, it is also becoming increasingly important in the field of military and medicine (ophthalmology). Therefore, these systems can be applied in fields where the goal is creating pictures with high exposition time and high resolution. The rapidly changing turbulent media can modify or distort the wavefront (the wavefront is a line or surface of the points which are in the same phase) of the incoming light. The performance of the imaging system is significantly deteriorated by this phenomenon. The goal of the adaptive optic system is to eliminate the distortions of the wavefront. The adaptive optic system is built up of two main components, the adaptive mirror and the wavefront sensor. Distortions of the wavefront are continuously measured by the wavefront sensor. Based on these measurements, the control system can modify the surface of the adaptive mirror continuously, to compensate the distortions of the wavefront. The HS wavefront sensor, which is frequently applied in adaptive optic systems, is basically built up of two parts, the lenslet array and the CCD (Charge-Coupled Device) or CMOS sensor. In a HS sensor, the image of the incoming pupil is projected on a lenslet array. Each lens of the array forms a miniature image of the source object and divides the incoming aperture into sub-apertures. The images of these sub-apertures are detected by the CCD or CMOS sensor. The shifts of these images from the reference positions (positions without aberrations) specify the local wavefront slopes at the locations of the corresponding sub-apertures (the wavefront is regarded locally flat but tilted). The overall shape of the wavefront extended for the whole pupil can be reconstructed by assembling all these local tilted surfaces with the adaptive optic system. 8

10 For a point source object (such as a star), simple quad-cell based HS sensors can measure these shifts. However, in the case of extended objects (the Sun or the Moon), these shifts can be determined only with a higher resolution sensor from the correlations between the sub-aperture images and the reference sub-aperture images. In this case, a higher computational speed is required, moreover, correcting ability of the adaptive optic system is better if the delay between sensing the wavefront and correction is smaller than the evolution time of the medium being corrected for. To eliminate these problems, a novel FPGA-based compact adaptive optic system was developed in MTA-SZTAKI (Figure 1). My task was to implement the wavefront sensor part of this system. Considering the limitation of the FPGA devices and the special parameterization of the mandatory wavefront sensors, the Sum of Absolute Differences (SAD) method was chosen to implement the required correlation-like processing. First, the SAD values of the picture are calculated, and the minimum of them is determined. With this method, the displacement of the images of all sub-apertures is determined with respect to a reference image Nonlinear template runner emulated digital CNN-UM as SAD-based wavefront sensor architecture. I gave the implementation of the SAD operator-based wavefront sensor on the FALCON architecture extended with nonlinear templates, and I investigated the effectiveness of this architecture. I showed that the general and dedicated resource requirement of the SAD operator runner FALCON processor is essentially the same as the original first-order FALCON processor. It only requires one additional BlockRAM. I showed that using the Spartan-3 XC3S4000 FPGA on the adaptive optic card, the number of implementable extended FALCON processors is 8. Using all these processors, a 320 million celliterations/second computing performance can be reached in case of 3x3 pixels sub-apertures and 5x5 pixels reference image. I showed that when the sub-aperture size is increased to 16x16 (commonly used in real applications), only 3 extended FALCON processors can be implemented, and the maximal computing performance is 120 million celliterations/second. In order to improve 9

11 the computational performance of the architecture and to suit the requirement of the adaptive optic board, I redesigned the architecture to create a high speed special purpose architecture Optimal implementation of SAD operator based wavefront sensor on FPGA-based adaptive optic card. I gave the optimized FPGA-based implementation of the SAD operator-based wavefront sensor architecture. I analyzed the area requirement and computational speed of the architecture in case of different kinds of FPGA families (Virtex-II, Virtex-4, Virtex- 6, Virtex-7). I showed that the general and dedicated resource requirement of the SAD unit, which is the central part of the wavefront sensor, is increasing quadratically according to the size of the sub-apertures. I showed that in case of Spartan-3 XC3S4000 FPGA using one 120MHz SAD unit x8 pixels and x32 pixels sized subapertures can be processed in real time. I showed that using the significantly larger Virtex-7 XC7V2000T FPGA, where the clock frequency of the SAD unit can reach the 300Mhz, the whole CMOS surface can be processed in real time. I showed that in case of 8x8 pixels and 16x16 pixel sized sub-apertures, the AT (Area Time) parameter of my system is 29%, and 22% better respectively than the traditional correlation-based system. Compared to other SAD based architectures, my architecture shows superior performance (in case of 16x16 pixels sub-aperture: slice and 496 clock cycles facing 9478 slice and 1600 clock cycles). 10

12 4. Application of the new experimental results i) Using the nonlinear template runner emulated digital FALCON architecture, it is possible to solve partial differential equations which describe processes with different spatiotemporal dynamics. The extended FALCON processor is able to solve PDEs, which describe viscid and non-viscid fluid flow at least 3 orders of magnitude faster than software simulation. In addition, the processor can be parametrized arbitrarily according to the problem needed to be solved. Since the extended FALOCN processor was implemented using VHDL hardware description language, the architecture can be implemented on arbitrary Xilinx FPGAs. In the field of image processing, the basic part of the digital video compression is motion estimation. One implementation method is the block-based motion estimation, where the optimal fit of the two images should be determined. For example, using the SAD operator this optimal fitting position can be determined. The SAD operator can be calculated by using my nonlinear template runner emulated digital FALCON processor. Not only the SAD operator, but different nonlinear templates can also be implemented, for example the Median-filter or Erosion/Dilation templates. ii) In astronomy, the observation of extended objects such as the Sun with large telescopes requires high resolution correlation based HS sensors to measure the distortions of the wavefront of the incoming light wave. The variations of the wavefront follow the variations of the atmosphere. In the visible region of the wavelength, these variations are millisecond length. The implemented wavefront sensor needs to follow these variations. The FPGA-based AO system developed in MTA-SZTAKI contains the required high resolution HS sensor and can compensate distortions in real time. Thanks to this the system well applicable in the field of astronomical observation of extended objects (Figure 2.). The turbulent nature of the atmosphere also deteriorates the performance of the remote control of satellites, so the system can also be applied in this field. 11

13 Figure 2. The AO system in astrology High performance telescopes are also used in the military applications, for different monitoring tasks. In case of these telescopes, similarly to the telescopes in astrology, the distortion of the wavefront of the incoming light wave also causes problem, which deteriorate the resolution of the telescopes. In order to improve the resolution of these telescopes, this AO system can also be used. In the field of medical imaging in ophthalmology, the pictures of the retina of the living human is also deteriorated by the imperfect human eyepiece. The distortions are caused by the eyepiece can also be eliminated by the help of the AO system. (Figure 3.). Figure 3. The AO system in the ophthalmology 12

14 In microscopy, the aberrations generated by the sample on the object table can also be eliminated by the proposed AO system (Figure 4.). Figure 4. Adaptive optics in microscopy 13

15 5. List of publications Journal papers: Z. Nagy, L. Kék, Z. Kincses, A. Kiss, P. Szolgay: Toward Exploitation of Cell Multi-processor Array in Time-Consuming Applications by Using CNN Model (International Journal of Circuit Theory and Applications, Wiley, Vol. 36., Special Issue: Cellular Wave Computing Architecture, July-September pp IF: , ISSN: ) Z. Kincses, L. Orzó, Z. Nagy, Gy, Mező, P. Szolgay: High-speed, SAD based wavefront sensor architecture implementation on FPGA (Journal of Signal Processing Systems, Springer, DOI: /s , 2011, IF: , Vol. 63, pp , ISSN: ) International conference papers: Z. Kincses, Z. Nagy, P. Szolgay: "Implementation of nonlinear template runner emulated digital CNN-UM on FPGA" (CNNA 2006, Turkey, Istambul, August 28-30) Z. Nagy, L. Kék, Z. Kincses, P. Szolgay: "CNN model on Cell multiprocessor array" (ECCTD 2007, Spain, Sevilla, August ) Z. Nagy, L. Kék, Z. Kincses, A. Kiss, P. Szolgay: "Toward Exploitation of Cell Multi-processor Array in Time-Consuming Applications by Using CNN Model" (CNNA 2008, Spain, Santiago de Compostela, July ). Z. Kincses, Z. Nagy, L. Orzó, P. Szolgay, Gy. Mező: "Implementation of a parallel SAD based wavefront sensor architecture on FPGA" (ECCTD 2009, Turkey, Antalya, August ) 14

16 Z. Kincses, Zs. Vörösházi, Z. Nagy, P. Szolgay, P. Szolgay, T. Laviniu, A. Gacsádi: Investigation of area and speed trade-offs in FPGA implementation of an image correlation algorithm (CNNA 2012, Turin, Italy, August ) Hungarian conference papers: Z. Kincses (2009): "High-speed, SAD based wavefront sensor architecture implementation on FPGA", Proceedings of the 7th PhD Mini-Symposium, University of Pannonia, Veszprém Kincses Z. (2008), "Toward Exploitation of Cell Multi-processor Array in Time-Consuming Applications by Using CNN Model", Proceedings of the 6th PhD Mini-Symposium, University of Pannonia, Veszprém Kincses Z. (2007), "CNN model on Cell multiprocessor array", Proceedings of the 5th PhD Mini-Symposium, University of Pannonia, Veszprém 15