Applications of algorithms for image processing using programmable logic

Transcription

1 Applications of algorithms for image processing using programmable logic Presented by: Nikolay Nenov, M. Sc. Ph. D. Student at the Technical University of Sofia Research director: Todor Djamiykov, Assoc. Prof. Dr. Ohrid 2006 Ohrid, September

2 Features Implementation in Optoelectronic measurement system Work with frames from CMOS image sensor Processing in real time High speed Implementation in FPGA Ohrid, September

3 CMOS image frames Continuous generation Data for image is generated pixel by pixel High Bit rate up to 20Mbps Free of Data time in each frame Structure of the CMOS frame Ohrid, September

4 The algorithms RGB to Grayscale conversion Interpolation of the green pixels Median filtration Thresholding Centre of mass calculation SVGA video interface for monitor Ohrid, September

5 RGB to Grayscale conversion - description Use neighbor pixels FIFO for one line from the image with BlockRAM in FPGA Y = 0,59G + 0,3R + 0,B Structure of the module Processing during data cycle of the CMOS frame How it works Ohrid, September

6 RGB to Grayscale conversion - results Device utilization summary: Selected Device: 3s400pq208-4 Number of Slices: 30 out of % Number of Slice Flip Flops: 93 out of 768 % Number of 4 input LUTs: 2 out of 768 2% Number of MULT8X8s: 4 out of 6 25% Number of GCLKs: out of 8 2% Timing Summary: Speed Grade: -4 Minimum period: ns (Maximum Frequency: MHz) Minimum input arrival time before clock: 5.208ns Maximum output required time after clock: 7.347ns Example RGB frame Disadvantages: - complicated equations - additional memory, - dead line and row in output image Output frame Ohrid, September

7 Interpolation of the green pixels - description Green color is most informative Use two neighbor green pixels in the line Y = (Gn + Gn+) / 2 Processing during data cycle of the CMOS frame Bayer matrix Green interpolation Ohrid, September

8 Interpolation of the green pixels - results MathCAD Simulation Device utilization summary: Selected Device : 3s400pq208-4 Number of Slices: 32 out of % Number of Slice Flip Flops: 4 out of 768 0% Number of 4 input LUTs: 4 out of 768 0% Number of bonded IOBs: 2 out of 4 4% Number of GCLKs: out of 8 2% Output image Timing Summary: Speed Grade: -4 Minimum period: 5.52ns (Maximum Frequency: MHz) Minimum input arrival time before clock: 6.250ns Maximum output required time after clock: 6.27ns Bayer Pattern Ohrid, September

9 Median filtration Use two neighbor green pixels in the line and current pixel Eliminate defect pixels in the frame Reduce noises Y = med (Y, Y2, Y3) Processing during data cycle of the CMOS frame Performance Device utilization summary: Selected Device : 3s400pq208-4 Number of Slices: 46 out of 3584 % Number of Slice Flip Flops: 39 out of 768 0% Number of 4 input LUTs: 76 out of 768 % Number of bonded IOBs: 2 out of 4 4% Number of GCLKs: out of 8 2% Timing Summary: Speed Grade: -4 Minimum period: 8.039ns (Maximum Frequency: MHz) Minimum input arrival time before clock: 8.92ns Maximum output required time after clock: 6.27ns Ohrid, September

10 Thresholding algorithm of Hamadani Uses mean value and standard deviation of the frame m = σ = M. N. M N i= j= M N M N i= j= ε ( i, ( ε ( i, j) j) m) 2 - Mean value - Standard deviation T = k.m + k2.σ - Threshold level ε(i,j) image M,N dimensions of the image k, k2 fitting coefficients Ohrid, September

11 Threshold algorithm - implementation Processing in both cycles of the CMOS frame Calculated Threshold level is used in the next frame Data Cycle n M N m = ε ( i, j) i= j= M N = ( ( n i, j ) m ) 2 n i= j = σ ε Processing Cycle mn = m M. N σ 2n = σ M. N n n σ n = σ 2 n T = k.m n + k2.σ n Ohrid, September

12 Centre of mass (COM) calculation - description Uses all pixels belong to the object Xc p i= = p i= XiEi Ei - X Coordinate Yc p i= = p i= YiEi Ei - Y Coordinate p number of pixels in the object Xc,Yc Coordinates of COM E intensity of the pixels Ohrid, September

13 Centre of mass (COM) calculation - implementation Processing in both cycles of the CMOS frame Data Cycle Processing Cycle X = Y = E = p i= p i= p i= XiEi YiEi Ei Xc = Yc = X E Y E Ohrid, September

14 SVGA video interface for monitor Resolution - SVGA (800x600) Frame rate - 60Hz 256 gray levels Ohrid, September

15 SVGA video interface - results Device utilization summary: Selected Device : 3s400pq208-4 Number of Slices: 93 out of % Number of Slice Flip Flops: 93 out of 768 % Number of 4 input LUTs: 64 out of 768 2% Number of bonded IOBs: 68 out of 4 48% Number of GCLKs: 3 out of 8 37% Timing Summary: Speed Grade: -4 Minimum period: 6.283ns (Maximum Frequency: 59.60MHz) Minimum input arrival time before clock: 7.229ns Maximum output required time after clock: 8.35ns Results Ohrid, September

16 Thank You for Your attention! Ohrid, September