Short Course On Phase-Locked Loops and Their Applications Day 1, PM Lecture. Advanced Analog Frequency Synthesizers, Clock and Data Recovery

Transcription

1 Short Course On Phase-Locked Loops and Their Applications Day 1, PM Lecture Advanced Analog Frequency Synthesizers, Clock and Data Recovery Michael Perrott August 11, 2008 Copyright 2008 by Michael H. Perrott All rights reserved.

2 Bandwidth Constraints for Integer-N Synthesizers 1/T Loop Filter Bandwidth << 1/T ref(t) (1/T = 20 MHz) PFD Loop Filter out(t) Divider N[k] PFD output has a periodicity of 1/T - 1/T = reference frequency Loop filter must have a bandwidth << 1/T - PFD output pulses must be filtered out and average value extracted Closed loop PLL bandwidth often chosen to be a factor of ten lower than 1/T 2

3 Bandwidth Versus Frequency Resolution 1/T Loop Filter Bandwidth << 1/T ref(t) (1/T = 20 MHz) PFD Loop Filter out(t) Divider N[k] N[k] out(t) S out (f) 1/T frequency resolution = 1/T GHz Frequency resolution set by reference frequency (1/T) - Higher resolution achieved by lowering 1/T 3

4 Increasing Resolution in Integer-N Synthesizers 1/T Loop Filter Bandwidth << 1/T 20 MHz 100 ref(t) (1/T = 200 khz) PFD Loop Filter out(t) Divider N[k] 9001 N[k] 9000 out(t) frequency resolution = 1/T S out (f) 1/T GHz Use a reference divider to achieve lower 1/T - Leads to a low PLL bandwidth ( < 20 khz here ) 4

5 The Issue of Noise 1/T Loop Filter Bandwidth << 1/T 20 MHz 100 ref(t) (1/T = 200 khz) PFD Loop Filter out(t) Divider N[k] 9001 N[k] 9000 out(t) frequency resolution = 1/T S out (f) 1/T GHz Lower 1/T leads to higher divide value - Increases PFD noise at synthesizer output 5

6 Modeling PFD Noise Multiplication PFD-referred Noise S En (f) 0 f 1/T e n (t) VCO-referred Noise S Φvn (f) 0-20 db/dec f Φ vn (t) Radians 2 /Hz 0 (f o ) opt α π N 2 S en (f) S Φvn (f) f Φ npfd (t) Divider Control Φ c (t) of Frequency Setting (assume noiseless for now) f o α π N G(f) Φ n (t) f o Φ nvco (t) Φ out (t) Influence of PFD noise seen in model from Lecture 16 - PFD spectral density multiplied by N 2 before influencing PLL output phase noise 1-G(f) Radians 2 /Hz 0 S Φnpfd (f) (f o ) opt S Φnvco (f) f High divide values high phase noise at low frequencies 6

7 Outline Of Talk Dual-loop Synthesizers Direct Digital Synthesizers Fractional-N Synthesizers - Traditional Approach - Sigma-Delta Concepts - Synthesizer Noise Analysis 7

8 Dual-Loop Frequency Synthesizer ref 1 PFD Loop Filter Divider VCO cos(w 1 t) sin(w 1 t) out ref 2 PFD N Loop Filter Divider VCO cos(w 2 t) sin(w 2 t) Single-sideband Mixer Overall synthesizer output M From trigonometry: cos(a-b) = cosacosb+sinasinb 8

9 Advantage #1: Avoids Large Divide Values ref 1 PFD Loop Filter Divider VCO cos(w 1 t) sin(w 1 t) out ref 2 PFD N Loop Filter Divider VCO cos(w 2 t) sin(w 2 t) Single-sideband Mixer M Choose top synthesizer to provide coarse tuning and bottom synthesizer to provide fine tuning - Choose w 1 to be high in frequency Set ref 1 to be high to avoid large N low resolution - Choose w 2 to be low in frequency Allows ref 2 to be low without large M high resolution 9

10 Advantage #2: Provides Suppression of VCO Noise ref 1 PFD Loop Filter Divider VCO cos(w 1 t) sin(w 1 t) out ref 2 PFD N Loop Filter Divider VCO cos(w 2 t) sin(w 2 t) Single-sideband Mixer M Top VCO has much more phase noise than bottom VCO due to its much higher operating frequency - Suppress top VCO noise by choosing a high PLL bandwidth for top synthesizer High PLL bandwidth possible since ref 1 is high 10

11 Alternate Dual-Loop Architecture ref 1 PFD Loop Filter VCO cos(w 1 t) sin(w 1 t) out Divider y ref 2 PFD N Loop Filter Divider VCO cos(w 2 t) sin(w 2 t) Single-sideband Mixer Calculation of output frequency M 11

12 Advantage of Alternate Dual-Loop Architecture ref 1 PFD Loop Filter cos(w 1 t) sin(w 1 t) out VCO Divider y ref 2 PFD N Loop Filter cos(w 2 t) sin(w 2 t) VCO Divider Single-sideband Mixer M Issue: a practical single-sideband mixer implementation will produce a spur at frequency w 1 + w 2 PLL bandwidth of top synthesizer can be chosen low enough to suppress the single-sideband spur - Negative: lower suppression of top VCO noise 12

13 Direct Digital Synthesis (DDS) clk Counter ROM DAC LPF out Encode sine-wave values in a ROM Create sine-wave output by indexing through ROM and feeding its output to a DAC and lowpass filter - Speed at which you index through ROM sets frequency of output sine-wave Speed of indexing is set by increment value on counter (which is easily adjustable in a digital manner) 13

14 Pros and Cons of Direct Digital Synthesis clk Counter ROM DAC LPF out Advantages - Very fast adjustment of frequency - Very high resolution can be achieved - Highly digital approach Disadvantages - Difficult to achieve high frequencies - Difficult to achieve low noise - Power hungry and complex 14

15 Hybrid Approach clk Counter ROM DAC LPF ref PFD Loop Filter VCO out Divider Use DDS to create a finely adjustable reference frequency Use integer-n synthesizer to multiply the DDS output frequency to much higher values Issues - Noise of DDS is multiplied by N 2 - Complex and power hungry N 15

16 Fractional-N Frequency Synthesizers ref(t) (1/T = 20 MHz) PFD Loop Filter out(t) N sd [k] Dithering Modulator N[k] Divider N sd [k] out(t) S out (f) 1/T frequency resolution << 1/T GHz Break constraint that divide value be integer - Dither divide value dynamically to achieve fractional values - Frequency resolution is now arbitrary regardless of 1/T Want high 1/T to allow a high PLL bandwidth 16

17 Classical Fractional-N Synthesizer Architecture ref(t) PFD e(t) Loop Filter out(t) div(t) N/N+1 frac[k] Accumulator 1-bit carry_out[k] N sd [k] = N + frac[k] Use an accumulator to perform dithering operation - Fractional input value fed into accumulator - Carry out bit of accumulator fed into divider 17

18 Accumulator Operation clk(t) frac[k] M-bit Accumulator M-bit 1-bit residue[k] carry_out[k] residue[k] frac[k] =.25 carry_out[k] Carry out bit is asserted when accumulator residue reaches or surpasses its full scale value - Accumulator residue increments by input fractional value each clock cycle 18

19 Fractional-N Synthesizer Signals with N = 4.25 carry_out(t) out(t) div(t) ref(t) e(t) phase error(t) Divide value set at N = 4 most of the time - Resulting frequency offset causes phase error to accumulate - Reset phase error by swallowing a VCO cycle Achieved by dividing by 5 every 4 reference cycles 19

20 The Issue of Spurious Tones ref(t) PFD e(t) Loop Filter out(t) div(t) N/N+1 frac[k] Accumulator 1-bit carry_out[k] N sd [k] = N + frac[k] PFD error is periodic - Note that actual PFD waveform is series of pulses the sawtooth waveform represents pulse width values over time Periodic error signal creates spurious tones in synthesizer output - Ruins noise performance of synthesizer 20

21 The Phase Interpolation Technique ref(t) PFD e(t) Loop Filter out(t) div(t) α N/N+1 D/A frac[k] M-bit Accumulator M-bit residue[k] 1-bit carry_out[k] Phase error due to fractional technique is predicted by the instantaneous residue of the accumulator - Cancel out phase error based on accumulator residue 21

22 The Problem With Phase Interpolation ref(t) PFD e(t) Loop Filter out(t) div(t) α N/N+1 D/A frac[k] M-bit Accumulator M-bit residue[k] 1-bit carry_out[k] Gain matching between PFD error and scaled D/A output must be extremely precise - Any mismatch will lead to spurious tones at PLL output 22

23 Is There a Better Way?

24 A Better Dithering Method: Sigma-Delta Modulation Time Domain M-bit Input Digital Σ Δ Modulator 1-bit D/A Analog Output Digital Input Spectrum Quantization Noise Frequency Domain Analog Output Spectrum Input Σ Δ Sigma-Delta dithers in a manner such that resulting quantization noise is shaped to high frequencies 24

25 Linearized Model of Sigma-Delta Modulator r[k] S r (e j2πft )= NTF z=e j2πft STF q[k] x[k] y[k] x[k] y[k] H Σ Δ s (z) z=e j2πft H n (z) S q (e j2πft )= H n (e j2πft ) Composed of two transfer functions relating input and noise to output - Signal transfer function (STF) Filters input (generally undesirable) - Noise transfer function (NTF) Filters (i.e., shapes) noise that is assumed to be white 25

26 Example: Cutler Sigma-Delta Topology x[k] u[k] y[k] H(z) - 1 e[k] Output is quantized in a multi-level fashion Error signal, e[k], represents the quantization error Filtered version of quantization error is fed back to input - H(z) is typically a highpass filter whose first tap value is 1 i.e., H(z) = 1 + a 1 z -1 + a 2 z -2 L - H(z) 1 therefore has a first tap value of 0 Feedback needs to have delay to be realizable 26

27 Linearized Model of Cutler Topology x[k] u[k] y[k] x[k] u[k] r[k] y[k] H(z) - 1 e[k] H(z) - 1 e[k] Represent quantizer block as a summing junction in which r[k] represents quantization error - Note: It is assumed that r[k] has statistics similar to white noise - This is a key assumption for modeling often not true! 27

28 Calculation of Signal and Noise Transfer Functions x[k] u[k] y[k] x[k] u[k] r[k] y[k] H(z) - 1 e[k] H(z) - 1 e[k] Calculate using Z-transform of signals in linearized model - NTF: H n (z) = H(z) - STF: H s (z) = 1 28

29 A Common Choice for H(z) 8 7 m = 3 6 Magnitude m = 2 m = Frequency (Hz) 1/(2T) 29

30 Example: First Order Sigma-Delta Modulator Choose NTF to be x[k] u[k] y[k] H(z) - 1 e[k] Plot of output in time and frequency domains with input of 1 Amplitude Magnitude (db) 0 0 Sample Number Frequency (Hz) 1/(2T) 30

31 Example: Second Order Sigma-Delta Modulator Choose NTF to be x[k] u[k] y[k] H(z) - 1 e[k] Plot of output in time and frequency domains with input of 2 Amplitude 1 0 Magnitude (db) -1 0 Sample Number Frequency (Hz) 1/(2T) 31

32 Example: Third Order Sigma-Delta Modulator Choose NTF to be x[k] u[k] y[k] H(z) - 1 e[k] Plot of output in time and frequency domains with input of 4 3 Amplitude Magnitude (db) Sample Number Frequency (Hz) 1/(2T) 32

33 Observations Low order Sigma-Delta modulators do not appear to produce shaped noise very well - Reason: low order feedback does not properly scramble relationship between input and quantization noise Quantization noise, r[k], fails to be white Higher order Sigma-Delta modulators provide much better noise shaping with fewer spurs - Reason: higher order feedback filter provides a much more complex interaction between input and quantization noise 33

34 Warning: Higher Order Modulators May Still Have Tones Quantization noise, r[k], is best whitened when a sufficiently exciting input is applied to the modulator - Varying input and high order helps to scramble interaction between input and quantization noise Worst input for tone generation are DC signals that are rational with a low valued denominator - Examples (third order modulator): x[k] = 0.1 x[k] = /1024 Magnitude (db) Magnitude (db) 0 Frequency (Hz) 1/(2T) 0 Frequency (Hz) 1/(2T) 34

35 Fractional Spurs Can Be Theoretically Eliminated See: - M. Kozak, I. Kale, Rigorous Analysis of Delta-Sigma Modulators for Fractional-N PLL Frequency Synthesis, IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol. 51, no. 6, pp , June S. Pamarti, I. Galton, "LSB Dithering in MASH Delta Sigma D/A Converters", IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 54, no. 4, pp , April

36 Cascaded Sigma-Delta Modulator Topologies x[k] ΣΔM 1 [k] q 1 [k] ΣΔM 2 [k] q 2 [k] ΣΔM 3 [k] M 1 1 y 1 [k] y 2 [k] y 3 [k] Digital Cancellation Logic y[k] Multibit output Achieve higher order shaping by cascading low order sections and properly combining their outputs Advantage over single loop approach - Allows pipelining to be applied to implementation High speed or low power applications benefit Disadvantages - Relies on precise matching requirements when combining outputs (not a problem for digital implementations) - Requires multi-bit quantizer (single loop does not) 36

37 MASH topology x[k] ΣΔM 1 [k] r 1 [k] ΣΔM 2 [k] r 2 [k] ΣΔM 3 [k] M 1 1 y 1 [k] y 2 [k] y 3 [k] 1-z -1 (1-z -1 ) 2 u[k] y[k] Cascade first order sections Combine their outputs after they have passed through digital differentiators 37

38 Calculation of STF and NTF for MASH topology (Step 1) x[k] ΣΔM 1 [k] r 1 [k] ΣΔM 2 [k] r 2 [k] ΣΔM 3 [k] M 1 1 y 1 [k] y 2 [k] y 3 [k] 1-z -1 (1-z -1 ) 2 u[k] y[k] Individual output signals of each first order modulator Addition of filtered outputs 38

39 Calculation of STF and NTF for MASH topology (Step 1) x[k] ΣΔM 1 [k] r 1 [k] ΣΔM 2 [k] r 2 [k] ΣΔM 3 [k] M 1 1 y 1 [k] y 2 [k] y 3 [k] 1-z -1 (1-z -1 ) 2 u[k] y[k] Overall modulator behavior - STF: H s (z) = 1 - NTF: H n (z) = (1 z -1 ) 3 39

40 Sigma-Delta Frequency Synthesizers F ref F out = M.F F ref ref(t) div(t) N sd [m] PFD e(t) Σ Δ Modulator Charge Pump N[m] Divider Loop Filter M+1 M Σ Δ Quantization Noise Use Sigma-Delta modulator rather than accumulator to perform dithering operation - Achieves much better spurious performance than classical fractional-n approach v(t) VCO f out(t) Riley et. al., JSSC, May

41 Background: The Need for A Better PLL Model PFD-referred Noise S En (f) VCO-referred Noise S Φvn (f) -20 db/dec 0 e n (t) 1/T f 0 Φ vn (t) f Φ ref [k] Φ div [k] α π PFD e(t) I cp Charge Pump Divider 1 N H(f) Loop Filter v(t) K V jf VCO Φ out (t) Classical PLL model - Predicts impact of PFD and VCO referred noise sources - Does not allow straightforward modeling of impact due to divide value variations N[k] This is a problem when using fractional-n approach 41

42 A PLL Model Accommodating Divide Value Variations PFD-referred Noise S En (f) VCO-referred Noise S Φvn (f) -20 db/dec Φ ref [k] PFD Tristate: α=1 XOR: α=2 α T 2π 0 e n (t) 1/T e(t) f C.P. I cp Loop Filter H(f) v(t) VCO K V jf 0 Φ vn (t) f Φ out (t) Φ div [k] 1 N nom Φ d [k] Divider 1 T n[k] 2π z-1 z=e j2πft 1 - z-1 See derivation in Perrott et. al., A Modeling Approach for Sigma-Delta Fractional-N Frequency Synthesizers, JSSC, Aug

43 Parameterized Version of New Model Noise Φ jit [k] e spur (t) α T π PFD-referred Noise S En (f) 0 e n (t) 1/T f VCO-referred Noise S Φvn (f) -20 db/dec 0 Φ vn (t) f Ι cpn (t) 1 Ι f o π α Nnom G(f) f o 1-G(f) Φ npfd (t) Φ nvco (t) Divide value variation n[k] n[k] 2π z z -1 G(f) Φ d (t) z=e j2πft F c (t) T G(f) f o Alternate Representation f o 1 jf Φ c (t) Φ c (t) Φ n (t) Φ out (t) D/A and Filter Freq. Phase 43

44 Spectral Density Calculations case (a): CT CT x(t) H(f) y(t) case (b): DT DT x[k] H(e j2πft ) y[k] case (c): DT CT x[k] H(f) y(t) Case (a): Case (b): Case (c): 44

45 Example: Calculate Impact of Ref/Divider Jitter (Step 1) Div(t) S Φjit (e j2πft ) T t (Δt jit ) rms = β sec. π T 2 β 2 0 f Δt jit [k] π T Φ jit [k] Assume jitter is white - i.e., each jitter value independent of values at other time instants Calculate spectra for discrete-time input and output - Apply case (b) calculation 45

46 Example: Calculate Impact of Ref/Divider Jitter (Step 2) Div(t) S Φjit (e j2πft ) S Φn (f) T t (Δt jit ) rms = β sec. π T 2 β 2 0 f 2 1 TN π T nom T 2 β2 0 f o f Δt jit [k] π T Φ jit [k] Φ jit [k] TN nom G(f) Φ n (t) f o Compute impact on output phase noise of synthesizer - We now apply case (c) calculation - Note that G(f) = 1 at DC 46

47 Now Consider Impact of Divide Value Variations Noise Φ jit [k] e spur (t) α T π PFD-referred Noise S En (f) 0 e n (t) 1/T f VCO-referred Noise S Φvn (f) -20 db/dec 0 Φ vn (t) f Ι cpn (t) 1 Ι f o π α Nnom G(f) f o 1-G(f) Φ npfd (t) Φ nvco (t) Divide value variation n[k] n[k] 2π z z -1 G(f) Φ d (t) z=e j2πft F c (t) T G(f) f o Alternate Representation f o 1 jf Φ c (t) Φ c (t) Φ n (t) Φ out (t) D/A and Filter Freq. Phase 47

48 Divider Impact For Classical Vs Fractional-N Approaches Classical Synthesizer 1 1/T n(t) 1 T n[k] G(f) f o F out (t) D/A and Filter Fractional-N Synthesizer 1 1/T n sd (t) 1 T n sd [k] Dithering Modulator n[k] G(f) f o D/A and Filter F out (t) Note: 1/T block represents sampler (to go from CT to DT) 48

49 Focus on Sigma-Delta Frequency Synthesizer n[k] F out (t) n sd [k] 1 1/T n sd (t) 1 T n sd [k] Σ Δ n[k] G(f) f o F out (t) freq=1/t D/A and Filter Divide value can take on fractional values - Virtually arbitrary resolution is possible PLL dynamics act like lowpass filter to remove much of the quantization noise 49

50 Quantifying the Quantization Noise Impact PFD-referred Noise S En (f) VCO-referred Noise S Φvn (f) -20 db/dec n sd [k] S r (e j2πft )= 1 12 NTF STF H s (z) r[k] Σ Δ H n (z) q[k] n[k] z=e j2πft Σ Δ Quantization Noise S q (e j2πft ) 0 2π z z -1 f Φ n [k] z=e j2πft 0 E n (t) f o Φ vn (t) T G(f) Φ tn,pll (t) Φ div (t) Φ out (t) f o 1/T f π α Nnom G(f) 0 f o f 1-G(f) Calculate by simply attaching Sigma-Delta model - We see that quantization noise is integrated and then lowpass filtered before impacting PLL output 50

51 A Well Designed Sigma-Delta Synthesizer -60 f o = 84 khz Spectral Density (dbc/hz) PFD-referred noise S Φout,En (f) Σ Δ noise S Φout,ΔΣ (f) VCO-referred noise S Φout,vn (f) khz 100 khz 1 MHz 10 MHz Frequency f 0 1/T Order of G(f) is set to equal to the Sigma-Delta order - Sigma-Delta noise falls at -20 db/dec above G(f) bandwidth Bandwidth of G(f) is set low enough such that synthesizer noise is dominated by intrinsic PFD and VCO noise 51

52 Impact of Increased PLL Bandwidth f o = 84 khz f o = 160 khz Spectral Density (dbc/hz) PFD-referred noise S Φout,En (f) Σ Δ noise S Φout,ΔΣ (f) VCO-referred noise S Φout,vn (f) Spectral Density (dbc/hz) PFD-referred noise S Φout,En (f) VCO-referred noise S Φout,vn (f) Σ Δ noise S Φout,ΔΣ (f) khz 100 khz 1 MHz 10 MHz Frequency f 0 1/T khz 100 khz 1 MHz 10 MHz f Frequency 0 1/T Allows more PFD noise to pass through Allows more Sigma-Delta noise to pass through Increases suppression of VCO noise 52

53 Impact of Increased Sigma-Delta Order m = 2 m = 3 Spectral Density (dbc/hz) PFD-referred noise S Φout,En (f) Σ Δ noise S Φout,ΔΣ (f) VCO-referred noise S Φout,vn (f) khz 100 khz 1 MHz 10 MHz Frequency f 0 1/T Spectral Density (dbc/hz) PFD-referred noise S Φout,En (f) Σ Δ noise S Φout,ΔΣ (f) VCO-referred noise S Φout,vn (f) khz 100 khz 1 MHz 10 MHz f Frequency 0 1/T PFD and VCO noise unaffected Sigma-Delta noise no longer attenuated by G(f) such that a -20 db/dec slope is achieved above its bandwidth 53

54 Summary of Advanced Analog Synthesizers Integer-N synthesizers have limited resolution for a given PLL bandwidth Advanced synthesizers improve the achievable resolution for a given bandwidth - Dual-loop synthesizers leverage two synthesizers and an I/Q mixer - Direct digital synthesizers use a lookup table and digital logic - Fractional-N synthesizers leverage Sigma-Delta modulation Simpler structure than the other approaches Primary issue is introduction of Sigma-Delta quantization noise 54

55 Clock And Data Recovery

56 High Speed Data Links From Broadband Transmitter PC board trace Z o Package Interface Z in Amp In Clock and Data Recovery Data Clk Data Out Data In Phase Detector Loop Filter Clk Out VCO A challenging component is the clock and data recovery circuit (CDR) - Two primary functions Extract the clock corresponding to the input data signal Resample the input data 56

57 Outline of Talk Clock and Data Recovery circuits - Jitter specifications - Phase detection - Modeling - Data dependent jitter - Bang-bang systems Delay locked loops - Implementation - The issue of infinite delay 57

58 PLL Based Clock and Data Recovery retimed data(t) data(t) PD e(t) Charge Pump Loop Filter v(t) clk(t) VCO Use a phase locked loop to tune the frequency and phase of a VCO to match that of the input data Performance issues - Jitter - Acquisition time - Bit error rate (at given input levels) Let s focus on specifications for OC i.e., 10 Gbit/s SONET 58

59 Jitter Generation retimed data(t) data(t) PD e(t) Charge Pump Loop Filter v(t) clk(t) VCO Definition - The amount of jitter at the output of the CDR when no jitter (i.e., negligible jitter) is present on the data input SONET requires - < 10 mui rms jitter - < 100 mui peak-to-peak jitter Note: UI is unit interval, and is defined as the period of the clk signal (i.e., 100 ps for 10 Gbit/s data rates) 59

60 Jitter Tolerance retimed data(t) data(t) PD e(t) Charge Pump Loop Filter v(t) clk(t) VCO Definition - The maximum amount of jitter allowed on the input while still achieving low bit error rates (< 10e-12) SONET specifies jitter tolerance according to the frequency of the jitter - Low frequency jitter can be large since it is tracked by PLL - High frequency jitter (above the PLL bandwidth) cannot be as high (PLL can t track it out) Limited by setup and hold times of PD retiming register 60

61 Example Jitter Tolerance Mask OC -192 Jitter Tolerance Mask Jitter Tolerance U.I. 15 UI 1.5 UI Acceptable Region 0.15 UI 2.4 khz 24 khz 400 khz 4 MHz 100 MHz Jitter Frequency (Hz) CDR tested for tolerance compliance by adding sine wave jitter at various frequencies (with amplitude greater than mask) to the data input and observing bit error rate 61

62 Jitter Transfer retimed data(t) data(t) PD e(t) Charge Pump Loop Filter v(t) clk(t) VCO Definition - The amount of jitter attenuation that the CDR provides from input to output SONET specifies jitter transfer by placing limits on its transfer function behavior from input to output - Peaking behavior: low frequency portion of CDR transfer function must be less than 0.1 db - Attenuation behavior: high frequency portion of CDR transfer function must not exceed a mask limit 62

63 Example Jitter Transfer Mask OC-192 Jitter Transfer Mask Maximum Allowed "Peaking" = 0.1 db Magnitude (db) Acceptable Region khz 100 khz 1 MHz 8 MHz 100 MHz Frequency (Hz) CDR tested for compliance by adding sine wave jitter at various frequencies and observing the resulting jitter at the CDR output 63

64 Summary of CDR Performance Specifications Jitter - Jitter generation - Jitter tolerance - Jitter transfer (and peaking) Acquisition time - Must be less than 10 ms for many SONET systems Bit error rates - Must be less than 1e-12 for many SONET systems 64

65 Phase Detectors in Clock and Data Recovery Circuits retimed data(t) data(t) PD e(t) Charge Pump Loop Filter v(t) clk(t) VCO Key issue - Must accommodate missing transition edges in input data sequence Two styles of detection - Linear PLL can analyzed in a similar manner as frequency synthesizers - Nonlinear PLL operates as a bang-bang control system (hard to rigorously analyze in many cases) 65

66 Popular CDR Phase Detectors Hogge Detector (Linear) e(t) Bang-Bang Detector (Nonlinear) retimed Reg Reg data(t) data(t) D Q D Q clk(t) e(t) data(t) Reg Latch D Q D Q retimed data(t) Reg Latch D Q D Q clk(t) clk(t) Linear - Hogge detector produces an error signal that is proportional to the instantaneous phase error Nonlinear - Alexander (Bang-bang) detector produces an error signal that corresponds to the sign of the instantaneous phase error 66

67 A Closer Look at the Hogge Detector data(t) clk(t) Hogge Detector (Linear) B Reg A C Latch D Q D Q e(t) retimed data(t) data(t) clk(t) A(t) retimed data(t) B(t) C(t) 1 e(t) 0-1 Error output, e(t), consists of two pulses with opposite polarity - Positive polarity pulse has an area that is proportional to the phase error between the data and clk - Negative polarity pulse has a fixed area corresponding to half of the clk period - Overall area is zero when data edge is aligned to falling clk edge 67

68 Example CDR Settling Characteristic with Hogge PD 0.6 Instantaneous Phase Error vs Time for CDR 1 (Hogge Detector) (Steady-State RMS Jitter = mui) Instantaneous Phase Error (UI) CDR tracks out phase error with an exponential transition response Jitter occuring at steady state is due to VCO and non-idealities of phase detector 68

69 Modeling of CDR with Hogge Detector Hogge Detector Φ data (t) Phase Sampler α 1 π Charge Pump e(t) i(t) I cp Loop Filter H(s) v(t) VCO 2π K v s Φ out (t) α = transition density 0 < α < 1, = 1/2 for PRBS input Similar to frequency synthesizer model except - No divider - Phase detector gain depends on the transition density of the input data The issue of transition density - Phase error information of the input data signal is only seen when it transitions VCO can wander in the absence of transitions - Open loop gain (and therefore the closed loop bandwidth) is decreased at low transition densities 69

70 A Common Loop Filter Implementation Φ data (t) Hogge Detector Phase Sampler Charge Pump Loop Filter VCO 1 e(t) i(t) v(t) Φ α K out (t) 2π v π I cp H(s) s α = transition density 0 < α < 1, = 1/2 for PRBS input i(t) v(t) R 1 C 1 C 2 C = C 1C 2 C 1 +C 2 H(s) = 1 s(c 1 +C 2 ) 1+sR 1 C 2 1+sR 1 C = 1+s/w z sc tot (1+s/w p ) Use a lead/lag filter to implement a type II loop - Integrator in H(s) forces the steady-state phase error to zero (important to minimize jitter) 70

71 Open Loop Response and Closed Loop Pole/Zeros Open loop gain increased 20log A(f) Evaluation of Phase Margin C Closed Loop Pole Locations of G(f) Im{s} B Dominant pole pair 0 db 120 o -140 o angle(a(f)) f z f p C B A f PM = 54 o for B PM = 53 o for A PM = 55 o for C Non-dominant pole A B C A A Re{s} o B -180 o C Key issue: an undesired pole/zero pair occurs due to stabilizing zero in the lead/lag filter 71

72 Corresponding Closed Loop Frequency Response G(w) Peaking caused by undesired pole/zero pair w cp w z 1 0 w z w o Frequency (rad/s) w Undesired pole/zero pair causes peaking in the closed loop frequency response SONET demands that peaking must be less than 0.1 db - For classical lead/lag filter approach, this must be achieved by having a very low-valued zero Requires a large loop filter capacitor 72

73 An Interesting Observation X(s) N A (s) D A (s) Y(s) N B (s) D B (s) Calculation of closed loop transfer function Key observation - Zeros in feedback loop do not appear as zeros in the overall closed loop transfer function! 73

74 Method of Achieving Zero Peaking retimed data(t) data(t) PD e(t) Charge Pump Loop Filter v(t) clk(t) VCO Adjustable Delay Element We can implement a stabilizing zero in the PLL feedback path by using a variable delay element - Loop filter can now be implemented as a simple integrator Issue: delay must support a large range See T.H. Lee and J.F. Bulzacchelli, A 155-MHz Clock Recovery Delay- and Phase-Locked Loop, JSSC, Dec

75 Model of CDR with Delay Element Φ data (t) Hogge Detector Phase Sampler VCO 1 e(t) i(t) v(t) Φ α K out (t) 2π v π I cp H(s) α = transition density 0 < α < 1, = 1/2 for PRBS input Charge Pump Loop Filter K d s Note: K v units are Hz/V Note: K d units are radians/v Delay gain, K d, is set by delay implementation Note that H(s) can be implemented as a simple capacitor - H(s) = 1/(sC) 75

76 Derivation of Zero Produced by Delay Element Φ data (t) Hogge Detector Phase Sampler VCO 1 e(t) i(t) v(t) Φ α K out (t) 2π v π I cp H(s) α = transition density 0 < α < 1, = 1/2 for PRBS input Charge Pump Loop Filter K d s Note: K v units are Hz/V Note: K d units are radians/v i(t) Loop Filter H(s) v(t) VCO 2π K v s Φ out (t) i(t) Loop Filter H(s) v(t) VCO 2π K v s Φ out (t) s 2πK v K d K d K v s 1+ 2π Zero set by ratio of delay gain to VCO gain 76

77 Alternate Implementation retimed data(t) data(t) PD e(t) Charge Pump Loop Filter v(t) clk(t) Adjustable Delay Element VCO -1 Can delay data rather than clk - Same analysis as before 77

78 The Issue of Data Dependent Jitter retimed data(t) Φ clk (t) data(t) PD e(t) Charge Pump Loop Filter v(t) clk(t) VCO For classical or Bulzacchelli CDR - Type II PLL dynamics are employed so that steady state phase detector error is zero Issue: phase detector output influences VCO phase through a double integrator operation - The classical Hogge detector ends up creating data dependent jitter at the VCO output 78

79 Culprit Behind Data Dependent Jitter for Hogge PD Hogge Detector (Linear) e(t) B C data(t) clk(t) A(t) retimed data(t) B(t) C(t) data(t) A Reg Latch D Q D Q retimed data(t) e(t) clk(t) e(t) 0 The double integral of the e(t) pulse sequence is nonzero (i.e., has DC content) - Since the data transition activity is random, a low frequency noise source is created Low frequency noise not attenuated by PLL dynamics 79

80 One Possible Fix Hogge Detector (Linear) e(t) data(t) clk(t) A(t) B 2 C D retimed data(t) B(t) C(t) data(t) clk(t) Reg D Q A Latch D Q Latch D Q retimed data(t) D(t) 1 e(t) 0-2 e(t) 0 Modify Hogge so that the double integral of the e(t) pulse sequence is zero - Low frequency noise is now removed See L. Devito et. al., A 52 MHz and 155 MHz Clockrecovery PLL, ISSCC, Feb,

81 A Closer Look at the Bang-Bang Detector data(t) clk(t) clk(t) Bang-Bang Detector (Nonlinear) Reg D Q D Q Reg A Reg Latch D Q D Q B retimed data(t) C e(t) D data(t) clk(t) A(t) retimed data(t) B(t) C(t) D(t) 1 e(t) 0-1 Error output consists of pulses of fixed area that are either positive or negative depending on phase error Pulses occur at data edges - Data edges detected when sampled data sequence is different than its previous value Above example illustrates the impact of having the data edge lagging the clock edge 81

82 A Closer Look at the Bang-Bang Detector (continued) data(t) clk(t) clk(t) Bang-Bang Detector (Nonlinear) Reg D Q D Q Reg A Reg Latch D Q D Q B retimed data(t) C e(t) D data(t) clk(t) A(t) retimed data(t) B(t) C(t) D(t) 1 e(t) 0-1 Above example illustrates the impact of having the data edge leading the clk edge - Error pulses have opposite sign from lagging edge case 82

83 Example CDR Settling Characteristic with Bang-Bang PD 0.05 Instantaneous Phase Error vs Time for CDR 2 (Bang-Bang Detector) (Steady-State RMS Jitter = mui) Instantaneous Phase Error (UI) Time (Micro Seconds) Bang-bang CDR response is slew rate limited - Much faster than linear CDR, in general Steady-state jitter often dominated by bang-bang behavior (jitter set by error step size and limit cycles)

84 The Issue of Limit Cycles Bang-Bang Style Phase Detector Φ clk (t) data(t) Sense e(t) Drive v(t) clk(t) VCO v(t) Φ clk (t) e(t) Bang-bang loops exhibit limit cycles during steadystate operation - Above diagram shows resulting waveforms when data transitions on every cycle - Signal patterns more complicated for data that randomly transitions For lowest jitter: want to minimize period of limit cycles 84

85 The Impact of Delays in a Bang-Bang Loop Bang-Bang Style Phase Detector Φ clk (t) data(t) Sense e(t) Delay Drive v(t) clk(t) VCO v(t) Φ clk (t) e(t) v(t) Φ clk (t) e(t) Delays increase the period of limit cycles, thereby increasing jitter 85

86 Practical Implementation Issues for Bang-Bang Loops Minimize limit cycle periods - Use phase detector with minimal delay to error output - Implement a high bandwidth feedforward path in loop filter One possibility is to realize feedforward path in VCO See B. Lai and R.C Walker, A Monolithic 622 Mb/s Clock Extraction Data Retiming Circuit, ISSCC, Feb 1991 Avoid dead zones in phase detector - Cause VCO phase to wonder within the dead zone, thereby increasing jitter Use simulation to examine system behavior - Nonlinear dynamics can be non-intuitive - For first order analysis, see R.C. Walter et. al., A Two- Chip 1.5-GBd Serial Link Interface, JSSC, Dec

87 Recall the CDR Model (Hogge Det.) From Lecture 21 Hogge Detector Φ data (t) Phase Sampler α 1 π Charge Pump e(t) i(t) I cp Loop Filter H(s) v(t) VCO 2π K v s Φ out (t) α = transition density 0 < α < 1, = 1/2 for PRBS input Similar to frequency synthesizer model except - No divider - Phase detector gain depends on the transition density of the input data 87

88 Key Observation: Must Use a Type II Implementation Φ data (t) Hogge Detector Phase Sampler Charge Pump Loop Filter VCO 1 e(t) i(t) v(t) Φ α K out (t) 2π v π I cp H(s) s α = transition density 0 < α < 1, = 1/2 for PRBS input i(t) v(t) R 1 C 1 C 2 C = C 1C 2 C 1 +C 2 H(s) = 1 s(c 1 +C 2 ) 1+sR 1 C 2 1+sR 1 C = 1+s/w z sc tot (1+s/w p ) Integrator in H(s) forces the steady-state phase error to zero - Important to achieve aligned clock and to minimize jitter 88

89 Issue: Type II System Harder to Design than Type I Open loop gain increased 20log A(f) Evaluation of Phase Margin C Closed Loop Pole Locations of G(f) Im{s} B Dominant pole pair 0 db 120 o -140 o angle(a(f)) f z f p C B A f PM = 54 o for B PM = 53 o for A PM = 55 o for C Non-dominant pole A B C A A Re{s} o B -180 o C A stabilizing zero is required Undesired closed loop pole/zero doublet causes peaking 89

90 Delay Locked Loops Hogge Detector Φ data (t) Phase Sampler α 1 π Charge Pump e(t) i(t) I cp Loop Filter H(s) v(t) VCO 2π K v s Φ out (t) α = transition density 0 < α < 1, = 1/2 for PRBS input Φ data (t) Hogge Detector Phase Sampler Charge Pump Loop Filter Voltage-Controlled Delay Element 1 e(t) i(t) v(t) Φ out (t) α 2πK π I cp H(s) v α = transition density 0 < α < 1, = 1/2 for PRBS input Delay element used in place of a VCO - No integration from voltage input to phase output - System is Type 1 90

91 System Design Is Easier Than For CDR Open loop gain increased 0 db -90 o -165 o -180 o 20log A(f) \A(f) Evaluation of Phase Margin f p f p2 f p3 C B A f PM = 72 o for A PM = 51 o for B PM = -12 o for C Closed Loop Pole Locations of G(f) Non-dominant poles Dominant pole pair A A B B Im(s) 0 C Re(s) -240 o -315 o No stabilizing zero required - No peaking in closed loop frequency response C 91

92 Example Delay-Locked Loop Implementation Clock and Data arrive misaligned in phase data(t) Adjustable Delay Element clk(t) PD e(t) Charge Pump Loop Filter retimed data(t) v(t) adjusted clk(t) Clock and Data are now re-aligned in phase Assume an input clock is provided that is perfectly matched in frequency to data sequence - However, phase must be adjusted to compensate for propagation delays between clock and data on the PC board A variable delay element is used to lock phase to appropriate value - Phase detector can be similar to that used in a CDR Hogge, Bang-Bang, or other structures possible 92

93 The Catch Clock and Data arrive misaligned in phase data(t) Adjustable Delay Element clk(t) PD e(t) Charge Pump Loop Filter retimed data(t) v(t) adjusted clk(t) Clock and Data are now re-aligned in phase Delay needs to support an infinite range if system to be operated continuously - Can otherwise end up at the end of range of delay element Won t be able to accommodate temperature variations Methods have been developed to achieve infinite range delay elements - Efficient implementation of such delay elements is often the key issue for high performance designs 93

94 The Myth Clock and Data arrive misaligned in phase data(t) Adjustable Delay Element clk(t) PD e(t) Charge Pump Loop Filter retimed data(t) v(t) adjusted clk(t) Clock and Data are now re-aligned in phase Delay locked loop designers always point to jitter accumulation problem of phase locked loops - Implication is that delay locked loops can achieve much lower jitter than clock and data recovery circuits The reality: phase locked loops can actually achieve lower jitter than delay locked loops - PLL s can clean up high frequency jitter of input clock - Whether a PLL or DLL is better depends on application (and achievable VCO performance) 94

95 One Method of Achieving Infinite Delay cos(2πf in t+φ) = cos(2πf in t)cos(φ) - sin(2πf in t)sin(φ) Q cos(2πf in t+φ) φ cos(2πf in t) I Phase shift of a sine wave can be implemented with I/Q modulation Note: infinite delay range allows DLL to be used to adjust frequency as well as phase - Phase adjustment now must vary continuously - Hard to get low jitter in practical implementations 95

96 Conceptual Implementation of Infinite Delay Range cos(2πf in t+φ) = cos(2πf in t)cos(φ) - sin(2πf in t)sin(φ) Q cos(2πf in t) i in (t) cos(2πf in t+φ) φ φ cos(φ) cos(2πf in t+φ) cos(2πf in t) I 90 o sin(φ) q in (t) φ cos(2πf in t) cos(2πf in t+φ) Practical designs often implement cos(φ) and sin(φ) signals as phase shifted triangle waves 96

97 Some References on CDR s and Delay-Locked Loops Tom Lee et. al. were pioneers of the previous infinite range DLL approach - See T. Lee et. al., A 2.5 V CMOS Delay-Locked Loop for an 18 Mbit, 500 Megabyte/s DRAM, JSSC, Dec 1994 Check out papers from Mark Horowitz s group at Stanford - Oversampling data recovery approach See C-K K. Yang et. al., A 0.5-um CMOS 4.0-Gbit/s Serial Link Transceiver with Data Recovery using Oversampling, JSSC, May Multi-level signaling See Ramin Farjad-Rad et. al., A 0.3-um CMOS 8-Gb/s 4- PAM Serial Link Transceiver, JSSC, May Bi-directional signaling See E. Yeung, A 2.4 Gb/s/pin simultaneous bidirectional parallel link, JSSC, Nov

98 Summary Clock and data recovery circuits generate a clock that is phase and frequency aligned to an incoming data signal - Jitter characteristics are one of the key performance metrics - Implementations are either linear or bang-bang Linear is needed for well-defined jitter transfer function Bang-bang has simpler implementation Delay locked loops phase align an existing clock to an incoming data stream - Potentially simpler implementation than CDR 98