74HC Bit Serial Input/Serial or Parallel Output Shift Register with Latched 3 State Outputs. High Performance Silicon Gate CMOS

Transcription

1 8 Bit Serial Input/Serial or Parallel Output Shift Register with Latched 3 State Outputs High Performance Silicon Gate CMOS The 74HC595 coists of an 8 bit shift register and an 8 bit D type latch with three state parallel outputs. The shift register accepts serial data and provides a serial output. The shift register also provides parallel data to the 8 bit latch. The shift register and latch have independent clock inputs. This device also has an asynchronous reset for the shift register. The HC595 directly interfaces with the SPI serial data port on CMOS MPUs and MCUs. Features Output Drive Capability: LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating oltage Range: to Low Input Current:.0 A High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A ESD Performance: HBM 2000 ; Machine Model 200 Chip Complexity: 328 FETs or 82 Equivalent Gates Improvements over HC595 Improved Propagation Delays % Lower Quiescent Power Improved Input Noise and Latchup Immunity These are Pb Free Devices SOIC D SUFFIX CASE B TSSOP DT SUFFIX CASE 948F MARKING DIAGRAMS HC 595 ALYW HC595 = Device Code A = Assembly Location L, WL = Wafer Lot Y, YY = Year W, WW = Work Week G or = Pb Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimeio section on page 2 of this data sheet. HC595G AWLYWW Semiconductor Components Industries, LLC, 2007 Publication Order Number: 74HC595/D

2 PIN ASSIGNMENT Q B CC Q C 2 Q A Q D 3 4 A Q E 4 OUTPUT ENABLE Q F 5 2 LATCH CLOCK SERIAL DATA INPUT A 4 SHIFT REGISTER LOGIC DIAGRAM LATCH Q A Q B 2 Q C 3 Q D 4 Q E 5 Q F 6 Q G 7 Q H PARALLEL DATA OUTPUTS Q G Q H GND SHIFT CLOCK RESET SQ H SHIFT CLOCK RESET LATCH CLOCK OUTPUT ENABLE 2 9 SQ H CC = PIN GND = PIN 8 SERIAL DATA OUTPUT ORDERING INFORMATION 74HC595DR2G Device Package Shipping SOIC (Pb Free) 20 Tape & Reel 74HC595DTR2G TSSOP * 20 Tape & Reel For information on tape and reel specificatio, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specificatio Brochure, BRD80/D. *This package is inherently Pb Free. 2

3 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MAXIMUM RATINGS Symbol Parameter alue Unit CC DC Supply oltage (Referenced to GND) 0.5 to in DC Input oltage (Referenced to GND) 0.5 to CC out DC Output oltage (Referenced to GND) 0.5 to CC I in DC Input Current, per Pin ±20 ma I out DC Output Current, per Pin ± ma I CC DC Supply Current, CC and GND Pi ± ma P D Power Dissipation in Still Air, SOIC Package TSSOP Package 0 4 T stg Storage Temperature to + 0 C T L Lead Temperature, mm from Case for Seconds (SOIC or TSSOP Package) 2 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditio is not implied. Extended exposure to stresses above the Recommended Operating Conditio may affect device reliability. Derating SOIC Package: 7 mw/ C from to 25 C TSSOP Package: 6. mw/ C from to 25 C For high frequency or heavy load coideratio, see Chapter 2 of the ON Semiconductor High Speed CMOS Data Book (DL29/D). RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit CC DC Supply oltage (Referenced to GND) in, out DC Input oltage, Output oltage (Referenced to GND) mw C 0 CC T A Operating Temperature, All Package Types C This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. However, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, in and out should be cotrained to the range GND ( in or out ) CC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or CC ). Unused outputs must be left open. t r, t f Input Rise and Fall Time CC = (Figure ) CC = CC =

4 DC ELECTRICAL CHARACTERISTICS (oltages Referenced to GND) Symbol Parameter Test Conditio IH IL OH OL OH OL I in I OZ I CC Minimum High Level Input oltage Maximum Low Level Input oltage Minimum High Level Output oltage, Q A Q H Maximum Low Level Output oltage, Q A Q H Minimum High Level Output oltage, SQ H Maximum Low Level Output oltage, SQ H Maximum Input Leakage Current Maximum Three State Leakage Current, Q A Q H Maximum Quiescent Supply Current (per Package) out = or CC out = or CC II out I 20 A II out I 20 A I out ma I out 7.8 ma I out ma I out 7.8 ma II out I 4.0 ma II out I 5.2 ma II out I 4.0 ma II out I 5.2 ma CC () Guaranteed Limit 55 to 25 C 85 C 25 C in = CC or GND ± ±.0 ±.0 A Output in High Impedance State in = IL or IH out = CC or GND in = CC or GND l out = 0 A Unit ±0.25 ±2.5 ±2.5 A 4.0 A NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High Speed CMOS Data Book (DL29/D). 4

5 AC ELECTRICAL CHARACTERISTICS (C L = pf, Input t r = t f = ) Symbol f max t PLH, t PHL t PHL t PLH, t PHL t PLZ, t PHZ t PZL, t PZH t TLH, t THL t TLH, t THL Parameter Maximum Clock Frequency (% Duty Cycle) (Figures and 7) Maximum Propagation Delay, Shift Clock to SQ H (Figures and 7) Maximum Propagation Delay, Reset to SQ H (Figures 2 and 7) Maximum Propagation Delay, Latch Clock to Q A Q H (Figures 3 and 7) Maximum Propagation Delay, Output Enable to Q A Q H (Figures 4 and 8) Maximum Propagation Delay, Output Enable to Q A Q H (Figures 4 and 8) Maximum Output Traition Time, Q A Q H (Figures 3 and 7) Maximum Output Traition Time, SQ H (Figures and 7) CC () Guaranteed Limit 55 to 25 C 85 C 25 C C in Maximum Input Capacitance pf C out Maximum Three State Output Capacitance (Output in High Impedance State), Q A Q H pf NOTE: For propagation delays with loads other than pf, and information on typical parametric values, see Chapter 2 of the ON Semiconductor High Speed CMOS Data Book (DL29/D). 25 C, CC = C PD Power Dissipation Capacitance (Per Package)* 0 pf * Used to determine the no load dynamic power coumption: P D = C PD 2 CC f + I CC CC. For load coideratio, see Chapter 2 of the ON Semiconductor High Speed CMOS Data Book (DL29/D) Unit MHz 5

6 TIMING REQUIREMENTS (Input t r = t f = ) Symbol Parameter CC () Guaranteed Limit 25 C to 55 C 85 C 25 C Unit t su Minimum Setup Time, Serial Data Input A to Shift Clock (Figure 5) t su Minimum Setup Time, Shift Clock to Latch Clock (Figure 6) t h Minimum Hold Time, Shift Clock to Serial Data Input A (Figure 5) t rec Minimum Recovery Time, Reset Inactive to Shift Clock (Figure 2) t w Minimum Pulse Width, Reset (Figure 2) t w Minimum Pulse Width, Shift Clock (Figure ) t w Minimum Pulse Width, Latch Clock (Figure 6) t r, t f Maximum Input Rise and Fall Times (Figure )

7 PACKAGE DIMENSIONS SOIC CASE B 05 ISSUE K A 9 8 B P 8 PL 0.25 (0.0) M B S NOTES:. DIMENSIONING AND TOLERANCING PER ANSI YM, CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 5 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 27 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. T SEATING PLANE G D PL K C M R X 45 J F MILLIMETERS INCHES DIM MIN MAX MIN MAX A B C D F G.27 BSC 0.0 BSC J K M P R (0.0) M T B S A S SOLDERING FOOTPRINT* 8X 6. X.2 X PITCH 8 9 DIMENSIONS: MILLIMETERS *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.