Interfacing Piezo Film to Electronics

Transcription

1 BASIC CIRCUIT CONCEPTS A properly designed interace circuit plays a key role in the optimization o piezo ilm sensors. The applications o piezo ilm span rom toys to military sensors and interacing to electronics is highly application dependent. In many cases, piezo ilm can be directly connected to electronic circuits without special interace considerations. However, or those cases where an interace circuit is required, the ollowing 3 steps are recommended: 1. Consider the requency range and signal amplitude requirements over the desired dynamic range. 2. Choose a proper load resistance to assure the low end operating requency and to minimize signal loss due to the loading eect. 3. Select a buer circuit i the signal level is small. I a high value load resistance is needed (such as 22MÙ or higher value), a low leakage high impedance buer ampliier is recommended. JFET's or CMOS operational ampliiers are commercially available or a buer. Simpliied Equivalent Circuits The irst step in an interace circuit design is to understand the piezo ilm characteristics as part o an electrical equivalent circuit. Figure 1 shows a simpliied equivalent circuit o piezo ilm. It consists o a series capacitance with a voltage source. The series capacitance C represents piezo ilm capacitance which is proportional to the ilm permittivity and area and inversely proportional to ilm thickness. The voltage source amplitude is equal to the open circuit voltage o piezo ilm and varies rom microvolts to 100's o volts, depending on the excitation magnitude. This simpliied equivalent circuit is suitable or most applications but is o limited value at very high requencies such as that used in ultrasound transducers. Figure 1. Equivalent circuit o piezo ilm Figure 2 shows an equivalent circuit as a charge generator. This equivalent circuit has ilm capacitance C, and internal ilm resistance R. The induced charge Q is linearly proportional to the applied orce as Figure 2. Equivalent circuit or described earlier. The capacitance C is proportional to the piezo ilm surace area o ilm and is inversely proportional to the ilm thickness. In low requency applications, the internal ilm resistance R is very high and can be ignored. The open circuit output voltage can be ound rom the ilm capacitance; i.e., V=Q/C. Input Resistance The most critical part o an interace circuit is the input Copyright 2006 by Measurement Specialties, Inc. All International Rights Reserved. 1 o 7

2 resistance. The input resistance aects low requency measurement capability as well as signal amplitude. This is called the "loading eect". Piezo ilm capacitance can be regarded as an equivalent source impedance. It is important to note that this source impedance increases with decreasing ilm capacitance and decreasing requency o operation. This source impedance combined with the input resistance produces a voltage divider. As the ratio o input resistance to source impedance is decreased, the overall output voltage is reduced. Thereore, choosing a proper input resistance or the electronic interace is critical in minimizing the loading eect. Time Constant Figure 3. Equivalent circuit o piezo ilm with input resistance o electronic interace Figure 4. Time response o piezo ilm In addition to input resistance, the input capacitance o an interace circuit can also aect the output. Figure 3 shows the equivalent circuit o ilm with input resistance R i and input capacitance C. i A typical time domain response o piezo ilm is shown in Figure 4. The charge developed on the ilm due to an applied orce decays with a time constant which is deined by R(C + C). i i This time constant represents the time required or a signal to decay to 70.7% (-3dB) o its original amplitude. The smaller the time constant, the quicker the signal decays. Because o this inite time constant, piezo ilm is suitable or dynamic measurements rather than static measurement (0.001 Hz minimum). I a long time constant is desired, a high input resistance and ilm capacitance can be used. It should be understood, however, that a high input resistance can also produce higher noise, requiring compensation through shielding, etc. Frequency Response Figure 5. High pass ilter characteristic o piezo ilm Another important aspect o the time constant can be seen in the requency response o the equivalent circuit. The circuit exhibits an RC high-pass ilter characteristic as shown in Figure 5. In this igure, the vertical axis implies the ratio o observable output signal to the developed signal (open circuit voltage o the piezo ilm). Zero db implies no loss o signal. The cuto requency (3 db down) is inversely proportional to the time constant. When a piezo ilm sensor is operated below this cut-o requency, the output signal is signiicantly reduced. For a low requency measurement, an Copyright 2006 by Measurement Specialties, Inc. All International Rights Reserved. 2 o 7

3 input resistance needs to be high enough so that the cut-o requency is well below the desired operating requency. This consequence can be veriied rom consideration o the time constant as well as the loading eect. Figure 6. Frequency response o SDT1 As an example, the requency response o a shielded piezo ilm sensor (model SDT1) is shown in Figure 6. In this example, the SDT is interaced with a circuit which contains a 10MÙ load resistor and an FET. The capacitance o the piezo ilm is 2.4 nf. With 10MÙ load resistance, the time constant becomes 24 msec and thus, the cut-o requency is 6.6 Hz. For comparison, the cut-o requency can be reduced to 0.66 Hz i a 100MÙ resistor is used instead o the 10MÙ resistor. This sensor component can be used or any application operating above the cut-o requency determined by the resistance value. In applications where the electronic circuit cannot be placed near the sensor, a buer circuit is recommended close to the sensor. The buer circuit converts the high output impedance o the piezo ilm element into a low output impedance and thus minimizes the signal loss and noise through the cable. For large size (i.e., high capacitance) piezo ilm sensors a buer may not be required, even with small signals and long cables. When a high piezo ilm output impedance is required, a low-leakage, high impedance buer is necessary. For example, inrared motion sensor and accelerometer applications require up to 50GÙ o input resistance to obtain a very low requency response. For such cases, the input impedance o the buer must be much higher than the output resistance o the piezo ilm in order to maintain the low requency response. In addition, minimum leakage current o the buer is critical in order to maximize the measurement accuracy. Some examples o low leakage buer electronics include: JFET (Siliconix, Sprague); Operational ampliiers LMC660, LF353 (National Semiconductor), OP80 (PMI), and 2201 (Texas Instruments). Figure 7 shows unity gain buer circuit examples or general applications. Operational ampliiers oer a great deal o versatility as both buers and ampliiers. They can be used as either charge-mode or voltage-mode ampliiers. Figure 8 shows basic charge and voltage ampliier conigurations. The Figure 7. Unity gain buer or piezo ilm sensors Copyright 2006 by Measurement Specialties, Inc. All International Rights Reserved. 3 o 7

4 voltage output o the charge ampliier is determined by Q/C. Q is the charge developed on the piezo ilm and C is the eedback capacitance o the charge ampliier. Figure 8. Typical ampliiers or piezo ilm sensors The output voltage o the charge ampliier depends on the eedback capacitance, not the input capacitance. This indicates that the output voltage o a charge ampliier is independent o the cable capacitance. The major advantage o a charge ampliier can be realized when a long cable is used between a piezo ilm sensor and electronics. In addition, it also minimizes charge leakage through the stray capacitance around the sensor. Otherwise, simple voltage ampliiers are suicient or most applications. Included in Figure 7 is a typical non-inverting voltage ampliier. The advantage o a voltage ampliier can be seen when ambient temperature is considered. The voltage sensitivity (g-constant) variation over temperature is smaller than the charge sensitivity (d-constant) variation. Consequently, voltage ampliiers with piezo ilm exhibit less temperature dependence. In Figure 8, the time constants or the charge ampliier and voltage ampliier are determined by RC and RC respectively. As a design example, a traic sensor interace is described. Because o its lexibility, piezo cable is an ideal sensor material or traic measurement applications. MEAS s BL traic sensor is constructed with a piezo cable sheathed in a compressed brass tube, with a variety o signal cable lengths tailored to the installation requirements. The BL is available in sensing lengths o more than 3 meters. In this speciic example, the BL sensor is 2 meters long. This electrically shielded sensor has 100 eet o coax cable. The electrical speciications o this sensor include: Figure 9. An interace circuit o a traic sensor Capacitance = 9.5 nf (including piezo cable and signal cable capacitances) Output = 500mV (or a wheel load o 800 pounds at 55mph and 70 F) Signal : Noise = 10:1 The basic requirements o an interace circuit are: Low end requency = 1.6 Hz Circuit output = Digital pulse count An interace circuit to meet these requirements is shown in Figure 9. This circuit works as a comparator. A 10MÙ input Copyright 2006 by Measurement Specialties, Inc. All International Rights Reserved. 4 o 7

5 resistance is chosen in order to reduce the cut-o requency to about 1 Hz. The actual cut-o requency with this resistor can be calculated as 1.6 Hz. A 10MÙ potentiometer is used to adjust the threshold voltage, V and the diode is included to protect the electronics rom high voltage damage. Typical piezo ilm and interace circuit output signals rom a passenger car at 55 mph are shown in Figure 9. Signal Conditioning Because piezo ilm is both piezoelectric and pyroelectric, some provision must be made to eliminate or at least reduce the eect o unwanted signals. The primary principles o signal conditioning include: Filtering Electrical ilters designed to give the desired band-pass and band-rejection characteristics. Averaging I the desired signal exhibits periodicity, while the undesired signal is random, signal averaging can increase the signal-to-noise ratio. Common Mode Rejection By wiring two equal areas o a piezo ilm electrode out-ophase, unwanted common-mode signals can be made to cancel. Basic Switch Circuitry A variety o circuits are available to electronically interace with piezo ilm including ield eect transistors (FETs), operational ampliiers (Op Amps), and low-current digital logic (CMOS). Figure 10. High requency, low gain FET circuit interace FETs lend themselves to applications o small size since they are readily available in surace mount technology. Important characteristics to consider when using FETs are switching requency, piezo ilm capacitance, leakage current o the FET in the o-state, input bias resistance, and shielding rom electromagnetic intererence (EMI). Figures 10 and 11 show typical FET circuit conigurations or a piezo ilm switch. Figure 10, the common drain or source ollower, applies well in applications where simple buering is important. Here, the circuit voltage gain is approximately one. Figure 11. Low requency, high gain FET circuit interace The common source circuit in Figure 11 is suitable or low requency applications where voltage gain is required. The gain is determined by resistances R D and R S. As the gain increases, requency bandwidth decreases by a actor o one decade per 20 db o gain. Operational ampliiers oer a great deal o versatility or piezo ilm switch applications. Adaptation to a particular application is oten as simple as making a ew wiring Copyright 2006 by Measurement Specialties, Inc. All International Rights Reserved. 5 o 7

6 changes. Important op amp circuit characteristics include input bias resistance, ilm switch capacitance, and EMI shielding. The op amp circuit o Figure 12, a charge ampliier, suits applications where a detected vibration actuates the switch. It also works well in small signal applications. A charge ampliier eliminates the eects o the time constants o both the piezo ilm and connecting cable. The charge ampliier is a current operated circuit with zero input impedance, which results in no voltage being generated across the ilm. The charge ampliier quickly absorbs charges developed by the ilm. With no charge let on its electrodes, the ilm exhibits no time constant. The capacitance o the ilm and connecting cable have no adverse eect on the circuit's transer unction. Thus tolerances on ilm size and cable length need not be exceptionally tight. The charge is transerred rom the ilm to the capacitor in the ampliier's eedback loop, which determines the output voltage: V = Q/C. The charge ampliier requires an op amp having a high input resistance and low bias current. A high input resistance avoids bleed-o o the charge on the eedbackcapacitor, and low bias current prevents the eedback capacitor rom charging and discharging at excessive rates. The layout o the charge ampliier circuit is critical. The op-amp casing must be well grounded and the inputs should be guarded and connected to the same ground as the casing. Figure 12. Op Amp Interace circuit acting as a charge ampliier Figure 13. Layout or guarding inputs Figure 14. Signal level detector A layout with guarded inputs is shown in Figure 13. Also, to prevent leakage noise rom being ampliied by the op-amp, the input cable should be terminated using a well-insulated stand-o connector. Even with the above precautions, it is likely that the output voltage will drit. To compensate or drit, a reset switch is generally designed into the circuit to manually reset the output to zero at intervals. One technique is to place a reed switch in series with a resistor, which is in parallel with the eedback capacitor C. Activating the reed switch closes the switch, discharging the voltage stored in the eedback capacitor. Another method is to use a MOSFET device in which the maximum output voltage and o-gate voltage determine the minimum gate voltage o the FET. In practice, a supply voltage greater than the ampliier voltage is applied to the gate o the MOSFET, thereby lowering its drain/source resistance and creating a current path or discharge o the eedback capacitor. Copyright 2006 by Measurement Specialties, Inc. All International Rights Reserved. 6 o 7

7 The third alternative is to place a bleed resistor across the eedback. This resistor creates a time constant (CR ), which is independent o the ilm capacitance and can be accurately controlled. Figure 15. Dierential Op Amp interace circuit The signal level detector o Figure 14 its applications where large signal-to-noise ratios are desirable. This circuit is perect or detecting an impact among low-level vibrations. For situations where signal to noise ratios are low and where impacts or pressures must be discerned rom background vibration, the dierential ampliier circuit o Figure 15 is appropriate. This circuit consists o two sensors driving a dierential ampliier. This coniguration uses a common-mode rejection concept. The two switches are mechanically coupled to cancel unwanted vibrations that stimulate both. An input or pressure on one switch but not the other, will produce an output. Figure 16. CMOS circuit or detecting a single impact CMOS logic oers a low-cost way to interace with piezo ilm. As mentioned earlier, low-power circuits implemented with CMOS technology are ideally suited to piezo ilm switches. CMOS applications or piezo ilm are generally or low requency operation. Other characteristics to consider include device input leakage current and input impedance, input bias resistance, and the eect o EMI. A CMOS circuit can be used, or example, in applications to sense a single impact or a single pressure. The D-Flip Flop in Figure 16 indicates the presence o either the impact or pressure to set o an audible alarm. The circuit in Figure 17, senses multiple impacts or pressures or counting applications. Figure 17. CMOS interace circuit or counting applications Many dierent CMOS circuit conigurations are possible to interace with piezo ilm. Common to all o them is an input bias resistor in parallel with the piezo ilm, and an input resistor in series with the ilm. The bias resistor handles leakage current and the series resistor limits current to protect against electrostatic discharge. Copyright 2006 by Measurement Specialties, Inc. All International Rights Reserved. 7 o 7