L16: Power Dissipation in Digital Systems. L16: Spring 2006 Introductory Digital Systems Laboratory

Transcription

1 L16: Power Dissipation in Digital Systems 1

2 Problem #1: Power Dissipation/Heat Power (Watts) Pentium proc 18KW 5KW 1.5KW 500W Year Power Density (W/cm) Rocket Nozzle Nuclear Reactor Hot Plate Sun s Surface P6 Pentium proc Year Courtesy Intel (S. Borkar) How do you cool these chips?? heat sink chip

3 Problem #: Energy Consumption The Energy Problem 7.5 cm 3 AA battery Alkaline: ~10,000J What can One Joule of energy do? (Image by MIT OCW. Adapted from Jon Eager, Gates Inc., S. Watanabe, Sony Inc.) Mow your lawn for 1 ms Operate a processor for ~ 7s Send a 1 Megabyte file over 80.11b Image by MIT OCW. No Moore s law for batteries Today: Understand where power goes and ways to manage it

4 Dynamic Energy Dissipation V DD Charging E 0 1 = C L V DD Discharging V DD i DD E cap = 1/C L V DD R P R P IN =0 E diss, RP = 1/C L V DD IN =1 E diss,rn =1/C L V DD R N C L R N C L P = C L V DD f clk 3

5 The Transition Activity Factor α 0 >1 Current Next Output Input Input Transition > > > > > > > > > > > > > > > > 0 A B Assume inputs (A,B) arrive at f and are uniformly distributed What is the average power dissipation? α 0 >1 = 3/16 P = α 0 >1 C L V DD f Z 4

6 Junction (Silicon) Temperature Simple Scenario Silicon T j -T a =R θja P D R θja is the thermal resistance between silicon and Ambient P D Realistic Scenario Silicon Case Sink T J T C T S T A T J R θjc T J T C P D R θja R θcs T S T A R θsa T j =T a + R θja P D T A Make this as low as possible R θca = R θcs +R θsa is minimized by facilitating heat transfer (bolt case to extended metal surface heat sink) 5

7 Intel Pentium 4 Thermal Guidelines Pentium 3.06 GHz dissipates 81.8W! Maximum T C = 69 C R CA < 0.3 C/W for 50 C ambient Typical chips dissipate 0.5-1W (cheap packages without forced air cooling) Image by MIT OpenCourseWare. Image by MIT OpenCourseWare. Adapted from Intel Pentium 4 documentation. 6

8 Power Reduction Strategies P = α 0 >1 C L V DD f Reduce Transition Activity or Switching Events Reduce Capacitance (e.g., keep wires short) Reduce Power Supply Voltage Frequency is typically fixed by the application, though this can be adjusted to control power Optimize at all levels of design hierarchy 7

9 Clock Gating is a Good Idea! Clock gating reduces activity and is the most common low-power technique used today Global Clock Enable_Adder Adder Off Adder Clock + Multiplier On X Enable_Multiplier Multiplier Clock 100 s of different clocks in a microprocessor Clock Gating Reduces Energy, does it reduce Power? 8

10 Does your GHz Processor run at a GHz? Processor Chip Activity Control Thermal Sensor Note that there is a difference between average and peak power On-chip thermal sensor (diode based), measures the silicon temperature If the silicon junction gets too hot (say 15 C), then the activity is reduced (e.g., reduce clock rate or use clock gating) Use of Thermal Feedback 9

11 Power Supply Resonance L board L package R grid Board decap On-die decap Switching currents Can write a Virus to Activate Power Supply Resonance! Image removed due to copyright restrictions. Image removed due to copyright restrictions. Image removed due to copyright restrictions. 10

12 Number Representation: Two s s Complement vs. Sign Magnitude Two s complement Sign-Magnitude Consider a 16 bit bus where inputs toggles between +1 and 1 (i.e., a small noise input) Which representation is more energy efficient? 11

13 Time Sharing is a Bad Idea Time Sharing Increases Switching Activity 1

14 Not just a Issue: Cool Software??? MEMORY address CPU address 16 a[0] a[1] a[] a[3] b[0] b[1] b[] b[3] float a [56], b[56]; float pi= 3.14; for (i = 0; i < 55; i++) { a[i] = sin(pi * i /56); b[i] = cos(pi * i /56); } 51(8) = 4607 bit transitions float a [56], b[56]; float pi= 3.14; for (i = 0; i < 55; i++) {a[i] = sin(pi * i /56);} for (i = 0; i < 55; i++) {b[i] = cos(pi * i /56);} (8)+( ) = 1030 transitions 13

15 Glitching Transitions Chain Topology A B Tree Topology A B C D + C D + + (A+B) + (C+D) (((A+B) + C)+D) Balancing paths reduces glitching transitions Structures such as multipliers have lot of glitching transitions Keeping logic depths short (e.g., pipelining) reduces glitching 14

16 Reduce Supply Voltage : But is it Free? V DD V DD G + V DD - t =0+ K V S ( V DD V T D ) C L IN OUT Delay = C L ΔV i D S = k C L V DD ( V DD DD V T ) ( V DD V V T ) 1 V DD V DD from V to 1V, energy by x4, delay x 15

17 Transistors Are Free (What do you do with a Billion Transistors?) f=1ghz V DD =V IN f = 500Mhz V DD =1V IN IN f = 500Mhz V DD =1V X X X OUT SELECT P serial = C mult f OUT Pparallel = (C mult 1 f /) = P serial /4 Trade Area for Low Power 16

18 Algorithmic Workload Image by MIT OCW. Exploit Time Varying Algorithmic Workload To Vary the Power Supply Voltage 17

19 Dynamic Voltage Scaling (DVS) Fixed Power Supply ACTIVE IDLE Variable Power Supply ACTIVE E FIXED = ½ C V DD 1.0 E VARIABLE = ½ C (V DD /) = E FIXED / 4 Normalized Energy Fixed Supply Variable Supply Normalized Workload [Gutnik97] 18

20 DVS on a Processor Digitally adjustable DC-DC converter powers SA-1110 core 3.6V 5 Energy per Operation Frequency (MHz) Core Voltage (V) 1.6 Controller V out SA-1110 Figure by MIT OpenCourseWare. Adapted from R. Min, T. Furrer, and A. P. Chandrakasan. "Dynamic Voltage Scaling Techniques for Distributed Microsensor Networks." Workshop on VLSI (April 000): Control μos selects appropriate clock frequency based on workload and latency constraints 19 μos

21 Energy Efficiency of Software Processor (StrongARM-1100) FPGA (Xilinx) CLB CLB Average Current (A) CLB CLB 0 ARM Instructions Power (%) Figure by MIT OpenCourseWare. Adapted from A. Sinha, DAC Cache Cpntrol GCLK EBOX I/O,PLL Figure by MIT OpenCourseWare. Adapted from Montanaro 1996, JSSC. Interconnect Software Energy Dissipation has Large Overhead 0 Clock I/O 9% 1% CLB 5% 65% Image by MIT OpenCourseWare. Adapted from Kusse 1998, UCB.

22 Trends: Leakage and Power Gating V DD Switching (computing) E = CV DD C V DD 0 1 E = V DD I V T /S C Leakage (standby) Total Energy/Switching Energy Duty Cycle (%) Low V T devices are leaky - Use a High V T device is used to gate leakage current Sleep 1

23 Trends: Energy Scavenging MEMS Generator Power Harvesting Shoes Image removed due to copyright restrictions. Courtesy of Joe Paradiso (MIT Media Lab). Used with permission. Vibration-to-Electric Conversion ~ 10μW After 3-6 steps, it provides 3 ma for 0.5 sec ~10mW