Size: px
Start display at page:

Download ""

Transcription

1 GateLevelDescriptionofSynchronous ThesisfortheDegreeofDoctorofPhilosophy AutomaticVericationBasedon Hardware TheoremProving and PerBjesse ChalmersUniversityofTechnologyandGoteborgUniversity DepartmentofComputingScience SE-41296Goteborg,Sweden Goteborg,May2001

2 GateLevelDescriptionofSynchronousHardwareand ISBN AutomaticVericationBasedonTheoremProving Nyserienr1702 DoktorsavhandlingarvidChalmersTekniskaHogskola, ISSN x cperbjesse,2001 ComputingScience ChalmersUniversityofTechnologyandGoteborgUniversity SE-41296Goteborg,Sweden PrintedatChalmers,Goteborg,2001

3 PerBjesse ComputingScience ChalmersUniversityofTechnologyandGoteborgUniversity AutomaticVericationBasedonTheoremProving GateLevelDescriptionofSynchronousHardwareand Today'shardwaredevelopmentindustryfacesenormousproblems.Theprimaryreason forthisisthatthecomplexityofstate-of-the-arthardwaredevicesisgrowingfaster thanthecapacityofthetoolsthatareusedtocheckthattheyarecorrect.this Abstract productsarecorrect. developmenttimeasshortaspossible.asaconsequence,componentsunderdesign problematicsituationisfurtheraggravatedbyanincreasingpressuretomakethe Inthisthesis,wecontributetoimprovedhardwaredesignmethodsintwoways. aremorelikelytocontainerrors,whilelesstimecanbespentmakingsurethatnished dedinthefunctionallanguagehaskell.lavausesthecapabilitiesofthehostlanguage toexpresssynchronouscircuitsinamathematicallypreciseway,andallowseasyconnectiontoexternalvericationtools.lavaalsousesthecapabilitiesofhaskellto First,wepresentLava,ahardwaredescriptionandvericationplatformthatisembed- allowthedesignertodeviseinterconnectionpatterns,andtowriteparametrisedcircuitdescriptions.weillustratethepoweroflavabydescribingandverifyinghardware Second,wepresentanumberoftechniquesandcasestudiesthatdemonstratehowautomatictheoremprovingcanbeusedtoprovecorrectnessandndbugsinsynchronous hardware.weshowhowvericationcanbedonebothatthelevelofcomplexarith- componentsforcomputingthefastfouriertransform(fft). logictheoremprovers.theresultingconvertedmethodsareshowntogiveorderof metic,andatthebooleanlevel.inthecaseofthevericationatthearithmeticlevel, magnitudespeedupscomparedtocurrentstate-of-theartvericationtechniques. orderlogictheoremprover.inthecaseofthevericationatthebooleanlevel,we convertanumberofstandardnitestatevericationmethodstousepropositional weuselavatoconstructspecialpurposeproofstrategiesthatinterfacewitharst Keywords:hardwaredescription,hardwareverication,modelchecking,reachabilityanalysis,symbolictrajectoryevaluation,theoremproving,satisability,induction, signalprocessing,functionallanguages.

4

5 Thisthesiscollectstogethervearticlesthatarepublishedoracceptedfor publication,whichappearaschapters2,3,5,6,and7: Lava:HardwareDesigninHaskell,writtentogetherwithKoenClaessen, AutomaticVericationofCombinationalandPipelinedFFTCircuits,publishedin1999[25] MarySheeranandSatnamSingh,publishedin1998[11] SymbolicReachabilityAnalysisBasedonSAT-Solvers,writtentogether SAT-basedVericationwithoutStateSpaceTraversal,writtentogether withkoenclaessen,publishedin2000[10] withparoshazizabdullaandniklaseen,publishedin2000[2] FindingBugsinanAlphaMicroprocessorUsingSatisabilitySolvers, Thethesisalsocontainsatechnicalreport,Chapter4,andajournalpaper writtentogetherwithtimleonardandabdelmokkedem,acceptedfor submittedforpublication,chapter8: publicationin2001[12] SAT-basedModelChecking:ATutorialandOverview,writtenduring2000 SymbolicModelCheckingwithSetsofStatesRepresentedasFormulas, publishedin1999[9] togetherwithmarysheeranandgunnarstalmarck[13] 5

6 morethanoneauthor: Thefollowingoutlinesmyparticipationonthearticlesinthisthesisthathave Lava:HardwareDesigninHaskell,writtentogetherwithClaessen,Sheeran, SymbolicReachabilityAnalysisBasedonSAT-Solvers,writtentogetherwith andsingh:iparticipatedindiscussions,didthefftmodellingandverication,andwrotesection4ofthepaper. AbdullaandEen:Iparticipatedindiscussions,didsomeoftheexperimentalwork,andwroteSections1-3and6-8ofthepaper. SAT-basedVericationwithoutStateSpaceTraversal,writtentogetherwith FindingBugsinanAlphaMicroprocessorUsingSatisabilitySolvers,writtentogetherwithLeonardandMokkedem:Iparticipatedindiscussions, Claessen:Iparticipatedindiscussions,implementedthecorealgorithms, andwrotehalfthepaper. SAT-basedModelChecking:ATutorialandOverview,writtentogetherwith implementedthesat-basedvericationalgorithms,andwrotethewhole exceptionofsection3andsection4.3. Sheeran:Iparticipatedindiscussionsandwrotethewholepaperwiththe paper.

7 Contents 1Introduction 1.1TheHardwareDevelopmentCrisis FormalMethods ABriefHistoryofFormalMethods FormalMethods Whatarethey? AimoftheThesis FormalHardwareVericationMethods Lava:HardwareDesigninHaskell 1.4Synopsis Introduction OverviewoftheSystem Monads TypeClasses Interpretations Combinators PrimitiveDataTypes UsingaSymbolicCircuit SymbolicInterpretation StandardInterpretation AnExample:FFT OtherInterpretations Verication ComplexNumbers...24 i

8 2.4.2DiscreteFourierTransform TwoFFTCircuits Components TheCircuitDescriptionsinLava RelatedWork RunningInterpretations Conclusions RelatedWorkonFFTDescriptionandVerication AutomaticVericationofCombinationalandPipelinedFFT Circuits 2.7FutureWork Introduction TheLavaHardwareDevelopmentPlatform VericationofComponents FFTLow-levelDescriptions TheFastFourierTransforms CombinationalFFTVerication TheoreticalBasisoftheVerications LessonsLearned ManualPreparation PipelinedFFTVerication RelatedWork Conclusions FutureWork SymbolicModelCheckingwithSetsofStatesRepresentedas 3.10Appendix...50 Formulas TheRadix-2FFTdescription Introduction Overview CTLModelChecking Conventions...54 ii

9 4.5RequirementsonaRepresentationforSetsofStates ComputingModelsofCTLFormulas SyntaxandSemantics EncodingsSetsofStatesinPropositionalLogic ModelCheckingusingStalmarck'sMethod FormulaRepresentation EquivalenceChecking FormulaMinimisation Discussion BooleanQuanticationformAX,mEX TheConnectiveOperatorsm#,m: OtherLogics ASimpleUseofFirstOrderLogic QuantiedBooleanFormulas SymbolicReachabilityAnalysisBasedonSAT-Solvers 4.9Conclusions AndMore Introduction Preliminaries Quantication ReachabilityAnalysis Satisability RepresentationofFormulas SAT-basedVericationwithoutStateSpaceTraversal 5.8ConclusionsandFutureWork ExperimentalResults Introduction VanEijk'sMethod Stalmarck'sMethodInsteadofBDDs Induction StrongerInductioninvanEijk'sMethod...96 iii

10 6.6Approximations ConclusionsandFutureWork RelatedWork ExperimentalResults FindingBugsinanAlphaMicroprocessorUsingSatisability Solvers 7.1Introduction Preliminaries TheMergeBuer SymbolicTrajectoryEvaluation BoundedModelChecking Verication AnalysisCycle BDD-basedSymbolicModelChecking AProposalforaMethodology SAT-basedSymbolicTrajectoryEvaluation BoundedModelChecking SAT-basedModelChecking:ATutorialandOverview 7.9Conclusions Introduction Preliminaries UsingSAT-solverstoVerifyReachableStateInvariants ModellingSystemsinPropositionalLogic ExpressingPropertiesofSystemsinPropositionalLogic ReachabilityAnalysis ImplementingtheAnalyses Induction BoundedModelChecking Analysis FormulaRepresentation ComparisonBetweentheSAT-basedMethods QBFTranslation iv

11 Bibliography 8.7InterestingFutureQuestions AComparisontoBDD-basedModelChecking v

12 vi

13 Chapter1 Introduction In1965,GordonMooregaveatalkwherehepredictedthatthecomplexity ofhardwaredeviceswoulddoubleevery18months.moore'spredictionhas 1.1 TheHardwareDevelopmentCrisis bythefactthattoday'sindustry-standardhardwaredescriptionlanguagesare ofhardwareisstaggering. Theresultingconstantlyincreasingpressureondesignersisfurtheraggravated turnedouttobeveryaccurate,andasaconsequence,thecurrentcomplexity meansthattheinterpretationofagivenlanguagedierssignicantlybetween verboseandcomplexlanguagesthatdonothaveawell-denedsemantics.this usabledesignswithalanguageisalsoverylong,andecientuseofalanguage resultinnonsenseafteranupgrade.thelearningtimetobeabletoproduce ferentversionsofthesametool;whatworkedtwoweeksagomayverywell reliesheavilyonintimateknowledgeofthequirksofaparticulartoolsuite. toolsfromdierentvendors.theinterpretationmightevendierbetweendif- Moreover,today'sdesignersmustnotonlycopewithverycomplexdesignsusing lessthanperfectlanguages;thedevelopmenttimeforagivendevicemustalso bekepttoanabsoluteminimumtoreducethetime-to-market.thishasled toaparadoxicalsituation,wherethefrequencyoferrorsconstantlygoesupas largerdesignshavetobeproducedinshortertime,whilelesstimecanbespent design,oramodelofit,onasetoftestvectors.thisisasimple,natural, onvalidation makingsurethatwhathasbeenbuiltindeedcorrespondstothe wayofmakingsurethatthecorrectdesignhasbeenbuilt.unfortunatelythis Thestandardwayofmakingsurethathardwareiscorrectistorunanished intendeddesign. validationmethodhasamajordrawback:onlyextremelysimpledesignscan realisethis,considerthatasimplecombinationalgatewithninputshastobe besimulatedexhaustivelysothatthefullfunctionalityofthechipistested.to 1

14 morethanhalfamillionyearstotestthefullfunctionalityofthemultiplier. Exhaustivetestingofrealisticcombinationalcircuitsishenceintractable,and testedon2ninputpatterns.thismeansthatinordertocheckthataninteger thegeneralcaseoftestingsequentialcircuitsisharderbyfar. multipliercorrectlymultipliestwo32-bitwords,wehavetotestiton264input vectors.assumingthatwecantestamillionpatternsasecond,wewouldneed ahandfulofoatingpointnumbers.thecostofrecallingthefaultychipswas astrous,asillustratedbythefailureofintel'spentiumchiptocorrectlydivide Unfortunately,failingbehaviourevenonasmallnumberofvectorscanbedis- Today'shardwaredevelopmentindustryisthusinabothersomesituation,which 475milliondollars. needstobeaddressedinatleasttwoways.first,itisvitalthathardware descriptionlanguagesareimprovedsothattheydonothinderthedesigner. Themosturgentofthenecessaryimprovementsistoconstructlanguagesthat haveamathematicallyprecisemeaning.second,thesupportforverifyingthat whathasbeendesignediscorrectmustbeimprovedsignicantly.itisimportant engineeringtogetherwithsimulation.thequestionishowthiscanbedone. tondalternativewaysofincreasingthecondenceindesignsotherthancareful industry-standarddevelopmentmethods. Inthisthesis,wewillconsiderformalmethodsasacomplementtotoday's 1.2 FormalMethods Aformalmethodideallyconsistsofthreecomponents:(1)Aformallanguage; 1.2.1FormalMethods Whatarethey? bepresent. aboutstatementsintheformallanguage.inpractice,notalloftheseneedto thatis,alanguagewhereeverywell-formedstatementhasamathematically denedmeaning;(2)toolsthathelptheuserdescribesystemsandrequirements Thepurposeofthethreecomponentsoftheformalmethodareasfollows:The intheformallanguage;and(3)aproofsystemthatallowstheusertoreason modelofthesystem,andoptionallyalsoconstructaspecication.whenthis language,togetherwiththetools,shouldletthedesignerwriteortranslatea isdone,theproofsystemshouldbeusedtodoasystemanalysis.hopefully, thisprocesswillallowthedesignertopredictwhethertheunderlyingsystem hasunintendedpropertiesthatwillcostmoney,orputhumansatrisk. ciselanguagethatisusedtowritedownaspecicationforagivensystem.the Aspecicationorientedformalmethodprovidesarichandmathematicallypre- Therearetwomainapproachestoformalmethods:(1)specicationoriented, and(2)vericationoriented. 2

15 thathasaformallydenedmeaning,itispossibletoreasonaboutthespecication.thepurposeofthisistovalidatethespecication tomakesurethe precisedescription.furthermore,asthespecicationiswritteninalanguage itforcesthespeciertothinkthroughthesystemcarefullyinordertomakea specicationmatchestheintentionofthedesigner.thiscanforexamplebe donebysimulatingthespecication,byprovingthatthespecicationiscon- processofwritingdownformalspecicationscanbringbenetstoaproject,as animplementationconformstosomespecication.inordertodothis,the theirreasonableness. Avericationorientedmethod,incontrast,hasthegoalofmakingsurethat sistent,orbyderivingconsequencesofthespecicationthatcanbecheckedfor atalowerlevelofabstraction.vericationtoolsarethenusedtotrytoestablish designerwritesaspecicationofthesystem,andamodelofanimplementation conformance.thiscanbedoneinanumberofways,afewofwhichwewill considerinsection1.2.3.ifnecessary,theprocesscanthenbereiteratedby writinganewspecicationatanevenlowerlevelandestablishingconformance ispost-hoc,meaningthatthesystemalreadyhasbeenbuilt,thegoalistoreach notbeenbuiltyet,thelowestlevelofspecicationcanbeusedasatemplate betweentheoldimplementation-levelandthenewlowerlevel.iftheverication theleveloftheexistingsystemmodel.ontheotherhand,ifthesystemhas systems.theanalysistoolscanonlybeappliedtothesemodels,nottothe realsystemsthemselves.thismeans,forexample,thataproofthatthemodel Itisimportanttorealisethatformalmethodsareconcernedwithmodelsof forautomaticormanualimplementation. specicationthatisdierentfromourintendedspecication,thentheproofis conformstothespecicationimpliespreciselythis,andnothingelse.ifthe modeldoesnotadequatelydescribetherealsystem,orifwehavewrittena worthless.ifwemodelacircuitatthelevelofbooleangates,wecanclearlynot 1.2.2ABriefHistoryofFormalMethods accountforerrorsatthetransistorlevel. Formalmethodsareintimatelyconnectedwithlogic,aslogicsareparticular recordedthoughtsaboutlogicdatebacktoaristotle'stime.aristotlemodelled situationsasacollectionofinformalstatements,andappliedwhatisknownas syllogisticreasoningtoanalysetheproblemathand. formallanguagesthatareusedtomodelandreasonaboutproblems.therst dreamtofconstructingalanguagerichenoughtomodelanykindofphenomena: TherstmodernproponentofformalmethodswasLeibnitz( ),who thecharacteristicauniversalis.anykindofquestionthatahumancouldenquire aboutshouldbepossibletoformulateinthislanguage.agivenquestionshould thenbedecidedusingadeviceleibnitzcalledthecalculusratiocinator.in thiswayeverydayquestionswouldbedecidedinascienticmannerbythe applicationofalgorithmictechniques.3

16 betherstcharacterisationofageneralpurposeformallanguagerichenough Leibnitz'dreamwasneverappreciatedbyhiscontemporaries;itwouldtake todeviseatheoryofsetsandelementaryarithmetic[37].thatfregewas ForemostoftheseearlypioneerswasGottlobFrege,whomadewhatwould ofthe19thcentury,manylogiciansstartedtothinkalongthelinesofleibnitz. almosttwohundredyearsbeforesimilarideasresurfaced.however,attheend interestedinthiswasnotverysurprising;hisoverallgoalwastoshowthat KurtGodeldeliveredacrushingblowtothishopebyprovingthatnonite allmathematicalreasoningcouldbereducedtologic.unfortunately,in1931 systemofaxiomsandinferencerulescouldbedevisedthatwouldgenerateall Godel'sresultsparkedalotofresearchintothelimitsofautomatedprocedures thetheoremsofelementaryarithmetic,andnonon-theorems[39]. non-trivial(inaprecise,technicalsense)propertyofprogramsisimpossibleto decidebyautomatedanalyses[80].muchofthecomputation-orientedresearch procedureswasseverelyrestricted.forexample,in1953riceprovedthatevery sequenceofsimilarresultsshowedthatthepowerofcompletelyautomated fordecidingwhetherformallanguagestatementsweretheoremsornot.awhole results",andfewresearcherswereinterestedinpursuingleibnitz'dream. duringthe1950sand1960swashencecenteredaroundderiving\impossibility Itwasnotuntilthelate1960sandearly1970sthatresearchersonceagaingot newupsurgeofinterestinrigour;manyresearchlanguagesweregivenmathematicallydenedsemantics,andthisallowedproofsaboutthelanguages,and aboutindividualprograms. seriouslyinterestedinapplyingformaltechniquestoreasoningandtheresearch comeinterestingtoindustry,andmanyresearcherswereinvolvedincreating tooko.itwasaboutthistimethatprogrammablecomputersstartedtobe- dierentkindsofformallanguages:programminglanguages.withthiscamea andhardwaresystems,andthedomainofcomputeraidedreasoningaboutthe models. methodswerelaid,bothinthedomainofmathematicalmodelsofsoftware Thenewfoundinterestinrigourledtotheestablishmentofmanynewresearch elds,anditwasduringthistimethefoundationsformuchoftoday'sformal byfloyd,hoare,anddijkstra[36,52,31].theseresearcherswereinterestedin Someoftherstattemptstoreasonformallyaboutprogramswereundertaken ofaprogramfragmentguaranteedtheassertedstateaftertheexecution. informalreasoninginrstorderlogictoprovethatthestatebeforetheexecution programannotationswithassertionsabouttheprogramstate.theythenused correctnessproofsforimperativeprograms,anddevelopedmethodsbasedon andchandy,whoinventedtheunitylogic[71];andlamport,whoinvented ThetechniquesforimperativeprogramvericationwereextendedbyOwicki thetemporallogicofactions[61].4 andgriestothemoregeneralcaseofparallelprograms[73].totallydierent calculiforspecifyingandreasoningaboutconcurrentprocesses[53,70];misra approachesweretakenbyhoareandmilner,whodevelopedspecialpurpose

17 velopingpowerfulspecicationmethodslikez,vdm,andlarch[91,58,44]. Whilesomeresearcherswerefocusingonprogramverication,otherswerede- Theeortsonprogramspecicationandvericationalsoinspiredresearchinto programminglanguagealgol60[19]. softwaresystems.earlysuccessstoriesincludeibm'suseofvdmtodenethe Thesemethodswereusedsuccessfullytospecifyandperformanalysisonlarge themodellingandvericationofhardware.someresearchersattemptedtouse extensionsofthetechniquesdevisedforprogramverication[30,88],whileothersdevelopednewformalismsaimedspecicallyathardwareandhardware-like vericationtechniqueswerestartingtobeappliedtosystemsofindustrialrelevanceandsize.examplesincludeshunt'smodellingandvericationofthefm 8501microprocessor[55]andCohns'correspondenceproofbetweendierent circuits[98],andmilne'sworkoncircal[69].inthemid-eighties,hardware workonveritas[49],wagner'sworkontransformationalcorrectnessproofsfor workonfp[83],johnson'sworkoncircuitderivation[57],daecheandhanna's system.earlyattemptstomodelandreasonaboutcircuitsincludesheeran's levelsofdescriptionsofthevipermicroprocessor[23]. tomaticmethods. Today'shardwarevericationmethodscanbedividedintointeractive,andau FormalHardwareVericationMethods Ininteractivemethods,theuserguidesthevericationprocess.Oftenthespecicationlanguageisrichenoughtobeundecidable;fullyautomaticverication provinginhigherorderlogic[40].inthisapproach,themodelofthecircuit,and isthereforenotevenattainableintheory. Aprimeexampleofaninteractivemethodishardwarevericationbytheorem bystartingfromaxiomsofthelogic,andapplyinginferencerulestogenerate theprocessistoestablishthatthecompoundstatementthatexpressesthatthe modelimplementsthespecicationisalogicaltruthinthesystem.thisisdone thespecicationisexpressedasstatementsinaverypowerfullogic.thegoalof new,logicallytrue,statements.thenatureoftheinferencerulesguaranteesthat ifthecorrectnessstatementisderivablebyanitechainofapplicationsofrules, startingfromaxiomsonly,thenthemodelmustimplementthespecication. Evenbetweendierentinteractivemethods,thelevelofinteractivenesscanvary substantially.forexample,certainhigherorderlogictheoremprovers,such aspvs[29],containsautomaticdecisionproceduresthatcanbeappliedto statementsofparticularforms.suchautomateddecisionproceduresexistfor onlyaxiomsareusedasstartingpointsforproofs. exampleforpresburgerarithmetic[76](arithmeticstatementsusingaddition butnotmultiplication).otherinteractivetheoremprovers,suchasisabelle[75], bymakingsurethateveryapplicationofaninferenceruleisvalid,andthat providemuchlessautomation;theymainlyhelptheuserwiththebookkeeping 5

18 Automaticmethods,incontrast,attempttoseparatetheuserfromtheindividualvericationsteps.Thismeansthatdesigners,whoseareaofexpertiseisthe workstouseit.however,tocontinuetheanalogywithcircuitsynthesis,the usermuststillknowsomethingaboutthetooltogetsucientlygoodresults. constructionofthecircuitsthemselves,candotheirownvericationwithout muchlikedesignersdonotneedtofullyunderstandhowahardwaresynthesiser spendingalongperiodoftimelearningaboutthetheoryunderlyingthemethod, relativelyweakproperties.forexample,fullhigherorderlogicwillprobably Inordertoachievefullautomation,itisnecessarytorestrictthecheckingto neverbeusedsuccessfullyasaspecicationlanguageaimedatautomaticproofs, thatcanbeachieved.forexample,duetorice'stheorem,ifthemodellingand asitistoocomplex.thereexistsacleartradeobetweenthecomplexityofthe modellinglanguageandthepropertiestocheck,andthedegreeofautomation Oneofthemostwidelyusedautomaticmethodsofverifyinghardwareismodel programs,thentherearemanyquestionsthatcannotbedecidedautomatically. checking[21,79].theaimofthisvericationmethodistotakeadescriptionofa specicationlanguageisstrongenoughtomodelprogramsandpropertiesof expressedinaweaklogicholdbyexhaustivelysearchingthroughthestatespace hardwarecomponentasanitestatemachine,andestablishwhetherproperties beexpressedarestillsolimitedthatthelogicitselfcanbedecided(thereexists propertiesofsystemsthatchangeovertime.however,thepropertiesthatcan oftime".thespecicationlanguageiscalledatemporallogic,asitcanexpress xistrue",\ifsignalxistrue,thensignalymustbefalseaftersomeniteperiod ofthemodel.examplesofpropertiesthatcanbecheckedare\atalltimes,signal aprocedurethatalwaysisabletotellwhetherastatementisalogicaltruthor not). isimportanttorealisethatthisalsoistrueonthedesignsideofhardwaredevelopment.whenindividualcomponentsaredesignedfromtransistors,idealised technology,asthemathematicsthatisinvolvedistoocomplicated.however,it entlevels.thelevelofelectronowisbeyondthereachoftoday'sverication Independentofthevericationmethoditself,circuitscanbemodelledatdier- modelsareusedforthetransistorsinordertofacilitatespeedyanalysis. accordingtoa\truthtable",withoutconsideringanyotherpossibilities.vericationatthislevelmayconsistinestablishingthatsimpletemporalproperties Thelowestlevelofmodellingthatisroutinelyprocessedtodayistransistorlevel transistorsasdevicesthatpropagateeitherofthevalues0,1,orx(unknown) hold. descriptions.modelsatthislevelarestilloftensimpliedbydescribingthe individualbuildingblocksarelogicalgatessuchasand-gatesandor-gates.at thislevel,vericationmayconsistofestablishingthatatransistorlevelimplementationimplementsagatenetwork,orcheckingthatatemporalspecication holds. Thenextlevelupinthehierarchyisthelevelofgateleveldesigns.Herethe 6

19 Fromthegatelevelup,thereexistsamultitudeoflevelsthatcircuitscanbe modelledat.forexample,atthelevelofarithmetic,anadditionoftwonumbers fromaninnitedomainisamonolithicoperation.justasgodel'stheorem predicts,thisisthelevelwhereautomationstartstobecometroublesome,and usersoftenturntomethodssuchasinteractivetheoremproving. Inthisthesis,wecontributetobettermethodsfordesigninghardwareintwo ways. 1.3 AimoftheThesis thatfunctionallanguagesoeracleanwayofdescribingsynchronoushardware, precisedescriptionsofsynchronoushardware,andallowstheusertointerfaceto vericationtoolsthroughaprogrammableinterface.thethesisofthisworkis First,wepresentahardwaredescriptionandvericationplatform,Lava,embeddedinthefunctionallanguageHaskell.Thisplatformsupportsmathematically andthatmodernprogramminglanguagefeaturesareusefultoolsalsoforhardwaredesigners.wealsoshowhowusefulitisthatlavaisaprogrammablevericationplatform,whichallowsustodevisespecialpurposevericationstrategies forparticularfamiliesofhardwarecomponents. hardware.weillustratethisbypresentingcasestudiesandnewtechniques canbeusedasanecientvehicleforprovingcorrectnessandndingbugsin Themajorthesisofthispartoftheworkisthatautomatictheoremproving forthevericationofsequentialhardwareatdierentlevelsonabstraction. Second,wefocusonhowautomatictheoremprovingcanbeusedasatool vericationmethods. thatgiveorderofmagnitudespeedupscomparedtostate-of-the-artautomatic 1.4 PaperASynopsis ThepapercontainsanoverviewoftheLavahardwaredescriptionandveri- 1998,andisjointworkwithKoenClaessen,MarySheeran,andSatnamSingh. paperappearedintheinternationalconferenceonfunctionalprogramming Therstpaperinthisthesisiscalled\Lava:HardwaredesigninHaskell".The cationplatform,whichisspeciallydesignedfordescribing,andanalysingsyn- chronoushardwareatthegatelevel. allowsthedesignertoeasilyconstructparametrisedcircuits,anddeneinterateanewcircuitbypluggingthebuildingblockstogether.acrucialfeatureof KeyelementsoftheLavaapproachisacleanwayofdescribingcircuitsthat connectionpatterns meta-circuitsthatgivenanumberofothercircuitsgener- 7

20 besentotoexternaltheoremprovers. andveriedbyinterpretingitinanotherwaythatproducesformulasthatcan example,thesamedescriptioncanbesimulatedbyinterpretingitinoneway, Lavaisthepossibilitytointerprethardwaredescriptionsinmultipleways.For (FFT).TheFFTisaparticularweightedsumofcomplexnumbersthatfor Thepresentationincludesacasestudy:Thespecicationandvericationofa frequencyinformationfromsampledsignals.thefactthatthecircuitoperates parametrisedcombinationalcircuitforperformingthefastfouriertransform instancecanbeusedtodoquickmultiplicationofpolynomials,andtoextract Lavacouldbeusedtomodelandverifythekindsofcomponentstheywere ThecasestudyisjointworkwithEricssonCadlab,whowantedtostudyhow some,asmanystandardtechniquesareunabletocopewitharithmetic. onthelevelofcomplexnumbersmeansthatautomaticvericationistrouble- interestedin InthispaperwecontinuetheworkondescribingandverifyingFFTcircuitry, anditappearedintheinternationalconferenceoncomputeraidedverication PaperBiscalled\AutomaticVericationofCombinationalandPipelinedFFTs", Inordertoverifythepipelinedimplementation,wedeviseaspecialpurpose FFTweprovedcorrectinpaperA. byusinglavatoimplementasequential,pipelined,versionofthecombinational simulationandinduction,inadditiontothetheoremprovingtechniqueswe apipelinedcircuitimplementation.thisprooftechniquereliesonsymbolic appliedinordertoverifythecombinationalfftcomponent. prooftechniqueforestablishingcorrespondencebetweenacombinationaland analyses,andimplementtheprooftechniqueasananalysisparametrisedbya WetakeadvantageoftheeasewithwhichLavacanbeextendedwithcustom sequentialandacombinationalcircuit. PaperCiscalled\SymbolicModelCheckingwithSetsofStatesRepresented asformulas".thispaperisarevisedversionoftechnicalreportcs99903, ChalmersUniversityofTechnology. Here,inspiredbytheworkwedidonverifyingsequentialcircuitsbytheorem ingcanbeconvertedtousepropositionallogictheoremprovingratherthanthe provinginpaperb,wepresentanideaforhowstandardsymbolicmodelcheck- morestandardchoiceofbinarydecisiondiagrams(bdds). 8

21 gorithmstouseformulasasasymbolicrepresentationforthesystemthatis analysed.weremovebooleanquantiersthatariseduringstatespacetraversal byapplyinganaiveunfoldingrule.inordertomakesurethattherepresentationsdonotgrowtoomuch,wesuggestanalgorithmforminimisingformulas Thepaperpresentsaconversionofthestandardsymbolicmodelcheckingalformulas. Weconcludethepaperbydiscussinghowtheideatousepropositionalformulas thatusesstalmarck'smethodofpropositionalprooftodetectequivalentsub- asarepresentation,andtheoremprovingtoimplementoperationsontherepresentationcanbeextendedtostrongerlogics,andthepossiblebenetsthereof. Thispaperiscalled\SymbolicReachabilityAnalysisbasedonSAT-solvers".It PaperD appearedintheinternationalconferenceontoolsandalgorithmsfortheconstructionandanalysisofsystems2000,andisjointworkwithparoshabdullvertingstandardmodelcheckingalgorithmstouseformulasandpropositional logictheoremproving.here,werestrictthepresentationtothecaseofsymbolic InthispaperwepresentFIXIT,apracticalimplementationoftheideaofcon- andniklaseen. inpaperc),butourimplementationhandlesthefulllogic. reachabilityanalysis(asingleoperatorfromthetemporallogicthatwascovered Keyelementsofourapproacharetouseaspecialpurposerepresentationfor formulasthatdoessimplereductionsautomatically,andtousesomeextrarules inthequantiertranslatorinsteadofthesinglerulewesuggestedinpaperc. PaperE someexamplesthatareveryhardfortwomaturebdd-basedmodelcheckers. Weillustratethattheresulting,fairlynaive,modelcheckercanstillcopewith Thispaper,\SAT-basedVericationwithoutStateSpaceTraversal",isjoint workwithkoenclaessen.itappearedintheinternationalconferenceonformalmethodsincomputeraideddesign2000. Algorithmsthatavoidthebooleanquantication,butstillusepropositional algorithmswepresentedinpaperdworksverypoorlyforcertainexamples. Thetranslationofbooleanquantiersnecessaryforstatespacetraversalinthe logictheoremproving,arethereforeveryinteresting. sothatitcanndmoreinformation,andmakeitcomplete.furthermore,by Stalmarck'salgorithmratherthanBDDs.Wealsostrengthenthealgorithm fordoingsequentialequivalencecheckingwithoutstatespacetraversal,touse InthispaperweconvertVanEijk'salgorithm,apreviouslypresentedmethod 9

22 examiningtheconnectionbetweenthealgorithmandoverapproximativesymbolicreachabilityanalysis,wedeviseananalogousdualalgorithmandamutual compareresultswithtworelatedmethodsbasedonpropositionallogictheorem proving,andamaturebdd-basedmodelchecker. Weillustratethepoweroftheresultinganalysesonsomebenchmarks,and improvementalgorithm. PaperF,\FindingBugsinanAlphaMicroprocessorusingSatisabilitySolvers", isjointworkwithtimleonardandabdelmokkedem.itisacceptedforpublicationattheinternationalconferenceoncomputeraidedverication2001. Herewepresenttheresultsofusingacombinationoftwomodelcheckingtechniquesbasedonsatisabilitysolverstondbugsinthememorysubsystemof anext-generationmicroprocessor. Therstofthesetechniquesiscalledboundedmodelchecking.Wecompare theperformanceofboundedmodelcheckingtobdd-basedmodelchecking, anddemonstratethatitcanbeusedtoreducetheruntimenecessaryfornding Thisanalysisisaversionofmodelcheckingthatconsistsofablendofabstract certainbugsinrealdesignsfromdaystominutes. ThesecondtechniqueissymbolictrajectoryevaluationbasedonSAT-solving. developingspecications. ocomparedtoboundedmodelcheckingisthatwehavetospendmoretime ofthelengthofminimumfailuretraces,usingnegligibleruntimes.thetradebolictrajectoryevaluationcanbeusedtondverycomplexbugs,interms interpretationandsymbolicsimulation.wedemonstratethatsat-basedsym- Weconcludethepaperbypresentingsomeadviceonusingacombinationofthe twomodelcheckingtechniquesforindustrial-strengthverication. PaperG Thispaperiscalled\SymbolicModelCheckingbasedonSAT-solvers:An logictheoremprovingbypresentingthreedierentapproachesthathaveappearedintheliterature. overviewandtutorial".itisjointworkwithmarysheeranandgunnarstalmarck, Herewegiveanoverviewoftheeldofmodelcheckingbasedonpropositional andissubmittedforpublication. PaperD,andsomeconclusionswehavecometowhileworkingwiththethree toimplementtheanalysesintheresearchmodelcheckerfixitwepresentedin Ourpresentationisgiveninatutorialstyle,andweputemphasisondemonstratinghowthemethodsarerelated.Wepresentsometechniquesthatareused 10

Gates, Circuits, and Boolean Algebra

Gates, Circuits, and Boolean Algebra Gates, Circuits, and Boolean Algebra Computers and Electricity A gate is a device that performs a basic operation on electrical signals Gates are combined into circuits to perform more complicated tasks

More information

1. True or False? A voltage level in the range 0 to 2 volts is interpreted as a binary 1.

1. True or False? A voltage level in the range 0 to 2 volts is interpreted as a binary 1. File: chap04, Chapter 04 1. True or False? A voltage level in the range 0 to 2 volts is interpreted as a binary 1. 2. True or False? A gate is a device that accepts a single input signal and produces one

More information

Tutorial on Using Excel Solver to Analyze Spin-Lattice Relaxation Time Data

Tutorial on Using Excel Solver to Analyze Spin-Lattice Relaxation Time Data Tutorial on Using Excel Solver to Analyze Spin-Lattice Relaxation Time Data In the measurement of the Spin-Lattice Relaxation time T 1, a 180 o pulse is followed after a delay time of t with a 90 o pulse,

More information

2Proofbymathematicalinductionplaysacrucialroleinthevericationofprogramtrans-

2Proofbymathematicalinductionplaysacrucialroleinthevericationofprogramtrans- SubmissiontoJ.FunctionalProgrammingSpecialIssueonTheoremProving&FunctionalProgramming AutomaticVericationofFunctionswith DepartmentofComputing&ElectricalEngineering, AccumulatingParameters UniversityofEdinburgh,80SouthBridge,

More information

#1-12: Write the first 4 terms of the sequence. (Assume n begins with 1.)

#1-12: Write the first 4 terms of the sequence. (Assume n begins with 1.) Section 9.1: Sequences #1-12: Write the first 4 terms of the sequence. (Assume n begins with 1.) 1) a n = 3n a 1 = 3*1 = 3 a 2 = 3*2 = 6 a 3 = 3*3 = 9 a 4 = 3*4 = 12 3) a n = 3n 5 Answer: 3,6,9,12 a 1

More information

Almost all spreadsheet programs are based on a simple concept: the malleable matrix.

Almost all spreadsheet programs are based on a simple concept: the malleable matrix. MS EXCEL 2000 Spreadsheet Use, Formulas, Functions, References More than any other type of personal computer software, the spreadsheet has changed the way people do business. Spreadsheet software allows

More information

Binary Adders: Half Adders and Full Adders

Binary Adders: Half Adders and Full Adders Binary Adders: Half Adders and Full Adders In this set of slides, we present the two basic types of adders: 1. Half adders, and 2. Full adders. Each type of adder functions to add two binary bits. In order

More information

Let s put together a Manual Processor

Let s put together a Manual Processor Lecture 14 Let s put together a Manual Processor Hardware Lecture 14 Slide 1 The processor Inside every computer there is at least one processor which can take an instruction, some operands and produce

More information

Notes on Excel Forecasting Tools. Data Table, Scenario Manager, Goal Seek, & Solver

Notes on Excel Forecasting Tools. Data Table, Scenario Manager, Goal Seek, & Solver Notes on Excel Forecasting Tools Data Table, Scenario Manager, Goal Seek, & Solver 2001-2002 1 Contents Overview...1 Data Table Scenario Manager Goal Seek Solver Examples Data Table...2 Scenario Manager...8

More information

WESTMORELAND COUNTY PUBLIC SCHOOLS 2011 2012 Integrated Instructional Pacing Guide and Checklist Computer Math

WESTMORELAND COUNTY PUBLIC SCHOOLS 2011 2012 Integrated Instructional Pacing Guide and Checklist Computer Math Textbook Correlation WESTMORELAND COUNTY PUBLIC SCHOOLS 2011 2012 Integrated Instructional Pacing Guide and Checklist Computer Math Following Directions Unit FIRST QUARTER AND SECOND QUARTER Logic Unit

More information

By: Peter K. Mulwa MSc (UoN), PGDE (KU), BSc (KU) Email: Peter.kyalo@uonbi.ac.ke

By: Peter K. Mulwa MSc (UoN), PGDE (KU), BSc (KU) Email: Peter.kyalo@uonbi.ac.ke SPREADSHEETS FOR MARKETING & SALES TRACKING - DATA ANALYSIS TOOLS USING MS EXCEL By: Peter K. Mulwa MSc (UoN), PGDE (KU), BSc (KU) Email: Peter.kyalo@uonbi.ac.ke Objectives By the end of the session, participants

More information

FORDHAM UNIVERSITY CISC 3593. Dept. of Computer and Info. Science Spring, 2011. Lab 2. The Full-Adder

FORDHAM UNIVERSITY CISC 3593. Dept. of Computer and Info. Science Spring, 2011. Lab 2. The Full-Adder FORDHAM UNIVERSITY CISC 3593 Fordham College Lincoln Center Computer Organization Dept. of Computer and Info. Science Spring, 2011 Lab 2 The Full-Adder 1 Introduction In this lab, the student will construct

More information

Chapter 4. Gates and Circuits. Chapter Goals. Chapter Goals. Computers and Electricity. Computers and Electricity. Gates

Chapter 4. Gates and Circuits. Chapter Goals. Chapter Goals. Computers and Electricity. Computers and Electricity. Gates Chapter Goals Chapter 4 Gates and Circuits Identify the basic gates and describe the behavior of each Describe how gates are implemented using transistors Combine basic gates into circuits Describe the

More information

SOAL-SOAL MICROSOFT EXCEL 1. The box on the chart that contains the name of each individual record is called the. A. cell B. title C. axis D.

SOAL-SOAL MICROSOFT EXCEL 1. The box on the chart that contains the name of each individual record is called the. A. cell B. title C. axis D. SOAL-SOAL MICROSOFT EXCEL 1. The box on the chart that contains the name of each individual record is called the. A. cell B. title C. axis D. legend 2. If you want all of the white cats grouped together

More information

Understanding Logic Design

Understanding Logic Design Understanding Logic Design ppendix of your Textbook does not have the needed background information. This document supplements it. When you write add DD R0, R1, R2, you imagine something like this: R1

More information

Programmable Logic Devices (PLDs)

Programmable Logic Devices (PLDs) Programmable Logic Devices (PLDs) Lesson Objectives: In this lesson you will be introduced to some types of Programmable Logic Devices (PLDs): PROM, PAL, PLA, CPLDs, FPGAs, etc. How to implement digital

More information

Preamble. Kirchoff Voltage Law (KVL) Series Resistors. In this section of my lectures we will be. resistor arrangements; series and

Preamble. Kirchoff Voltage Law (KVL) Series Resistors. In this section of my lectures we will be. resistor arrangements; series and Preamble Series and Parallel Circuits Physics, 8th Edition Custom Edition Cutnell & Johnson Chapter 0.6-0.8, 0.0 Pages 60-68, 69-6 n this section of my lectures we will be developing the two common types

More information

Working With Direct Deposit Accounts and Your Payment Elections

Working With Direct Deposit Accounts and Your Payment Elections Working With Direct Deposit Accounts and This document contains instructions in the following areas for working with your direct deposit accounts and payment elections: Overview Working with Your Direct

More information

Heuristic Methods. Part #1. João Luiz Kohl Moreira. Observatório Nacional - MCT COAA. Observatório Nacional - MCT 1 / 14

Heuristic Methods. Part #1. João Luiz Kohl Moreira. Observatório Nacional - MCT COAA. Observatório Nacional - MCT 1 / 14 Heuristic Methods Part #1 João Luiz Kohl Moreira COAA Observatório Nacional - MCT Observatório Nacional - MCT 1 / Outline 1 Introduction Aims Course's target Adviced Bibliography 2 Problem Introduction

More information

Circuits and Boolean Expressions

Circuits and Boolean Expressions Circuits and Boolean Expressions Provided by TryEngineering - Lesson Focus Boolean logic is essential to understanding computer architecture. It is also useful in program construction and Artificial Intelligence.

More information

EXCEL 2010: PAGE LAYOUT

EXCEL 2010: PAGE LAYOUT EXCEL 2010: PAGE LAYOUT PAGE SET UP Options to change the page layout of a spreadsheet are available from the PAGE LAYOUT tab. Most of these options are available from the PAGE SETUP group on this tab.

More information

Online Quotes Our 6 Top Tips

Online Quotes Our 6 Top Tips Online Quotes Our 6 Top Tips While we hope you ll find our online quotes system simple and easy to use, to help you along the way, we ve gathered the 6 most common queries users have, with the answers!

More information

Basic Logic Gates Richard E. Haskell

Basic Logic Gates Richard E. Haskell BASIC LOGIC GATES 1 E Basic Logic Gates Richard E. Haskell All digital systems are made from a few basic digital circuits that we call logic gates. These circuits perform the basic logic functions that

More information

Lecture 13 of 41. More Propositional and Predicate Logic

Lecture 13 of 41. More Propositional and Predicate Logic Lecture 13 of 41 More Propositional and Predicate Logic Monday, 20 September 2004 William H. Hsu, KSU http://www.kddresearch.org http://www.cis.ksu.edu/~bhsu Reading: Sections 8.1-8.3, Russell and Norvig

More information

Cofactor Expansion: Cramer s Rule

Cofactor Expansion: Cramer s Rule Cofactor Expansion: Cramer s Rule MATH 322, Linear Algebra I J. Robert Buchanan Department of Mathematics Spring 2015 Introduction Today we will focus on developing: an efficient method for calculating

More information

SECTION 500 REPORTING INSTRUCTIONS SCHEDULE RFA RECONCILIATION OF INPATIENT AND OUTPATIENT DATA SETS REVENUE TO FINANCIAL DATA

SECTION 500 REPORTING INSTRUCTIONS SCHEDULE RFA RECONCILIATION OF INPATIENT AND OUTPATIENT DATA SETS REVENUE TO FINANCIAL DATA SECTION 500 REPORTING INSTRUCTIONS SCHEDULE RFA RECONCILIATION OF INPATIENT AND OUTPATIENT DATA SETS REVENUE TO FINANCIAL DATA Overview Schedule RFA is provided to enable each hospital to reconcile, within

More information

Foundations of Logic and Mathematics

Foundations of Logic and Mathematics Yves Nievergelt Foundations of Logic and Mathematics Applications to Computer Science and Cryptography Birkhäuser Boston Basel Berlin Contents Preface Outline xiii xv A Theory 1 0 Boolean Algebraic Logic

More information

programsitproduces.finally,weshowhowtoproduceecient,optimizingprogramgeneratorsby

programsitproduces.finally,weshowhowtoproduceecient,optimizingprogramgeneratorsby TopicsinOnlinePartialEvaluation TechnicalReport:CSL-TR-93-563 (alsofusememo93-14) March,1993 ErikRuf DepartmentsofElectricalEngineering&ComputerScience ComputerSystemsLaboratory Partialevaluationisaperformanceoptimizationtechniqueforcomputerprograms.Whenaprogram

More information

Digital Logic Design. Basics Combinational Circuits Sequential Circuits. Pu-Jen Cheng

Digital Logic Design. Basics Combinational Circuits Sequential Circuits. Pu-Jen Cheng Digital Logic Design Basics Combinational Circuits Sequential Circuits Pu-Jen Cheng Adapted from the slides prepared by S. Dandamudi for the book, Fundamentals of Computer Organization and Design. Introduction

More information

APPLE INC FORM FWP. (Free Writing Prospectus - Filing under Securities Act Rules 163/433) Filed 05/07/15

APPLE INC FORM FWP. (Free Writing Prospectus - Filing under Securities Act Rules 163/433) Filed 05/07/15 APPLE INC FORM FWP (Free Writing Prospectus - Filing under Securities Act Rules 163/433) Filed 05/07/15 Address ONE INFINITE LOOP CUPERTINO, CA 95014 Telephone (408) 996-1010 CIK 0000320193 Symbol AAPL

More information

RIFIS Ad Hoc Reports

RIFIS Ad Hoc Reports RIFIS Ad Hoc Reports To retrieve the entire list of all Ad Hoc Reports, including the Base reports and any additional reports published to your Role, select Ad Hoc for the Type under Filter Report By and

More information

COMPUTER SKILLS PLACEMENT TEST QUESTIONS MS OFFICE 2010/WINDOWS 7

COMPUTER SKILLS PLACEMENT TEST QUESTIONS MS OFFICE 2010/WINDOWS 7 COMPUTER SKILLS PLACEMENT TEST QUESTIONS MS OFFICE 2010/WINDOWS 7 CPS Assessment Test Questions/Answers DCCCD Spring 2014 The Computer Skills Placement Test (CSP) is designed to assess the computer literacy

More information

threads threads threads

threads threads threads AHybridMultithreading/Message-PassingApproachforSolving IrregularProblemsonSMPClusters Jan-JanWu InstituteofInformationScience AcademiaSinica Taipei,Taiwan,R.O.C. Chia-LienChiang Nai-WeiLin Dept.ComputerScience

More information

Australian/New Zealand Standard

Australian/New Zealand Standard AS/NZS 3200.1.8:2005 (IEC 60601-1-8:2003) AS/NZS 3200.1.8:2005 Australian/New Zealand Standard Medical electrical equipment Part 1.8: General requirements for safety Collateral Standard: General requirements,

More information

Dick Schwanke Finite Math 111 Harford Community College Fall 2013

Dick Schwanke Finite Math 111 Harford Community College Fall 2013 Annuities and Amortization Finite Mathematics 111 Dick Schwanke Session #3 1 In the Previous Two Sessions Calculating Simple Interest Finding the Amount Owed Computing Discounted Loans Quick Review of

More information

Higher National Unit Specification. General information for centres. Unit title: Digital Electronics. Unit code: DN4E 34

Higher National Unit Specification. General information for centres. Unit title: Digital Electronics. Unit code: DN4E 34 Higher National Unit Specification General information for centres Unit code: DN4E 34 Unit purpose: The Unit is designed to enable candidates to know, understand and apply the basic concepts of digital

More information

Experiment 4: Sensor Bridge Circuits (tbc 1/11/2007, revised 2/20/2007, 2/28/2007) I. Introduction. From Voltage Dividers to Wheatstone Bridges

Experiment 4: Sensor Bridge Circuits (tbc 1/11/2007, revised 2/20/2007, 2/28/2007) I. Introduction. From Voltage Dividers to Wheatstone Bridges Experiment 4: Sensor Bridge Circuits (tbc //2007, revised 2/20/2007, 2/28/2007) Objective: To implement Wheatstone bridge circuits for temperature measurements using thermistors. I. Introduction. From

More information

CE 314 Engineering Economy. Interest Formulas

CE 314 Engineering Economy. Interest Formulas METHODS OF COMPUTING INTEREST CE 314 Engineering Economy Interest Formulas 1) SIMPLE INTEREST - Interest is computed using the principal only. Only applicable to bonds and savings accounts. 2) COMPOUND

More information

Further Topics in Actuarial Mathematics: Premium Reserves. Matthew Mikola

Further Topics in Actuarial Mathematics: Premium Reserves. Matthew Mikola Further Topics in Actuarial Mathematics: Premium Reserves Matthew Mikola April 26, 2007 Contents 1 Introduction 1 1.1 Expected Loss...................................... 2 1.2 An Overview of the Project...............................

More information

Static Program Transformations for Efficient Software Model Checking

Static Program Transformations for Efficient Software Model Checking Static Program Transformations for Efficient Software Model Checking Shobha Vasudevan Jacob Abraham The University of Texas at Austin Dependable Systems Large and complex systems Software faults are major

More information

Welcome to the topic on queries in SAP Business One.

Welcome to the topic on queries in SAP Business One. Welcome to the topic on queries in SAP Business One. 1 In this topic, you will learn to create SQL queries using the SAP Business One query tools Query Wizard and Query Generator. You will also see how

More information

Department of Chemical Engineering ChE-101: Approaches to Chemical Engineering Problem Solving MATLAB Tutorial VI

Department of Chemical Engineering ChE-101: Approaches to Chemical Engineering Problem Solving MATLAB Tutorial VI Department of Chemical Engineering ChE-101: Approaches to Chemical Engineering Problem Solving MATLAB Tutorial VI Solving a System of Linear Algebraic Equations (last updated 5/19/05 by GGB) Objectives:

More information

FTS Real Time System Project: Portfolio Diversification Note: this project requires use of Excel s Solver

FTS Real Time System Project: Portfolio Diversification Note: this project requires use of Excel s Solver FTS Real Time System Project: Portfolio Diversification Note: this project requires use of Excel s Solver Question: How do you create a diversified stock portfolio? Advice given by most financial advisors

More information

MICROSTATION INFORMATION BRIDGE DEPARTMENT

MICROSTATION INFORMATION BRIDGE DEPARTMENT MICROSTATION INFORMATION BRIDGE DEPARTMENT CFLHD S FTP SITE ACCESS server name = ftp.cflhd.gov user name = cflhd password = fhwa-cflhd Feel free to tell the user name and password to anyone who needs it.

More information

To Evaluate an Algebraic Expression

To Evaluate an Algebraic Expression 1.5 Evaluating Algebraic Expressions 1.5 OBJECTIVES 1. Evaluate algebraic expressions given any signed number value for the variables 2. Use a calculator to evaluate algebraic expressions 3. Find the sum

More information

CHAPTER 14 ORDINAL MEASURES OF CORRELATION: SPEARMAN'S RHO AND GAMMA

CHAPTER 14 ORDINAL MEASURES OF CORRELATION: SPEARMAN'S RHO AND GAMMA CHAPTER 14 ORDINAL MEASURES OF CORRELATION: SPEARMAN'S RHO AND GAMMA Chapter 13 introduced the concept of correlation statistics and explained the use of Pearson's Correlation Coefficient when working

More information

Solving Linear Programs in Excel

Solving Linear Programs in Excel Notes for AGEC 622 Bruce McCarl Regents Professor of Agricultural Economics Texas A&M University Thanks to Michael Lau for his efforts to prepare the earlier copies of this. 1 http://ageco.tamu.edu/faculty/mccarl/622class/

More information

IMPLEMENTATION OF HIGH SPEED ENHANCED CSLA BASED ON GATED D-LATCH

IMPLEMENTATION OF HIGH SPEED ENHANCED CSLA BASED ON GATED D-LATCH IMPLEMENTATION OF HIGH SPEED ENHANCED BASED ON GATED D-LATCH 1 MEDA NAGAPAVANI, 2 T. JYOTHI 1 P.G Student, VLSI Design, Dept of ECE, 2 Assistant Professor, Dept of ECE. Sri Venkatesa Perumal College of

More information

VI. The Feasibility Study. The Feasibility Study Phase

VI. The Feasibility Study. The Feasibility Study Phase VI. The Feasibility Study What is a feasibility study? What to study and conclude? Benefits and costs Cost/Benefit analysis Accounting methods Comparing alternatives Do it! 2002 Jaelson Castro and John

More information

Analytics with Excel and ARQUERY for Oracle OLAP

Analytics with Excel and ARQUERY for Oracle OLAP Analytics with Excel and ARQUERY for Oracle OLAP Data analytics gives you a powerful advantage in the business industry. Companies use expensive and complex Business Intelligence tools to analyze their

More information

CSE373: Data Structures and Algorithms Lecture 3: Math Review; Algorithm Analysis. Linda Shapiro Winter 2015

CSE373: Data Structures and Algorithms Lecture 3: Math Review; Algorithm Analysis. Linda Shapiro Winter 2015 CSE373: Data Structures and Algorithms Lecture 3: Math Review; Algorithm Analysis Linda Shapiro Today Registration should be done. Homework 1 due 11:59 pm next Wednesday, January 14 Review math essential

More information

Chapter 5: Sequential Circuits (LATCHES)

Chapter 5: Sequential Circuits (LATCHES) Chapter 5: Sequential Circuits (LATCHES) Latches We focuses on sequential circuits, where we add memory to the hardware that we ve already seen Our schedule will be very similar to before: We first show

More information

Basic Pivot Tables. To begin your pivot table, choose Data, Pivot Table and Pivot Chart Report. 1 of 18

Basic Pivot Tables. To begin your pivot table, choose Data, Pivot Table and Pivot Chart Report. 1 of 18 Basic Pivot Tables Pivot tables summarize data in a quick and easy way. In your job, you could use pivot tables to summarize actual expenses by fund type by object or total amounts. Make sure you do not

More information

IMPLEMENTATION OF HIGH SPEED ENHANCED CSLA BASED ON GATED D-LATCH:

IMPLEMENTATION OF HIGH SPEED ENHANCED CSLA BASED ON GATED D-LATCH: IMPLEMENTATION OF HIGH SPEED ENHANCED BASED ON GATED D-LATCH 1 MEDA NAGAPAVANI, 2 T. JYOTHI 1 P.G Student, VLSI Design, Dept of ECE, 2 Assistant Professor, Dept of ECE. Sri Venkatesa Perumal College of

More information

Irwin, Basic Engineering Circuit Analysis, 9/E 1 3.1 P3.1. Figure P3.1. Chapter 3: Loop and Nodal Techniques for Circuit Analysis Problem 3.

Irwin, Basic Engineering Circuit Analysis, 9/E 1 3.1 P3.1. Figure P3.1. Chapter 3: Loop and Nodal Techniques for Circuit Analysis Problem 3. Irwin, Basic Engineering Circuit Analysis, 9/E 1 3.1 P3.1 Figure P3.1 3k Chapter 3: Loop and Nodal Techniques for Circuit Analysis Problem 3.1 Ch03.indd 1 12/22/08 4:40:33 PM Irwin, Basic Engineering Circuit

More information

The University of Queensland. Classification Guidelines for. Research-Related General Staff Positions. (HEW Levels 1-9).

The University of Queensland. Classification Guidelines for. Research-Related General Staff Positions. (HEW Levels 1-9). The University of Queensland Classification Guidelines for Research-Related General Staff Positions (HEW Levels 1-9). Appendix 2 Revised & updated October 2003 PART 1 - Definitions The qualification levels

More information

Lecture 8: Synchronous Digital Systems

Lecture 8: Synchronous Digital Systems Lecture 8: Synchronous Digital Systems The distinguishing feature of a synchronous digital system is that the circuit only changes in response to a system clock. For example, consider the edge triggered

More information

A single register, called the accumulator, stores the. operand before the operation, and stores the result. Add y # add y from memory to the acc

A single register, called the accumulator, stores the. operand before the operation, and stores the result. Add y # add y from memory to the acc Other architectures Example. Accumulator-based machines A single register, called the accumulator, stores the operand before the operation, and stores the result after the operation. Load x # into acc

More information

Excel Add-ins Quick Start Guide

Excel Add-ins Quick Start Guide Excel Add-ins Quick Start Guide Contents Bloomberg - Excel Add-In... 2 Datastream - Excel Add-in... 9 FactSet - Excel Add-in... 13 Thomson Reuters Eikon - Excel Add-in... 19 Bloomberg - Excel Add-In Bloomberg

More information

ML for the Working Programmer

ML for the Working Programmer ML for the Working Programmer 2nd edition Lawrence C. Paulson University of Cambridge CAMBRIDGE UNIVERSITY PRESS CONTENTS Preface to the Second Edition Preface xiii xv 1 Standard ML 1 Functional Programming

More information

Information and Communication Technology Skills. QQI Level 4

Information and Communication Technology Skills. QQI Level 4 Information and Communication Technology Skills QQI Level 4 1 Table of Contents Introduction:... 3 Course Duration:... 3 Investment:... 4 Course Purpose:... 4 Who is it for?:... 4 Course Benefits:... 4

More information

MBA Jump Start Program

MBA Jump Start Program MBA Jump Start Program Module 2: Mathematics Thomas Gilbert Mathematics Module Online Appendix: Basic Mathematical Concepts 2 1 The Number Spectrum Generally we depict numbers increasing from left to right

More information

Table of Contents. Summary of Changes

Table of Contents. Summary of Changes SECTION 54 RENTAL PAYMENTS FOR SPACE AND LAND Table of Contents 54.1 Do I need to report on rental payments? 54.2 What materials must I provide? 54.3 What terms do I need to know? 54.4 How do I prepare

More information

ECE3281 Electronics Laboratory

ECE3281 Electronics Laboratory ECE328 Electronics Laboratory Experiment #4 TITLE: EXCLUSIVE-OR FUNCTIONS and INRY RITHMETIC OJECTIVE: Synthesize exclusive-or and the basic logic functions necessary for execution of binary arithmetic.

More information

IRA Pivot Table Review and Using Analyze to Modify Reports. For help, email Financial.Reports@dartmouth.edu

IRA Pivot Table Review and Using Analyze to Modify Reports. For help, email Financial.Reports@dartmouth.edu IRA Pivot Table Review and Using Analyze to Modify Reports 1 What is a Pivot Table? A pivot table takes rows of detailed data (such as the lines in a downloadable table) and summarizes them at a higher

More information

NURSING 1241 NURSING INFORMATICS TUTORIAL PORTFOLIO DEVELOPMENT (SPREADSHEET APPLICATION)

NURSING 1241 NURSING INFORMATICS TUTORIAL PORTFOLIO DEVELOPMENT (SPREADSHEET APPLICATION) NURSING 1241 NURSING INFORMATICS TUTORIAL PORTFOLIO DEVELOPMENT (SPREADSHEET APPLICATION) Nursing Informatics Integration Page 1 of 6 You are encouraged to create a comprehensive portfolio which normally

More information

Microsoft Office Word 2010: Level 1

Microsoft Office Word 2010: Level 1 Microsoft Office Word 2010: Level 1 Workshop Objectives: In this workshop, you will learn fundamental Word 2010 skills. You will start by getting acquainted with the Word user interface, creating a new

More information

Two's Complement Adder/Subtractor Lab L03

Two's Complement Adder/Subtractor Lab L03 Two's Complement Adder/Subtractor Lab L03 Introduction Computers are usually designed to perform indirect subtraction instead of direct subtraction. Adding -B to A is equivalent to subtracting B from A,

More information

Efficient and Robust Secure Aggregation of Encrypted Data in Wireless Sensor Networks

Efficient and Robust Secure Aggregation of Encrypted Data in Wireless Sensor Networks Efficient and Robust Secure Aggregation of Encrypted Data in Wireless Sensor Networks J. M. BAHI, C. GUYEUX, and A. MAKHOUL Computer Science Laboratory LIFC University of Franche-Comté Journée thématique

More information

Review Your Thesis or Dissertation

Review Your Thesis or Dissertation Review Your Thesis or Dissertation This document shows the formatting requirements for UBC theses. Theses must follow these guidelines in order to be accepted at the Faculty of Graduate and Postdoctoral

More information

The finite field with 2 elements The simplest finite field is

The finite field with 2 elements The simplest finite field is The finite field with 2 elements The simplest finite field is GF (2) = F 2 = {0, 1} = Z/2 It has addition and multiplication + and defined to be 0 + 0 = 0 0 + 1 = 1 1 + 0 = 1 1 + 1 = 0 0 0 = 0 0 1 = 0

More information

Analysis Design Coding Testing. Figure 3.1: Basic Waterfall Model

Analysis Design Coding Testing. Figure 3.1: Basic Waterfall Model Chapter 3 Research Methodology 3.1 Waterfall Model Information Engineering Analysis Design Coding Testing Figure 3.1: Basic Waterfall Model The Figure 3.1(Rosenbat, 1987) illustrates the basic waterfall

More information

4 Operations On Data

4 Operations On Data 4 Operations On Data 4.1 Source: Foundations of Computer Science Cengage Learning Objectives After studying this chapter, students should be able to: List the three categories of operations performed on

More information

Understanding Start-Up Costs

Understanding Start-Up Costs Understanding Start-Up Costs One of the many tasks you have to do when you plan to start any business is to calculate the initial costs involved in starting and operating your business. Almost every business

More information

Non-Redundant (RAID Level 0)

Non-Redundant (RAID Level 0) There are many types of RAID and some of the important ones are introduced below: Non-Redundant (RAID Level 0) A non-redundant disk array, or RAID level 0, has the lowest cost of any RAID organization

More information

MAT-71506 Program Verication: Exercises

MAT-71506 Program Verication: Exercises MAT-71506 Program Verication: Exercises Antero Kangas Tampere University of Technology Department of Mathematics September 11, 2014 Accomplishment Exercises are obligatory and probably the grades will

More information

Gouvernement du Québec Ministère de l Éducation, 2004 04-00811 ISBN 2-550-43541-9

Gouvernement du Québec Ministère de l Éducation, 2004 04-00811 ISBN 2-550-43541-9 Gouvernement du Québec Ministère de l Éducation, 2004 04-00811 ISBN 2-550-43541-9 Legal deposit Bibliothèque nationale du Québec, 2004 1. INTRODUCTION This Definition of the Domain for Summative Evaluation

More information

Data exploration with Microsoft Excel: univariate analysis

Data exploration with Microsoft Excel: univariate analysis Data exploration with Microsoft Excel: univariate analysis Contents 1 Introduction... 1 2 Exploring a variable s frequency distribution... 2 3 Calculating measures of central tendency... 16 4 Calculating

More information

MS Excel. Handout: Level 2. elearning Department. Copyright 2016 CMS e-learning Department. All Rights Reserved. Page 1 of 11

MS Excel. Handout: Level 2. elearning Department. Copyright 2016 CMS e-learning Department. All Rights Reserved. Page 1 of 11 MS Excel Handout: Level 2 elearning Department 2016 Page 1 of 11 Contents Excel Environment:... 3 To create a new blank workbook:...3 To insert text:...4 Cell addresses:...4 To save the workbook:... 5

More information

General Excel Instructions. Excel Instructions

General Excel Instructions. Excel Instructions Excel Instructions This is a general document designed to assist you with understanding the Excel functions (formulas) and how they work. The contents are: Entering Excel Formulas... 2 How Formulas Work...

More information

David Coufal 2 Institute of Computer Science Academy of Sciences of the Czech Republic Pod Vodarenskou vezi 2, 182 07 Prague 8, Czech Republic

David Coufal 2 Institute of Computer Science Academy of Sciences of the Czech Republic Pod Vodarenskou vezi 2, 182 07 Prague 8, Czech Republic V.012 SHORT TERM PREDICTION OF HIGHWAY TRAVEL TIME USING DATA MINING AND NEURO-FUZZY METHODS 1 David Coufal 2 Institute of Computer Science Academy of Sciences of the Czech Republic Pod Vodarenskou vezi

More information

= 2 + 1 2 2 = 3 4, Now assume that P (k) is true for some fixed k 2. This means that

= 2 + 1 2 2 = 3 4, Now assume that P (k) is true for some fixed k 2. This means that Instructions. Answer each of the questions on your own paper, and be sure to show your work so that partial credit can be adequately assessed. Credit will not be given for answers (even correct ones) without

More information

Chapter 2: Formulas, Functions, and Formatting Microsoft Excel 2010 OBJECTIVE We will practice using formulas and functions in Microsoft Excel 2010.

Chapter 2: Formulas, Functions, and Formatting Microsoft Excel 2010 OBJECTIVE We will practice using formulas and functions in Microsoft Excel 2010. OBJECTIVE We will practice using formulas and functions in. ESSENTIAL SKILLS Enter formulas by typing Enter formulas by Point mode Apply the AVERAGE, MAX, and MIN functions Verify a formula using Range

More information

Floating Point Fused Add-Subtract and Fused Dot-Product Units

Floating Point Fused Add-Subtract and Fused Dot-Product Units Floating Point Fused Add-Subtract and Fused Dot-Product Units S. Kishor [1], S. P. Prakash [2] PG Scholar (VLSI DESIGN), Department of ECE Bannari Amman Institute of Technology, Sathyamangalam, Tamil Nadu,

More information

Cryptography and Network Security. Prof. D. Mukhopadhyay. Department of Computer Science and Engineering. Indian Institute of Technology, Kharagpur

Cryptography and Network Security. Prof. D. Mukhopadhyay. Department of Computer Science and Engineering. Indian Institute of Technology, Kharagpur Cryptography and Network Security Prof. D. Mukhopadhyay Department of Computer Science and Engineering Indian Institute of Technology, Kharagpur Module No. # 01 Lecture No. # 12 Block Cipher Standards

More information

3.Basic Gate Combinations

3.Basic Gate Combinations 3.Basic Gate Combinations 3.1 TTL NAND Gate In logic circuits transistors play the role of switches. For those in the TTL gate the conducting state (on) occurs when the baseemmiter signal is high, and

More information

SCHOOLOFCOMPUTERSTUDIES RESEARCHREPORTSERIES UniversityofLeeds Report95.23. AutomaticDetectionofKeySignature usingnotedistribution

SCHOOLOFCOMPUTERSTUDIES RESEARCHREPORTSERIES UniversityofLeeds Report95.23. AutomaticDetectionofKeySignature usingnotedistribution SCHOOLOFCOMPUTERSTUDIES RESEARCHREPORTSERIES UniversityofLeeds Report95.23 AutomaticDetectionofKeySignature usingnotedistribution DivisionofArticialIntelligence,SchoolofComputerStudies K.C.Ng,R.D.Boyle&D.Coopery

More information

Secret File Sharing Techniques using AES algorithm. C. Navya Latha 200201066 Garima Agarwal 200305032 Anila Kumar GVN 200305002

Secret File Sharing Techniques using AES algorithm. C. Navya Latha 200201066 Garima Agarwal 200305032 Anila Kumar GVN 200305002 Secret File Sharing Techniques using AES algorithm C. Navya Latha 200201066 Garima Agarwal 200305032 Anila Kumar GVN 200305002 1. Feature Overview The Advanced Encryption Standard (AES) feature adds support

More information

L1-2. Special Matrix Operations: Permutations, Transpose, Inverse, Augmentation 12 Aug 2014

L1-2. Special Matrix Operations: Permutations, Transpose, Inverse, Augmentation 12 Aug 2014 L1-2. Special Matrix Operations: Permutations, Transpose, Inverse, Augmentation 12 Aug 2014 Unfortunately, no one can be told what the Matrix is. You have to see it for yourself. -- Morpheus Primary concepts:

More information

l What have discussed up until now & why: l C Programming language l More low-level then Java. l Better idea about what s really going on.

l What have discussed up until now & why: l C Programming language l More low-level then Java. l Better idea about what s really going on. CS211 Computer Architecture l Topics Digital Logic l Transistors (Design & Types) l Logic Gates l Combinational Circuits l K-Maps Class Checkpoint l What have discussed up until now & why: l C Programming

More information

Method for Multiplier Verication Employing Boolean Equivalence Checking and Arithmetic Bit Level Description

Method for Multiplier Verication Employing Boolean Equivalence Checking and Arithmetic Bit Level Description Method for Multiplier Verication Employing Boolean ing and Arithmetic Bit Level Description U. Krautz 1, M. Wedler 1, W. Kunz 1 & K. Weber 2, C. Jacobi 2, M. Panz 2 1 University of Kaiserslautern - Germany

More information

Excel Spreadsheet Activity Redo #1

Excel Spreadsheet Activity Redo #1 Excel Spreadsheet Activity Redo #1 Melissa Ebling 11/9/06 Directions: Please follow all directions in this packet. This assignment will consist of your tracking ten different stocks over a period of a

More information

Overview What is a PivotTable? Benefits

Overview What is a PivotTable? Benefits Overview What is a PivotTable? Benefits Create a PivotTable Select Row & Column labels & Values Filtering & Sorting Calculations Data Details Refresh Data Design options Create a PivotChart Slicers Charts

More information

New Method to Calculate Determinants of n n(n 3) Matrix, by Reducing Determinants to 2nd Order

New Method to Calculate Determinants of n n(n 3) Matrix, by Reducing Determinants to 2nd Order International Journal of Algebra, Vol 6, 202, no 9, 93-97 New Method to Calculate Determinants of n n(n 3) Matrix, by Reducing Determinants to 2nd Order Armend Salihu Department of Telecommunication, Faculty

More information

SAMPLE COURSE OUTLINE APPLIED INFORMATION TECHNOLOGY FOUNDATION YEAR 12

SAMPLE COURSE OUTLINE APPLIED INFORMATION TECHNOLOGY FOUNDATION YEAR 12 SAMPLE COURSE OUTLINE APPLIED INFORMATION TECHNOLOGY FOUNDATION YEAR 12 Copyright School Curriculum and Standards Authority, 2015 This document apart from any third party copyright material contained in

More information

Outline. Systems and Signals 214 / 244 & Energy Systems 244 / 344. Ideal Inductor. Ideal Inductor (cont... )

Outline. Systems and Signals 214 / 244 & Energy Systems 244 / 344. Ideal Inductor. Ideal Inductor (cont... ) Outline Systems and Signals 214 / 244 & Energy Systems 244 / 344 Inductance, Leakage Inductance, Mutual Inductance & Transformers 1 Inductor revision Ideal Inductor Non-Ideal Inductor Dr. P.J. Randewijk

More information

1.2. Successive Differences

1.2. Successive Differences 1. An Application of Inductive Reasoning: Number Patterns In the previous section we introduced inductive reasoning, and we showed how it can be applied in predicting what comes next in a list of numbers

More information

CSI 333 Lecture 1 Number Systems

CSI 333 Lecture 1 Number Systems CSI 333 Lecture 1 Number Systems 1 1 / 23 Basics of Number Systems Ref: Appendix C of Deitel & Deitel. Weighted Positional Notation: 192 = 2 10 0 + 9 10 1 + 1 10 2 General: Digit sequence : d n 1 d n 2...

More information

Symbolic Logic on the TI-92

Symbolic Logic on the TI-92 Symbolic Logic on the TI-92 Presented by Lin McMullin The Sixth Conference on the Teaching of Mathematics June 20 & 21, 1997 Milwaukee, Wisconsin 1 Lin McMullin Mathematics Department Representative, Burnt

More information

Candle Plant process automation based on ABB 800xA Distributed Control Systems

Candle Plant process automation based on ABB 800xA Distributed Control Systems Candle Plant process automation based on ABB 800xA Distributed Control Systems Yousef Iskandarani and Karina Nohammer Department of Engineering University of Agder Jon Lilletuns vei 9, 4879 Grimstad Norway

More information