SDR Software Defined Radio

Transcription

1 SDR Software Defined Radio DSP Vladimir Poučki S.P., Slovenia 1

2 Presentation Outline What is SDR? Role of FPGAs in SDR SDR in Mobile Base Station SDR for Particle Accelerators CIC filters Digital Pre-Distortion My 2 cents 2

3 What is SDR? SDR is, in a very strict definition, radio communication system implemented in software in embedded system (this includes FPGA). My personal view is broader. SDR are all hard real-time embedded systems that process limited bandwidth signals residing in radio frequency spectrum. 3

4 What is SDR? 4

5 What is SDR? DDC Digital Down Converter. First processing block that performs low-pass filtering and decimation; RX direction. DUC Digital Up Converter. Last processing block that performs low-pass filtering and interpolation; TX direction. 5

6 What is SDR? DDC Digital Down Converter. First processing block that performs low-pass filtering and decimation; RX direction. DUC Digital Up Converter. Last processing block that performs low-pass filtering and interpolation; TX direction. 6

7 Role of FPGAs in SDR Inputs are ADC sampling from couple of 10s MHz to couple of 100s MHz. First data processing is always done at the highest = sampling rate of ADC. Amount of data is huge (~200 Msamples/s). After first signal conditioning, decimation is the first block. 7

8 Role of FPGAs in SDR At the highest rate there is no possibility for sophisticated LowPass (LP) filter; this a prerequisite for decimation. Usual solution is using CIC filter or Halfband filters. Then one or more decimation stages. Generation of I,Q components. 8

9 Role of FPGAs in SDR Multiplication with LO generated sine/cos, plus filtering. Finally, signal is in base band, or at low multiple of base band spectrum. Additional filtering and conditioning. Some AGC (Automatic Gain Control). 9

10 Role of FPGAs in SDR Baseband signal is then transferred to DSP Processor for further processing. FPGA processing starts at ~ MHz, ends up at usually ~Nx100kHz or Nx1MHz. This DSP processing is not too complex. But, it takes a lot of knowledge to implement it properly. 10

11 SDR in Mobile Base Station 2G, 3G and 4G (LTE). 2G is far more complex for FPGA implementation. Reasons: - 200kHz Nx100 MHz sampling rate. - Many disturbance effects from neighboring channels. - Relatively high dynamic range, high amplitudes. 11

12 SDR in Mobile Base Station 3G and 4G (LTE). 3G (from FPGA processing point of view) is almost the same as 4G. 4G has higher bandwidth. Only difference is in the last stages of decimation. 12

13 SDR in Mobile Base Station Power level of the signal is below noise level. Excellent AGC is required to track power level in real-time, on a slot basis; otherwise one EndUser (mobile phone) communication would kill the whole channel. 13

14 SDR in Mobile Base Station Processing technologies used are: - Half-band and CIC filters for first stages of decimation - Rational factor of decimation; this is conditioned with sampling rates and adjusting the processing to different technologies (2-4 G). - Highly tuned decimation with FIR compilers. Standard FIR filters. 14

15 SDR in Mobile Base Station Processing technologies used are: - Complex multi-stage multi-rate filters. Very hard to be designed and simulated in Matlab. - Complicated clock domain crossings. - Highly efficient rational decimation. - Complex multipliers for handling frequency multiplication to baseband. 15

16 SDR in Mobile Base Station Simulations in Matlab are complex and long lasting. It is not possible really to simulate everything perfectly, so numerous approximations are included. Multiplexing of numerous channels to single signal (serializing) for resource saving => really hard to implement in FPGA. 16

17 SDR in Mobile Base Station Business with extreme competition; even 0.1 or 0.2 db means a lot. New features can be added with careful design of numerous filters. 17

18 SDR for Particle Accelerators Big circular high physics machines. Electrons are circling at ~ speed of light in vacuum. Usually the RF frequency is around 499 MHz. Revolution frequency is always equal to RF frequency divided by integer; from ~100kHz to 15 MHz. FPGA processing is deployed from RF to revolution; very similar to real wireless SDR. 18

19 SDR for Particle Accelerators Undersampling technique! For the bandwidth limited signal, you need to sample (per Nyquist) with frequency two times higher than the highest component bandwidth! It does not matter where the signal really is in the spectrum. 19

20 SDR for Particle Accelerators Usual undersampling frequency were ~120 MHz. So, 4 th harmonic of sampling frequency (of ADC) was actually sampling the 500 MHz signal. First implementation on old Virtex-II Xilinx devices. Max speed ~130 MHz, low on resources, simple multipliers. 20

21 SDR for Particle Accelerators The following filters and decimation structures were used: - Multiplierless band-pass IIR filters (@ ADC rate) - Sort of Moving Average (MA) and decimation block (output revolution rate) - CIC filtering, Polyphase FIR filtering ~15 khz rate) - Notch filters - One more CIC stage. ~10 Hz rate). 21

22 SDR for Particle Accelerators Multiplierless band-pass IIR filters 22

23 SDR for Particle Accelerators 4 input channels I,Q times 4 channels => 8 processing channels => high resource consumption. Starting with revolution rate, resource sharing techniques are used. Single circuit does multiple calculations for all 8 channels: hardware folding, time multiplexing... 23

24 SDR for Particle Accelerators Each Particle Accelerator has different parameters => customized SDR for each. Engine for generation of Verilog code. Sophisticated Matlab scripts for generation of filter coefficients to always maintain the same quality of filtering. Automated simulations and level checks in Modelsim. Close to 100 different SDR designed. 1 SDR = 1 DAY OF WORK!!! 24

25 25 CIC Cascaded Integrated Comb filter Integrators and comb filter pairs. Interpolator or decimator. Exists ONLY IN FIXED-POINT ARITHMETIC. For Matlab implementation, developer must use fixed-point objects. It is important to make really optimal implementation, since the number of bits for adders and registers can easily go as high as 70 bits.

26 CIC Cascaded Integrated Comb filter Bible on understanding CIC filters: fred harris: Multirate Signal Processing for Communication Systems Each section has a 13dB attenuation. N sections => Nx13dB. -13dB is the maximum side-lobe level. Gain must be properly calculated and applied. 26

27 DPD Digital Pre-Distortion Digital Pre-Distortion, increase efficiency of output (TX) Power Amplifiers. Amplifier characterization, for Type1: curve of the amplitude transfer function. AM-AM, AM-PM distortion. 27

28 DPD Digital Pre-Distortion Type 2 distortion, memory effect, is the function of signal bandwidth. Waveform spectrum used for characterization of Type 2 Magnitude and phase of Type 2 distortion. 28

29 DPD Digital Pre-Distortion Solution is in the model. 3G and 4G pushed for even higher peak-to-average ratio => Doherty amplifier. Model for DPD correction - FPGA 29 IMPROVEMENTS!!!

30 My 2 cents Variable gain SAW analog filters. Xilinx Zynq family: FPGA + ARM core. Latest trends in mobile base stations: integration of WiFi with 2G,3G and 4G. 30

31 THANK YOU! HVALA! 31