Foundations of Computing and Communication Lecture 7. The von Neumann Architecture

Transcription

1 Foundations of Computing and Communication Lecture 7 The von Neumann Architecture Based on The Foundations of Computing and the Information Technology Age, Chapter 6 Lecture overheads c John Thornton 2007

2 Lecture Objective To gain a practical understanding of how a program executes within the von Neumann architecture. Overview of Topics The von Neumann Architecture The Fetch-Execute Cycle Set Architectures Basic Program s Executing a Simple Program The Evolution of the von Neumann Architecture 1

3 The von Neumann Architecture The architecture that underpins the operation of a modern computer still adheres to a structure put forward by John von Neumann (and John Mauchly and Presper Eckert) in This structure separates the internal operation of a computer into two basic logical components: the central processing unit (CPU) and memory. Control Unit Input Memory CPU Arithmetic and Logic Unit Output 2

4 General Purpose Memory It s all data! The revolutionary idea behind the architecture was that data and program instructions were both to be stored in the same format within the same internal memory devices (like universal Turing machine tape). This only became practical with the development of high speed electronic memory after WWII. The stored program concept: In this way programs were to be stored within the computer rather than being accessed from a separate location during runtime. The programmer has control: Because there is no physical distinction between data and program instructions it is the role of the programmer to ensure that memory locations are correctly read, interpreted and written to. 3

5 Digital Synchronism The von Neumann bottleneck: Given input devices from which data can be loaded into memory and output devices to store and display results, the focus of the von Neumann architecture is the passage of data back and forth between memory and the CPU. The importance of the clock: To work correctly this passage of data has to be rigidly synchronised via the control of a system clock. Digital states: The system clock enforces a sufficient gap for the machine to move from one state to another. Hence components must wait until all other relevant processes have moved to a new state before starting the next computation. 4

6 The Fetch-Execute Cycle The process of moving from one state to another according to the ticking of a system clock is known as the fetch-execute cycle. In the fetch step, the CPU control unit fetches an instruction from memory and stores it in an instruction register. In the execute step, the instruction triggers processes that change the values in the CPU data registers. The next instruction is then fetched and the cycle repeats. Addressable memory: The emphasis on always moving data back and forth from memory means the CPU must be able to access memory as fast as possible via direct addressing, i.e. by having a key value that can directly unlock a memory location without having to perform a search. 5

7 The Fetch-Execute Cycle Central Processing Unit Fetch Registers Execute Memory Control Unit Pointer Data Data Data Data ALU 6

8 Inside the CPU The Pointer Register is used by the control unit to fetch the next instruction - it holds the memory address of an instruction and is automatically updated after each fetch to point to the address of the next instruction. Control Unit s take care of loading and storing data back and forth from memory, updating the pointer register and halting the program execution. Arithmetic and Logic Unit s perform the arithmetic and logical transformations on the data stored in the data registers. 7

9 The Turing Machine Analogy Just as a Turing machine reads a symbol from a tape and, according to that symbol and its internal state, writes another symbol, changes state and moves the tape, a von Neumann machine reads a symbol string from memory and according to the value of that string and the current state of its registers, writes another string to memory, changes the state of its registers and moves to read another memory location. Turing machine tape Memory; Turing machine rules CPU circuits; Direction of tape movement Pointer register; Current and next states register; Current symbol Data copied from memory to data registers; Next symbol Data copied from data registers to memory. 8

10 It Could Have Been Different... Serial processing: Both the Turing and von Neumann machines enforce that one thing must be done after another in strict sequence. The power of the modern computer has come from performing the von Neumann fetch-execute cycle with enormous speed. The self-timing systems of nature: Nature manages to perform far more sophisticated calculations by using massively parallel, asynchronous systems. Instead of doing one thing over and over with great speed, a brain does millions of things at once relatively slowly. Mathematical roots: von Neumann chose a sequential digital architecture because it is simpler to build and works well for the kinds of mathematical problems that faced the US military in

11 Set Architectures The connection between instructions and processors: Unlike the five elements of a Turing machine instruction, the form of a von Neumann machine s instruction set is not fixed and thereby helps define the processor architecture. Op-codes and operands: typically an instruction is divided into an op-code that represents an operation and zero to many operands on which the operation is to be performed: op-code operand 1 operand 2 operand

12 An Language Formal Languages: the choice of an instruction set and the form in which the set is encoded defines a formal language. A two-state alphabet: the standard alphabet of a modern machine language takes the form of two states: {0,1}. This choice is based on the practical need to efficiently represent and manipulate states as electrical charges. Boolean algebra represents a formal language suitable for manipulating a two state alphabet using a remarkably small set of primary logical operations: AND, OR and NOT 11

13 The Three Primary Logical s AND OR NOT 0 AND 0 = 0 0 OR 0 = 0 NOT 0 = 1 0 AND 1 = 0 0 OR 1 = 1 NOT 1 = 0 1 AND 0 = 0 1 OR 0 = 1 1 AND 1 = 1 1 OR 1 = AND OR NOT

14 Combining Operators All other logical operations can be expressed using a combination of the AND, OR and NOT operators, for example: A XOR B = (A AND NOT(B)) OR (NOT(A) AND B) XOR 0 XOR 0 = 0 0 XOR 1 = 1 1 XOR 0 = 1 1 XOR 1 = XOR

15 The Logic of Addition ADD = = = = 10 Dividing each result above into a leading and trailing bit shows that the trailing bit (T) is only on when the original bits are different (i.e. when = 01 or = 01). Hence we can decide the value of the trailing bit using an XOR operation. Similarly, the leading bit (L) in the answer is only on when both the original bits are also on (i.e. when = 10). Hence we can decide the value of the leading bit using an AND operation. 14

16 The Logic of Addition Representing the two bits to be added as A and B, the leading result bit as L and the trailing result bit as T, gives: A + B = LT where L = A AND B T = A XOR B To handle multiple bit numbers we also need to add the carry bit arriving from the previous column to the right. We can achieve this by adding this carry in bit (C in ) to the trailing bit of our first addition, as follows: T + C in = CS where C = T AND C in S = T XOR C in 15

17 The Logic of Addition We now need to combine the carry out information into a single bit that can be passed to the next column. This bit should be on if either of the additions produced a carry, i.e: C out = C OR L Given input bits: A, B and C in, and output bits: S and C out, where A and B are the bits that line up in column n of our original pair of binary numbers, C in is the value of the carry in bit arriving from column n 1, S is the resulting bit sum for column n and C out is the carry out bit to be sent to column n + 1, we can perform a complete column addition as follows: S = (A XOR B) XOR C in C out = ((A XOR B) AND C in ) OR (A AND B) 16

18 More Complex s General addition: By combining binary column adders we can add together binary numbers of arbitrary size. The instruction set: Our instruction set now consists of 5 operations: AND, OR, NOT, XOR and ADD Subtraction: To subtract two binary numbers we can use the same complement method Pascal used for his calculator. For a binary number, two s complement is found by subtracting each digit from one (using NOT) and adding one: ADD(NOT(A), 0001) 17

19 Subtraction Subtraction is achieved by adding the two s complement of the number you wish to subtract and discarding the final carry bit. For example, to subtract 7 3: = = ADD(0111, ADD(NOT(0011), 0001)) = ADD(0111, ADD(1100, 0001)) = ADD(0111, 1101) = 0100 Here the answer 0100 is given after removing the carry bit (i.e. the full answer is 10100). If the leading bit of this truncated string is one then the string represents a two s complement negative number, otherwise it represents a normal positive number. 18

20 Shifting If we take a bit string to be a binary number then the SHIFT operator has the same effect as moving the decimal point in a base ten number. So moving a binary point left in a base two number is equivalent to dividing by two. Similarly, a left shift will move the binary point to the right and is equivalent to multiplying by two. 0 zero bit shifted in leading bits shifted out Right Shift +1 bit Left Shift 2 bits trailing bit shifted out zero bits shifted in x

21 Control Unit s The LOAD and STORE instructions control the the movement of data between memory and the CPU data registers. The conditional BRANCH instruction tests a condition (such as whether or not a register holds a non-zero value) and, if the condition is met, it overrides the fixed update of the program counter and places a new address in the pointer register. This allows the flow of program control to jump anywhere in memory. The HALT instruction terminates a program and switches the computer off. 20

22 Sequence, Selection and Iteration Selection and iteration: A conditional BRANCH allows selection (if) and iteration (do while). Sequence: Everything else sequentially follows fetch and execute instructions that copy data and perform simple logical transformations until the program halts. Input and Output: I/O devices can be accessed and controlled by reading and writing data to reserved memory locations. Another universal language: That s it! All programming, hence all effective procedures can be captured by the simple set of instructions we have described. 21

23 A von Neumann Machine Programming Language AND register address register address register address * * * * * * * * * * * * OR register address register address register address * * * * * * * * * * * * XOR register address register address register address * * * * * * * * * * * * ADD register address register address register address * * * * * * * * * * * * LOAD register address memory address * * * * * * * * * * * * STORE register address memory address * * * * * * * * * * * * BRANCH register address memory address * * * * * * * * * * * * NOT register address register address unused * * * * * * * * SHIFT register address register address unused * * * * * * * * HALT unused 22

24 A Simple Programming Problem A university subject convenor has decided to give out bonus marks to students who have unusual and original ideas. These marks accrue in addition to the marks given for the regular assignments and make it possible for a student to score more than 100% for the overall subject. Unfortunately, the university s final grading system is not very flexible and if it finds a student with more than 100% it assumes an error has occurred and the subject convenor must explain what has happened. To avoid this situation we need to write a program that checks a student s final mark and makes sure anyone getting more than 100% has their final mark reduced back to 100%. In programming terms, we can express the problem as follows: If an overall mark is greater than 100 then set the overall mark to

25 The Solution 1 LOAD register-3-address value-one-address load value 1 in register 3 2 LOAD register-2-address value-one-hundred-address load value 100 in register 2 3 LOAD register-1-address value-seven-address load value 7 in register 1 4 LOAD register-0-address mark-address load mark M in register 0 5 NOT register-0-address register-0-address unused negate M and store as M in register 0 6 ADD register-0-address register-3-address register-0-address store M + 1 as M in register 0 7 ADD register-0-address register-2-address register-0-address store -M as in register 0 8 SHIFT register-0-address register-1-address unused right shift by 7 to isolate sign bit B 9 BRANCH register-0-address halt-address branch to HALT if B is zero 10 STORE register-2-address mark-address store mark = back to memory 11 HALT unused terminate program

26 1: LOAD value one into register 3 Central Processing Unit Memory Control Unit Fetch Increment Pointer LOAD Pointer Data Data Data Data ALU 25

27 2: LOAD value one hundred into register 2 Central Processing Unit Memory Control Unit Fetch Increment Pointer LOAD Pointer Data Data Data Data ALU 26

28 3: LOAD value seven into register 1 Central Processing Unit Memory Control Unit Fetch Increment Pointer LOAD Pointer Data Data Data Data ALU 27

29 4: LOAD mark into register 0 Memory Control Unit Fetch Increment Pointer LOAD Central Processing Unit Pointer Data Data Data Data ALU 28

30 5: NOT register 0 = not(register 0) Central Processing Unit Memory Control Unit Fetch Increment Pointer Pointer Data Data Data Data ALU Decode NOT Save Result 29

31 6: ADD register 0 = register 0 + register 3 Central Processing Unit Memory Control Unit Fetch Increment Pointer 3 Pointer Data Data Data Data ALU Decode ADD Save Result 30

32 7: ADD register 0 = register 0 + register 2 Central Processing Unit Memory Control Unit Fetch Increment Pointer 3 Pointer Data Data Data Data ALU Decode ADD Save Result 31

33 8: SHIFT register 0 by register 1 bits Central Processing Unit Memory Control Unit Fetch Increment Pointer 3 Pointer Data Data Data Data ALU Decode SHIFT Save Result 32

34 9: BRANCH to halt address if register 0 is zero Central Processing Unit Memory Control Unit Fetch Increment Pointer BRANCH Pointer Data Data Data Data ALU 33

35 10: STORE mark = register 2 Central Processing Unit Memory Control Unit Fetch Increment Pointer STORE Pointer Data Data Data Data ALU 34

36 11: HALT Central Processing Unit Memory Control Unit Fetch HALT 3 1 Pointer Data Data Data Data ALU 35

37 The Evolution of the von Neumann Architecture Most modern PCs use a bus architecture to connect different system components to the CPU. Still adheres to von Neumann s basic functional design and still suffers from von Neumann s bottleneck. Parallel processing architectures alleviate the bottleneck by multiplying processors - but each processor is still uses the fetchexecute paradigm. Memory CPU Control Registers Unit ALU System Bus Hard Disk Monitor Keyboard 36

38 Lecture Exercise Using the Set Architecture (ISA) described in the lecture, devise a program to solve the following problem: the Global Regulated Economic Efficiency Development Bank offers loan accounts to farmers in underdeveloped areas. Every month the bank checks its accounts to decide if an account keeping fee should be charged. It uses the following rule: if an account balance is less than or equal US$25 then charge the account a US$5 fee, otherwise leave the account balance unchanged. You should write each instruction as a 16 bit binary number that specifies the necessary register and memory addresses and diagrammatically show how the program and data would be represented in memory. 37