ECE Advanced Digital Systems Lab 2 ALU Arithmetic Logic Unit. September 29, 2012

Transcription

1 ECE Advanced Digital Systems Lab 2 ALU Arithmetic Logic Unit September 29,

2 1 Functional Description 1.1 Introduction The objective of lab 2 is to design and develop a ALU using the DE2 115 development board. The ALU subsystem performs all the arithmetic operations of a microprocessor. The block diagram of the ALU in this lab is shown in Fig. 1. The ALU takes takes two sixteen bit inputs (SA[15..0] and SB[15..0]) and performs an arithmetic operation on them based on the value of the OPERA- TIONS[2..0] input. The ALU drives the tri state result bus R[15..0] with the results of the arithmetic operation. SA[15..0] Arithmetic Logic Unit SB[15..0] R[15..0] Op-Codes [2..0] Figure 1: Top Level of ALU 1.2 Inputs Table 1: Inputs to the ALU system Input Description SA[15..0] Provides one 16 bit operand to the ALU SB[15..0] Provides one 16 bit operand to the ALU Operation [2..0] Operations[2..0] selects one of the possible arithmetic operations available to the ALU. Table 2: ALU Operations Value (OP code) Action 0 R = A + B ( Addition) 1 R = A - B (Subtraction) 2 R = A (Complement) 3 R = A B (Shift A left by B bits, filled with 0 ; B 7 4 R = A B (Shift A right by B bits, filled with 0 ; B 7 5 R = A B (XOR) 6 R = A B (Logical OR) 7 R = A B ( Logical AND) 1.3 Outputs 2

3 Table 3: ALU Outputs Output Description R[15..0] 16 bit output bus of the ALU. Should connect to the Hex displays 2 Implementation The following tables will define the pins used in this lab. All 18 switches, Table 4, will be used along with 2 push buttons, 1 clock, Table 5, and 4 seven segment displays, Table 6. Additional information on the I/O ports can be found in the DE2 115 User Guide posted on the course website. Table 4: Switch Locations Switch FPGA Pin SW[0] SW[1] SW[2] SW[3] SW[4] PIN AB28 PIN AC28 PIN AC27 PIN AD27 PIN AB27 SW[5] PIN AC26 SW[6] PIN AD26 SW[7] PIN AB26 SW[8] PIN AC25 SW[9] PIN AB25 SW[10] PIN AC23 Table 5: Push Button and Clock Locations Switch FPGA Pin Key[0] Key[1] CLK PIN M23 PIN M21 PIN AG14 SW[11] PIN AB24 SW[12] PIN AB23 SW[13] PIN AA24 SW[14] PIN AA23 SW[15] PIN AA22 SW[16] PIN Y24 SW[17] PIN Y23 3

4 Table 6: Hex Display Locations: Hex 3 is the left most display Display FPGA Pin Hex0[0] PIN G18 Hex0[1] PIN F22 Hex0[2] PIN E17 Hex0[3] PIN L26 Hex0[4] PIN L25 Hex0[5] PIN J22 Hex0[6] PIN H22 Hex1[0] PIN M24 Hex1[1] PIN Y22 Hex1[2] PIN W21 Hex1[3] PIN W22 Hex1[4] PIN W25 Hex1[5] PIN U23 Hex1[6] PIN U24 Hex2[0] PIN AA25 Hex2[1] PIN AA26 Hex2[2] PIN Y25 Hex2[3] PIN W26 Hex2[4] PIN Y26 Hex2[5] PIN W27 Hex2[6] PIN W28 Hex3[0] PIN V21 Hex3[1] PIN U21 Hex3[2] PIN AB20 Hex3[3] PIN AA21 Hex3[4] PIN AD24 Hex3[5] PIN AF23 Hex3[6] PIN Y19 4

5 3 Operation The data will be entered using the first 16 switches (SW0 to SW15). Due to the limited amount of switches available on the DE2 115, each input to the ALU has to be entered separately and stored in two 16 bit registers. A clock signal is required for the registers. The values of the registers are loaded 16 bits at a time using the push buttons ( e.g., set the 16 switches to the number you want than press the appropriate push button to store the data). It should be noted that the push buttons are active low therefore a NOT Gate should be used at the output of the push button pin to before connecting to the registers. The OP Codes are controlled by 3 switches (SW0 to SW2). These switches are available at all times except when the push buttons are pressed causing the switches to be used as data input instead. Table 8 indicates the complete op codes using the switches and their description. Table 7: ALU OP Code Switch Locations SW[2] SW[1] SW[0] Description R = A + B ( Addition) R = A - B (Subtraction) R = A (Complement) R = A B (Shift A left by B bits, filled with 0 ; B R = A B (Shift A right by B bits, filled with 0 ; B R = A B (XOR) R = A B (Logical OR) R = A B ( Logical AND) The outputs of the ALU (R[15..0]) and registers (SA[15..0], SB[15..0] are to be displayed on the four Hex displays, where HEX 3 represents the left most display. For this purpose the code converter from Lab 1 is required (bintohex). The switches SW16 and SW17 are used to determine which output is to be displayed. Table 8 describes the switch operations to achieve this. Table 8: ALU OP Code Switch Locations SW[17] SW[16] Description 0 0 Display the ALU output R[15..0] 0 1 Display the register output SA[15..0] 1 0 Display the register output SB[15..0] 1 1 Don t Care 4 Testing Develop the above ALU and testing circuit using schematic capture and VHDL methods. The system should be fully tested on the DE2 115 development board. To receive full marks every function must work correctly. Hint: It is recommended that the MegaWizard Plug In manager be used as much as possible to generate commonly used sub blocks, such as adders, counters, shifters, registers, Mux, etc. 5

6 5 Deliverables A report should be completed for this lab and include any schematics and code used, as well as how the overall structure is implemented. The functions should be demoed to the TA during the second lab session during this lab. 6