Canon Mp CMOS Image Sensor from the Canon EOS 50D 15.1 Mp DSLR Camera 0.5 µm CMOS Process

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Willis Chambers
7 years ago
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1 Mp CMOS Image Sensor from the Canon EOS 50D 15.1 Mp DSLR Camera 0.5 µm CMOS Process Imager Process Review For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor and electronics technology, please call Sales at Chipworks Richmond Road, Suite 500, Ottawa, ON K2H 5B7, Canada Tel: Fax:

2 Imager Process Review Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Company Profile 1.4 Introduction 1.5 Device Summary 1.6 Process Summary 2 Device Overview 2.1 Downstream Product, Package, and Die 2.2 Die Features 3 Process Analysis 3.1 General Device Structure 3.2 Bond Pads 3.3 Dielectrics 3.4 Metallization 3.5 Vias and Contacts 3.6 MOS Transistors and Poly 3.7 Isolation 3.8 Wells and Substrate 4 Pixel Analysis 4.1 Pixel Overview and Schematic 4.2 Pixel Plan-View Analysis 4.3 Pixel Array Cross Section (Parallel to Row Select Line) 4.4 Pixel Array Cross Section (Parallel to Column Out Line) 5 Critical Dimensions 6 References 7 Statement of Measurement Uncertainty and Scope Variation Report Evaluation

3 Overview Overview 1.1 List of Figures 2 Device Overview Canon EOS 50D Front Canon EOS 50D Back Canon EOS 50D Top Canon EOS 50D Bottom Canon EOS 50D Main Board Front Canon EOS 50D Main Board Back Canon EOS 50D Image Sensor Assembly Front Canon EOS 50D Image Sensor Assembly Back Package Front Package Back Die Photograph Metal 1 Die Photograph Die Corner A Die Corner B Die Corner C Die Corner D Green Filter Alignment Marks Alignment Marks Lower Left Array Corner Upper Right Array Corner Pixel Array at Corner Bond Pad 3 Process Analysis General Structure Die Edge Die Edge and Seal Bond Pad in Tilt View Bond Pad Edge Passivation and IMD IMD and Pre-Metal Dielectric Minimum Pitch Metal Minimum Pitch Peripheral Metal TEM Metal Minimum Pitch Peripheral Metal Minimum Pitch Pixel Array Metal TEM Metal 1 in Pixel Array Via Minimum Pitch Via 1s and Contacts Peripheral Transistor Layout Peripheral NMOS Transistor Peripheral PMOS Transistor

4 Overview TEM Minimum Gate Length Peripheral Transistor TEM Left Sidewall Spacer TEM Peripheral Transistor Gate Oxide Minimum Width Isolation Poly Over Isolation Pixel Array and Column Out at Diffusion SCM of Pixel Array Well Structure SRP Pixel Array P-Well SRP Peripheral P-Well SRP Peripheral Embedded P-Well SRP Peripheral N-Well 4 Pixel Analysis Pixel Schematic Microlenses and RGB Color Filter Array Microlenses Microlenses in Tilt View Color Filters Pixel at Metal Pixel at Metal Pixel at Metal Pixel at Poly Pixel at Diffusion Bevel SCM of Buried Photocathode Planes of Cross-Sectioning Pixel Near Left Edge of Array Pixel Near Array Center Blue Filter Green Pixel Dielectric Stack and Metallization TEM Green Filter and Lens Photocathode SCM Photocathode Transfer Gate (T1/T2) TEM Transfer Transistor TEM Left Edge Transfer Gate TEM Silicon Nitride AR Layer TEM Transfer Gate Oxide Source Follower (T4) and Row Select (T5) Transistors Reset Transistor (T3) Dark Pixels Red and Green Pixels Silicon Nitride A/R Layer Over Photocathode Reset Transistor (T3) Gate Width Source Follower (T4) Gate Width Row Select Transistor (T5) Gate Width

5 Overview List of Tables 1 Overview Device Identification Device Summary Process Summary 2 Device Overview Die and Bond Pad Dimensions 3 Process Analysis Measured Dielectric Thicknesses Metallization Thicknesses Metallization Width and Pitch Via and Contact Dimensions Peripheral MOS Transistor and Poly Dimensions LOCOS Critical Dimensions Well Depths and Die Thickness 4 Pixel Analysis Pixel Horizontal Dimensions Pixel Transistor Dimensions Pixel Vertical Dimensions 5 Critical Dimensions Die and Bond Pad Dimensions Measured Dielectric Thicknesses Metallization Thicknesses Metallization Width and Pitch Via and Contact Dimensions Peripheral MOS Transistor and Poly Dimensions Well Depths and Die Thickness LOCOS Critical Dimensions Pixel Horizontal Dimensions Pixel Transistor Dimensions Pixel Vertical Dimensions

6 About Chipworks Chipworks is the recognized leader in reverse engineering and patent infringement analysis of semiconductors and electronic systems. The company s ability to analyze the circuitry and physical composition of these systems makes them a key partner in the success of the world s largest semiconductor and microelectronics companies. Intellectual property groups and their legal counsel trust Chipworks for success in patent licensing and litigation earning hundreds of millions of dollars in patent licenses, and saving as much in royalty payments. Research & Development and Product Management rely on Chipworks for success in new product design and launch, saving hundreds of millions of dollars in design, and earning even more through superior product design and faster launches. Contact Chipworks To find out more information on this report, or any other reports in our library, please contact Chipworks at: Chipworks 3685 Richmond Rd. Suite 500 Ottawa, Ontario K2H 5B7 Canada T: F: Web site: info@chipworks.com Please send any feedback to feedback@chipworks.com

Micron MT29F2G08AAB 2 Gbit NAND Flash Memory Structural Analysis

August 17, 2006 Micron MT29F2G08AAB 2 Gbit NAND Flash Memory Structural Analysis For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor