Digital To Analog Converter

Transcription

1 Digital To Analog Converter To output analog voltage from a PC or µc, the numerical value (integer) must be converted to the analog voltage equivalent by a D/A converter. Analog outputs are much simpler than analog inputs. This process is very fast, and does not experience the timing problems of sampling and conversion with analog inputs. However, analog outputs are still subject to quantization errors.

2 Weighted Resistor Summing DAC Develop an analytical model for 3-bit DAC output in terms of the resistances, reference voltage and the switch positions.

3 Ladder Resistor Network DAC + - Vr S W A2 R 1 2 R A1 A0 2R 2R R 2R Vo G 1 B A T S W A S W A0 R 2 2 R R 3 2 R R 4 R 5 R 6 2 R R R Vo G N D Ex: Develop a model for 2-bit DAC output, via superposition. Prelab L1-1: Develop an analytical model for 3-bit DAC output in terms of the R-2R resistances, reference voltages and the switch positions. Prelab L1-2: Develop a model for the switch currents. Prelab L1-3: Install Arduino IDE masek/arduino01.pdf

4 Ladder Resistor Network DAC - cont d Solution to Prelab L1-1: v 0 V ref = + + R R 1R 2 + 2R1 2 4R R 1R 2 + 2R1 2 D 2 + R 2 (R 2 + 2R 1 ) 4R R 1R 2 + 2R1 2 D 1 + R 2 2 4R R 1R 2 + 2R 2 1 D 0

5 Ladder Resistor Network DAC - cont d Test of the solution to Prelab L1-1: R 2 = 2R 1 v 0 = D 2 V ref 2 + D D 0 8

6 Uncertainty Maximum uncertainty 1 : MAX V DAC = V DAC R R 1 + V DAC 1 R 2 Probable uncertainty 2 : R V DAC R N R N PROB V DAC = ( VDAC R 1 R1 ) 2 ( ) 2 ( ) 2 VDAC VDAC + R RN R 2 R N Assignment A1-1,2: Calculate DAC uncertainty for both, (1) 3-bit Weighted Resistor Summing DAC and (2) 3-bit Ladder Resistor Network DAC, assuming 1% tolerances. 1 represents the worst case uncertainty 2 represents a more realistic uncertainty

7 A1-1 Solution V o = ( R R 2 D 2 + R R 4 D 1 + R R 8 D 0 )V R MAX V o D0 =D 1 =D 2 =1 = R V R R2 R + R 2 R V R R4 2 R + R 4 R V R 4 R 8 R8 R 8 MAX V o = ( 1 2 1% % %)V R MAX V o = 7 8 1%V R =0.87%V R

8 A1-2 Solution MAX V o D0 =D 1 =D 2 =1 = + R2 2(7R 2 + 4R 1 ) (4R R 1R 2 + 2R1 2 V )2 R R 1 + R 1 R 2 (7R 2 + 4R 1 ) (4R R 1R 2 + 2R1 2 V )2 R R 2 MAX V o R2 =2R 1 = ( R 1 R R 2 R 1 )V R MAX V o R2 =2R 1 = ( R 1 R R 2 2R 1 )V R MAX V o = %V R =0.14%V R The three bit R-2R DAC exhibits over six times less uncertainty in comparison to the three bit weighted resistor DAC.

9 PWM to Voltage - filter design Required Attenuation in terms of the ripple voltage: A db = 20 log V RIP V PWM (1) Required Attenuation in terms of the slope S (-20, -40,...): A db = S log f PWM f 3dB (2) f 3dB = f PWM 10 A db S (3) RC filter: f 3dB = 1 2π R F C F (4)

10 PWM to Voltage - filter design cont d

11 PWM to Voltage - IC MILPITAS, CA - August 12, Linear Technology Corporation introduces the LTC2645, a quad-channel 12-bit/10-bit/8-bit PWM-to-voltage output digital-to-analog converter (DAC) with 10ppm/Â C reference. These parts convert PWM input signals to 12-bit accurate, stable, buffered voltage outputs in less than 8 microseconds, eliminating the ripple and delay typically associated with analog filters.... The LTC2645 measures the period and pulse width of the PWM input signals and updates the DACs after each PWM input rising edge, accepting PWM input frequencies from 30Hz up to 100kHz. An IDLSEL pin provides flexibility to set the outputs to idle at zero or full scale, power-down with high-impedance output, or hold the previous state indefinitely in response to an idle PWM input. This convenient mode has the advantage over analog filter implementations, which require the PWM to run continuously.

12 Analog to Digital Conversion - definitions To input an analog voltage into a PC or µcontroller, the continuous voltage value must be first sampled and then converted to a numerical value by an A/D converter. The process of sampling the data is not instantaneous, so each sample has a start and stop time. The time required to acquire the sample is called the sampling time t s. A/D converters can only acquire a limited number of samples per second. The time between samples is called the sampling period T S, and the inverse of the sampling period is the sampling frequency/rate. T s < T S The maximum V max and minimum V min readable voltages are a function of the control hardware such as 0V to 5V. The number of bits of the A/D converter is the number of bits in the result word. If the A/D converter is 8 bit then the result can read up to 256 different voltage levels.

13 Sampling DAC - Digital to Analog Conversion Sample & Hold (S/H) circuitry takes a snapshot of the input signal and holds the value for the A/D converter to have a stable signal. Often a FET switch connects capacitor to buffered input at the beginning of every sample period. The capacitor then holds the voltage value sampled until a new sample is acquired. This voltage slowly decreases over time despite of the high impedance output buffer. It is then necessary to perform the A/D conversion quickly in a short period of time.

14 S&H Chopper Circuit

15 Flash ADC consist of a set of comparators and reference voltages, and a digital encoder typically 4 to 8 bit designs due to the required number of comparators fast scanning rates typically used in TV, fast measurement instruments often a bubble error correction is applied prior to digital encoding

16 Successive Approximation ADC > 7.5 > 7 < 6.5 > 6 > 5.5 < 5 < > 3.5 > 3 < 2.5 < 2 > 1.5 < 1 < 0.5 MSB LSB 2 0 ±0.5V = LSB/2

17 Timer/Counter based ADC s RC network with a comparator V C = V R (1 e t τ ) τ = RC Charging a capacitor method is a simple time-interval based technique, however, the accuracy is low due to non-linearity, and V R / RC stability.

18 Timer/Counter based ADC s - cont d Dual Slope Integrating ADC applications that do not require high speed sampling immune to non-linearity of the integrator can be very accurate provided a longer time of conversion is acceptable An integrator is the core element in the dual-slope ADC. A zeroed integrator (V int = 0) is first connected to the measured voltage V S&H for a fixed time duration (run-up time T 1 =const). This causes the integrator to wind up to a certain voltage, say Vint u. Then a fixed reference voltage V R of the opposite polarity than V S&H is connected to the integrator which causes the integrator to back-integrate from Vint u to zero voltage. This phase is often referred to as run-down phase of time duration T 2.

19 Timer/Counter based ADC s - cont d Dual Slope Integrating ADC - SUMMARY Two voltage signal integration phases: 1 integration of the input voltage V S&H over a constant time period T 1 starting at zero (0V) 2 (back) integration of the constant reference voltage V R over a variable time T 2 until zero level crossing occurs (0V) Using a ratiometric method, the non-linearity and drift of RC is not critical as was the case of RC network ADC or a single slope ADC. V S&H = V R T 2 T 1 (5)

20 Assignment II. 1 Specify all components in the dual slope ADC circuit and define the timing sequence of control lines S-H, RES, INT, DEINT. 2 Simulate the analog to digital conversion using SPICE transient analysis and provide these waveforms: S-H(t), RES(t), INT(t), DEINT(t), V INT (t), COMP(t). 3 Propose a solution to minimize the transient spikes at the integrator s input. 4 Derive an expression for the measured voltage in terms of the design parameters and the measured time of de-integration.

21 Assignment II. - cont d Four digital outputs are required to control the conversion process assuming only uni-polar voltage being measured. One digital output controls S&H operation, two digital outputs control switching of V S&H and V R to the integrator input, and one digital output is used to discharge the capacitor at the beginning of each conversion cycle. LTspice: masek/dual-slope-adc.asc

22 Assignment II. - solution