CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541
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1 CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541 Data sheet acquired from Harris Semiconductor SCHS189A January Revised May 2000 High Speed CMOS Logic Octal Buffer and Line Drivers, Three-State Features Description [ /Title (CD74 HC540, CD74 HCT54 0, CD74 HC541, CD74 HCT54 HC540, CD74HCT Inverting HC541, HCT Non-Inverting Buffered Inputs Three-State Outputs Bus Line Driving Capability Typical Propagation Delay = 9ns at = 5V, C L = 15pF, T A = 25 o C Fanout (Over Temperature Range) - Standard Outputs LSTTL Loads - Bus Driver Outputs LSTTL Loads Wide Operating Temperature Range o C to 125 o C Balanced Propagation Delay and Transition Times Significant Power Reduction Compared to LSTTL Logic ICs HC Types - 2V to 6V Operation - High Noise Immunity: N IL = 30%, N IH = 30% of at = 5V HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, V IL = 0.8V (Max), V IH = 2V (Min) - CMOS Input Compatibility, I l 1µA at V OL, V OH The HC540 and CD74HCT540 are Inverting Octal Buffers and Line Drivers with Three-State Outputs and the capability to drive 15 LSTTL loads. The HC541 and HCT541 are Non- Inverting Octal Buffers and Line Drivers with Three-State Outputs that can drive 15 LSTTL loads. The Output Enables (OE1) and (OE2) control the Three-State Outputs. If either OE1 or OE2 is HIGH the outputs will be in the high impedance state. For data output OE1 and OE2 both must be LOW. Ordering Information PART NUMBER TEMP. RANGE ( o C) PACKAGE CD54HC540F3A -55 to Ld CERDIP CD74HC540E -55 to Ld PDIP CD74HC540M -55 to Ld SOIC CD74HCT540E -55 to Ld PDIP CD74HCT540M -55 to Ld SOIC CD54HC541F3A -55 to Ld CERDIP CD74HC541E -55 to Ld PDIP CD74HC541M -55 to Ld SOIC CD54HCT541F -55 to Ld CERDIP CD54HCT541F3A -55 to Ld CERDIP CD74HCT541E -55 to Ld PDIP CD74HCT541M -55 to Ld SOIC NOTES: 1. When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel. 2. Wafer and die for this part number is available which meets all electrical specifications. Please contact your local TI sales office or customer service for ordering information. Pinouts CD54HC540 (CERDIP) CD74HC540, CD74HCT540 (PDIP, SOIC) TOP VIEW CD54HC541, CD54HCT541 (CERDIP) CD74HC541, CD74HCT541 (PDIP, SOIC) TOP VIEW OE 1 20 OE A OE2 A OE2 A Y0 A Y0 A Y1 A Y1 A Y2 A Y2 A Y3 A Y3 A Y4 A Y4 A Y5 A Y5 A Y6 A Y Y Y7 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright 2000, Texas Instruments Incorporated 1
2 Functional Diagram CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541 OE A OE B D 0 Y0 Y 0 D 1 Y 1 Y 1 D 2 Y 2 Y 2 D 3 Y 3 Y 3 D 4 Y 4 Y 4 D 5 Y 5 Y 5 D 6 Y 6 Y 6 D 7 Y 7 Y 7 TRUTH TABLE INPUTS S OE1 OE2 An L L H L H H X X Z Z X H X Z Z L L L H L NOTE: H = HIGH Level L = LOW Level X = Don t Care Z = High Impedance 2
3 Absolute Maximum Ratings DC Supply, V to 7V DC Input Diode, I IK For V I < -0.5V or V I > + 0.5V ±20mA DC Output Diode, I OK For V O < -0.5V or V O > + 0.5V ±20mA DC Drain, per Output, I O For -0.5V < V O < + 0.5V ±35mA DC Output Source or Sink per Output Pin, I O For V O > -0.5V or V O < + 0.5V ±25mA DC or Ground, I CC ±50mA Thermal Information Thermal Resistance (Typical, Note 3) θ JA ( o C/W) PDIP Package SOIC Package Maximum Junction Temperature o C Maximum Storage Temperature Range o C to 150 o C Maximum Lead Temperature (Soldering 10s) o C (SOIC - Lead Tips Only) Operating Conditions Temperature Range, T A o C to 125 o C Supply Range, HC Types V to 6V HCT Types V to 5.5V DC Input or Output, V I, V O V to Input Rise and Fall Time 2V ns (Max) 4.5V ns (Max) 6V ns (Max) CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 3. θ JA is measured with the component mounted on an evaluation PC board in free air. DC Electrical Specifications PARAMETER HC TYPES High Level Input Low Level Input High Level Output CMOS Loads High Level Output TTL Loads Low Level Output CMOS Loads Low Level Output TTL Loads Input Leakage SYMBOL TEST CONDITIONS 25 o C -40 o C TO 85 o C -55 o C TO 125 o C V I (V) I O (ma) (V) MIN TYP MAX MIN MAX MIN MAX V IH V V V V IL V V V V OH V IH or V IL V V V UNITS V V V V OL V IH or V IL V V V I I or V V V ±0.1 - ±1 - ±1 µa 3
4 DC Electrical Specifications (Continued) PARAMETER Quiescent Device Three- State Leakage HCT TYPES High Level Input Low Level Input High Level Output CMOS Loads High Level Output TTL Loads Low Level Output CMOS Loads Low Level Output TTL Loads Input Leakage Quiescent Device Three- State Leakage Additional Quiescent Device Per Input Pin: 1 Unit Load SYMBOL I CC or I OZ V IL or V IH V O = or V IH to 5.5 V IL to µa ±0.5 - ±5.0 - ±10 µa V V V OH V IH or V IL V V V OL V IH or V IL V I I I CC and or I OZ V IL or V IH V O = or I CC TEST CONDITIONS 25 o C -40 o C TO 85 o C -55 o C TO 125 o C V I (V) I O (ma) (V) MIN TYP MAX MIN MAX MIN MAX V ±0.1 - ±1 - ±1 µa µa to ±0.5 - ±5.0 - ±10 µa NOTE: For dual-supply systems theoretical worst case (V I = 2.4V, = 5.5V) specification is 1.8mA. HCT Input Loading Table UNIT LOADS UNITS µa INPUT HCT540 HCT541 A0 - A OE OE NOTE: Unit load is I CC limit specific in DC Electrical Specifications Table, e.g., 360µA max. at 25 o C. 4
5 Switching Specifications C L = 50pF, Input t r, t f = 6ns PARAMETER SYMBOL TEST CONDITIONS (V) 25 o C -40 o C TO 85 o C -55 o C TO 125 o C MIN TYP MAX MIN MAX MIN MAX UNITS HC TYPES Propagation Delay t PLH, t PHL C L = 50pF Data to Outputs (540) ns ns C L = 15pF ns C L = 50pF ns Data to Outputs (541) t PLZ,t PHZ C L = 50pF ns ns C L = 15pF ns C L = 50pF ns Output Enable and Disable to Outputs (540) t PLZ,t PHZ C L = 50pF ns ns C L = 15pF ns C L = 50pF ns Output Enable and Disable to Outputs (541) t PLZ,t PHZ C L = 50pF ns ns C L = 15pF ns C L = 50pF ns Output Transition Time t THL, t TLH C L = 50pF ns ns ns Input Capacitance C I C L = 50pF pf Three-State Output Capacitance Power Dissipation Capacitance (Notes 4, 5) (540) Power Dissipation Capacitance (Notes 4, 5) (541) C O pf C PD C L = 15pF pf C PD C L = 15pF pf HCT TYPES Propagation Delay t PHL, t PLH Data to Outputs (540) C L = 50pF ns C L = 15pF ns Data to Outputs (541) t PHL, t PLH C L = 50pF ns C L = 15pF ns Output Enable and Disable to Outputs (540, 541) t PLZ,t PHZ C L = 50pF ns C L = 15pF ns Output Transition Time t TLH, t THL C L = 50pF ns Input Capacitance C I C L = 50pF pf 5
6 Switching Specifications C L = 50pF, Input t r, t f = 6ns (Continued) PARAMETER SYMBOL TEST CONDITIONS (V) 25 o C -40 o C TO 85 o C -55 o C TO 125 o C MIN TYP MAX MIN MAX MIN MAX UNITS Three-State Output Capacitance Power Dissipation Capacitance (Notes 4, 5) (540, 541) C O pf C PD C L = 15pF pf NOTES: 4. C PD is used to determine the dynamic power consumption, per channel. 5. P D = V 2 CC f i (C PD + C L ) where f i = Input Frequency, C L = Output Load Capacitance, = Supply. Test Circuits and Waveforms t r = 6ns t f = 6ns t r = 6ns t f = 6ns INPUT INPUT 2.7V 1.3V 0.3V 3V t THL t TLH t THL t TLH INVERTING t PHL t PLH INVERTING t PHL t PLH 1.3V FIGURE 1. HC TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC 6ns DISABLE 6ns t r DISABLE 6ns t f ns 3V tplz t PZL t PLZ t PZL LOW TO OFF LOW TO OFF 1.3V HIGH TO OFF t PHZ t PZH HIGH TO OFF t PHZ t PZH 1.3V S ENABLED S DISABLED S ENABLED S ENABLED S DISABLED S ENABLED FIGURE 3. HC THREE-STATE PROPAGATION DELAY WAVEFORM FIGURE 4. HCT THREE-STATE PROPAGATION DELAY WAVEFORM 6
7 Test Circuits and Waveforms (Continued) OTHER INPUTS TIED HIGH OR LOW DISABLE IC WITH THREE- STATE R L = 1kΩ C L 50pF FOR t PLZ AND t PZL FOR t PHZ AND t PZH NOTE: Open drain waveforms t PLZ and t PZL are the same as those for three-state shown on the left. The test circuit is Output R L =1kΩ to, C L = 50pF. FIGURE 5. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT 7
8 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI s publication of information regarding any third party s products or services does not constitute TI s approval, warranty or endorsement thereof. Copyright 2000, Texas Instruments Incorporated
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