A 136 GHz Dynamic Divider in SiGe Technology

Transcription

1 A 136 GHz Dynamic Divider in SiGe Technology Ekaterina Laskin ECE Department, University of Toronto, Toronto, ON, Canada Alexander Rylyakov IBM T. J. Watson Research Center, Yorktown Heights, NY, USA January 20th, 2009 Session 7, Paper #3 1/26

2 Outline Motivation Divider architecture and schematics Transformer design Fabrication and testing Measurement results Conclusion January 20th, 2009 Session 7, Paper #3 2/26

3 Motivation & Background Applications: Phase locked loops 1 st divider stage is critical Mm wave dividers needed in radio/radar systems 110Gb/s communication systems Measurement equipment Increase the operation frequency of divide by 2 circuit Need to keep input power < 0 dbm Dynamic dividers are faster, lower power than static Above 110GHz: no need for more BW than waveguide F band: GHz, cutoff at 73.84GHz D band: GHz, cutoff at 90.84GHz January 20th, 2009 Session 7, Paper #3 3/26

4 Divider Comparison Static Dynamic (Miller) Injection Locked Bandwidth Widest Wide Narrow Noise Low Low High Sensitivity High High High Power High Medium Low Waveguide operation OK Best Worst January 20th, 2009 Session 7, Paper #3 4/26

5 Divider Architecture Miller divider core mixer + LPF 2 stage output buffer drives 50 Ω Swing 100mV per side can drive next divider Input passive network On chip single ended to differential conversion On chip match to 50 Ω Divider chip can be driven by waveguide source in pad input network dynamic divider core output buffer Practical I/O interface out January 20th, 2009 Session 7, Paper #3 5/26

6 Divider Core Start with a Gilbert cell mixer in mixer January 20th, 2009 Session 7, Paper #3 6/26

7 Divider Core Add EFs act as a low pass filter and level shifter January 20th, 2009 Session 7, Paper #3 7/26

8 Divider Core Cherry Hopper amplifiers to extend mixer BW in mixer low pass filter January 20th, 2009 Session 7, Paper #3 8/26

9 Divider Core Input is biased with resistors in Vbias out bias mixer low pass filter January 20th, 2009 Session 7, Paper #3 9/26

10 Divider Core Consumes 72.6 mw from 3.3 V in le=2.5μm le=4μm 80Ω le=3μm le=4μm le=8.5μm Vbias out l e =3μm 637Ω 127Ω 1mA 6mA 4mA 4mA 8mA bias mixer low pass filter January 20th, 2009 Session 7, Paper #3 10/26

11 Output Buffer 2 stage design 1 st stage reduce load on divider Cherry Hooper to extend BW 2 nd stage 50Ω driver Swing: 100mV per side 46.2mW from 3.3V 200Ω 75Ω le=3μm 165pH 158pH January 20th, 2009 Session 7, Paper #3 11/26

12 Transformer Design Providing differential input from off chip is impractical Transformer for single ended to differential conversion Coupling depends on the backend and DRC rules Small h good vertical coupling Small s good sideways coupling h s M_top M_top 1 M_top 2 Use wide vertically coupled lines for higher k Small area for higher SRF substrate January 20th, 2009 Session 7, Paper #3 12/26

13 Transformer Design Implemented with vertically coupled lines January 20th, 2009 Session 7, Paper #3 13/26

14 Divider 50Ω Matching Simulated divider S 11, S 22 and transformer S 21 January 20th, 2009 Session 7, Paper #3 14/26

15 Layout and Fabrication IN D D January 20th, 2009 Session 7, Paper #3 IBM SiGe8HP ft = 210 GHz fmax = 260 GHz Circuit area: 380μm 280μm 15/26

16 CW source Test Setup (74 96 GHz) oscilloscope spectrum analyzer OUT OUT 6 multiplier GHz January 20th, 2009 Session 7, Paper #3 16/26

17 CW source Test Setup ( GHz) oscilloscope spectrum analyzer OUT OUT 6 multiplier GHz January 20th, 2009 Session 7, Paper #3 17/26

18 CW source Test Setup ( GHz) oscilloscope spectrum analyzer OUT OUT 8 multiplier GHz amplifier divider January 20th, 2009 Session 7, Paper #3 18/26

19 Test Setup January 20th, 2009 Session 7, Paper #3 19/26

20 Measured Divider Sensitivity Less than 0 dbm for dividing 74GHz 136 GHz D band 90 F band Setup #1 Setup #2 Setup #3 Simulation Input Frequency (GHz) January 20th, 2009 Session 7, Paper #3 20/

21 Divider Output Spectrum (102GHz) divider 51GHz Output PN = kHz offset Difference = 11.3dB, Ideal = 9dB CW 17GHz Phase Noise = kHz offset January 20th, 2009 Session 7, Paper #3 21/26

22 Divider Output Spectrum (131.2GHz) after external divider divider 32.8GHz Output PN = khz offset Difference = 6.8dB, Ideal = 6dB CW 16.4GHz Phase Noise = 100 khz offset January 20th, 2009 Session 7, Paper #3 22/26

23 Divider Output Time Domain 110mVpp per side in 50Ω Input at 96.6 GHz, Output at 48.3 GHz January 20th, 2009 Session 7, Paper #3 23/26

24 Divider Output Time Domain 100mVpp per side in 50Ω Input at GHz, signal accumulated for 5 minutes January 20th, 2009 Session 7, Paper #3 24/26

25 Divider Output Time Domain 100mVpp per side in 50Ω Input at 136 GHz, Output at 68 GHz January 20th, 2009 Session 7, Paper #3 25/26

26 Conclusions Dynamic divide by 2 circuit operational from 74 GHz to 136 GHz has been implemented in SiGe Requires less than 0 dbm input power Single ended to diff. conversion at input Divider core consumes 72.6 mw from 3.3 V Output buffer consumes 46.2 mw from 3.3 V January 20th, 2009 Session 7, Paper #3 26/26

27 Back up January 20th, 2009 Session 7, Paper #3 27/26

28 Test Setups Setup #1: GHz 110 GHz probe 67 GHz probe CW signal source GHz 2 Dynamic Divider Spectrum analyzer Sampling oscilloscope (70GHz head) Setup #2: GHz GHz waveguide probe 67 GHz probe CW signal source GHz 2 Dynamic Divider Spectrum analyzer Sampling oscilloscope (70GHz head) Setup #3: GHz GHz waveguide probe 67 GHz probe CW signal source GHz 2 Dynamic Divider amp 2 Sampling oscilloscope (70GHz head) Spectrum analyzer January 20th, 2009 Session 7, Paper #3 28/26