Simulation and Design Route Development for ADEPT-SiP

Transcription

1 Simulation and Design Route Development for ADEPT-SiP Alaa Abunjaileh, Peng Wong and Ian Hunter The Institute of Microwaves and Photonics School of Electronic and Electrical Engineering The University of Leeds Malcolm Edwards AWR Ltd. Copyright 2006

2 Outline HDI/ Substrate Architecture Passive Components Modelling Resistors Capacitors Inductors Transmission lines/resonators Work Plan and Developments End Users Demonstrators AWR Production Design Kit

3 ADEPT-SiP Architecture encapsulation ADEPT-SiP module active devices embedded passives HDI substrate motherboard

4 ADEPT-SiP PCB Substrate Architecture The ADEPT-SiP printed circuit board architecture involves: 6-layer board construction with 2 conductor layer core sequential build-up. High Density Interconnect (HDI) layers on either side of this core. R, L, C embedded passives in M1-M3.

5 Design Rules HDI/Microvia Outer Layer Track width>100μm Distance track-track width>125μm Inner Layer Track width>100μm Distance track-track width>100μm Microvia Standard - padφ=300μm Stacked - padφ=300μm End Φ=100μm

6 Design route development Well-defined process architecture Stable process & known capabilities Produce component characterisation boards RFOW measurements S-parameter extraction Model generation Design kit integration Ground Signal Ground Ground Signal Ground Source: IMEC, Intarsia/Dow

7 Design route application design specification schematic capture - hierarchical simulation & optimisation component generation circuit layout re-simulation design tolerance & yield Component & Layout Libraries Models Design Specification Circuit Description Analysis Optimisation design for test, reliability... mask layout verification - DRC, LVS design documentation Design Rules Layout Verification Fabrication

8 Passive Components Simulations Test Vehicle 1 (TV1) Modelling and Simulations Summery: 30 Microstrip transmission lines (including coplanar) 48 Spiral Inductors ( Square and Circular) 56 Capacitors (PTF and Prepreg) 48 Resistors

9 TV1 Floor Plan

10 Interconnects; RFOW Pads Design

11 Transmission lines Interconnect coupon is divided into four 25x25mm areas, where the line lengths are 5, 10 and 20mm. Zo (Ω) Tx line type Structure Line width (μm) (w-width, s-spacing) 50 Microstrip M1M3 (M1 trace, M3 ground) w50+15=>170 i.w50=>185 ii.w50-15=> Microstrip M2M3 (M2 trace, M3 ground) w50+15=>113 i.w50=>98 50 CPW M2 coplanar w=1880, s= CPW M1 coplanar w=1080, s= CPW M1 coplanar w=100, s=130

12 Transmission Lines and Resonators Coplanar Waveguide M1 (Ground Plane), t= 36 μ m Zo = 100Ω l = 5, 10, 20mm, h=60 μ m εr=5.4, tangent loss= Supported Coplanar Waveguide* M2 (Ground Plane), t= 9 μ m Zo = 50 Ω, 100Ω l = 5, 10, 20mm, h=60 μ m εr=5.4, tangent loss=0.035 *S. S. Bedair and I. Wolff, Fast, Accurate and Simple Approximate Analysis Formulas for Calculating the Parameters of Supported Coplanar Waveguides for MMIC s, IEEE Trans. Microwave Theory Tech., Vol.40, No. 1, pp , Jan

13 Polymer Thick Film Resistors 100Ω/square carbon based inks are used. Length(mm) Width (mm) 0.5mm family 1.0mm family 2.0mm family 3.0mm family width width width width Ω 200 Ω 50Ω 100 Ω 300 Ω 150 Ω 600 Ω 300 Ω 25Ω 50Ω 75Ω 150 Ω Ω 33.3 Ω 50Ω 100 Ω 1000 Ω 500Ω 250Ω Ω

14 Capacitors Two classes of capacitors: Polymer Thick Film Capacitors Prepreg Capacitors

15 PTF Capacitors Thickness 20um Dielectric constant = 40 Capacitance 16pF/mm 2

16 Prepreg Capacitors Thickness 50um Dielectric constant = 4 Capacitance 1pF/mm 2

17 Capacitance (pf) Prepreg Capacitor M1M2_THRU_M3_KEEPOUTS-Cal M1M2_THRU_M3_KEEPOUTS-Sim M1M2_THRU_M3_GROUNDED-Cal M1M2_THRU_M3_GROUNDED-Sim M1M2_COMMON_ELECTRODE_THRU_M3_KEEPOUTS-Sim Dimensions (Squared mm)

18 ResonantFreq (GHz) Prepreg Capacitor M1M2_THRU_M3_KEEPOUTS-Res M1M2_COMMON_ELECTRODE_THRU_M3_KEEPOUTS-Res M1M2_THRU_M3_GROUNDED-Res Dimensions (Squared mm)

19 30 25 Prepreg Capacitor M2M3_GROUNDED-Cal M2M3_GROUNDED-Sim M2M3_GROUNDED-Res Capacitance (pf) Resonant Freq (GHz) Dimensions (mm2) 0

20 Inductors TV1 include Square and Circular Spiral inductor classes. The inductor spirals are defined on Conductive Layer 1 (M1) and the underpass on Conductive Layer 2 (M2). The Gnd plane under the inductor is removed.

21 Inductors 120 Inductors; Circular Spirals with Gnd keep outs of 125, 250 and 500um Inductance nh L125 L250 L500 L_Q_250 L_Q_125 L_Q_ Quality Factor No. of Turns 0

22 Inductors 120 Inductors; Circular Spirals with Gnd keep outs of 125, 250 and 500um with the respective cutoff frequency Inductance nh L125 L250 L500 L_CF_125 L_CF_250 L_CF_ Freq (GHz) No. of Turns 0.5

23 TV1 Inductors Q

24 TV 1 Inductors Coupon Inductance Quality Factor Self resonance frequency Line width Spacing Number of Turns Rin Line width Total length Conductivity Substrate dielectric constant Substrate thickness Total length

25 Higher Rin for N=3p5

26 Future Developments Improve inductors performance (L, Q, Fres). Study various configurations for embedded passives.

27 TV 2 Calibration Coupon Transmission lines (also resonators) Short Open Loaded Terminated Coupled Lines Ring resonators At 3 and 5GHz

28 Filter Design

29 Baluns

30 TV2 Partners Contribution Filtronic Zarlink

31 AWR Design Environment The Designers View mixed technology SMD Embedded Passive Cap_PTF_M1M1 ID=Cap_PTF1 L=1000 um W=1000 um C=17.7 pf M1 M1 IND ID=L1 L=1 nh IND ID=L2 L=3 nh VIA ID=V1 D=127 um H=1651 um T=17.78 um RHO=0.7 VIA ID=V2 D=127 um H=1651 um T=17.78 um RHO=0.7 Component library defined in a Process Design Kit (PDK)

32 AWR Design Environment The Designers View 2D and 3D views 2D View 3D View The Process Design Kit (PDK) defines drawing layers, models, pcells, fixed artwork, mapping to DXF etc

33 AWR Design Environment The Library uses XML as a Glue <COPYRIGHT>Copyright(c) 2007 Applied Wave Research, Inc.</COPYRIGHT> <SUMMARY>This file contains data for the Wurth Elektronik 6 Layer HDI Process</SUMMARY> <COMPONENT Name="CAP PTF M1M1"> <MODEL>Cap_PTF_M1M1</MODEL> <DESC>PTF Capacitor with 2 Pins and integrated vias to M1</DESC> <SYMBOL>[email protected]</SYMBOL> <CELL>Cap_PTF_M1M1_Cell*</CELL> <DATA DataType="awrmodel" Inline="yes"> <PARAM Name="L">1000e-6</PARAM> <PARAM Name="W">1000e-6</PARAM> </DATA> </COMPONENT> Points to model located in DLL Points to a parametric cell (pcell) located in DLL Initial Parameter used to define the component These are supplied to the electrical model and the pcell

34 AWR Design Environment Parametric Cells The AWR Design Environment supports CALL BACK Models can report back to the schematic symbol Edit the size of the capacitor Cap_PTF_M1M1 ID=Cap_PTF1 L=1000 um W=1000 um C=17.7 pf M1 Cap_PTF_M1M1 ID=Cap_PTF1 L=1000 um W=500 um C=8.85 pf M1 Editing can be conducted using the layout editor M1 M1

35 AWR Design Environment The AWR Design Environment supports multiple technology load more than one PDK! SMD GaAs MMIC Embedded Passive SiGe RFIC

36 Conclusion TV2 Should include components with optimum performance (R, L, C, Q and Fres). Various configurations will be studied to obtain the best performance. The modelled components and results will be built into the AWR-Process Design Kit (PDK), to design microwave devices (filters, baluns etc) and partners demonstrators.