A 10Gbps/port 8x8 Shared Bus Switch with embedded DRAM Hierarchical Output Buffer

Transcription

1 A /port 8x8 Shared Bus Switch with embedded Hierarchical Output Buffer Kangmin Lee*, Se-Joong Lee, and Hoi-Jun Yoo Semiconductor System Laboratory Department of EECS Korea Advanced Institute of Science and Technology

2 Outline Introduction & Motivation Hierarchical Output Buffering Technique Simulation Results Implementation Measurement Result Conclusion 2

3 Introduction Simplified Router System Input Port 1GHz x 10b 20MHz x 512b 8x8 Shared Bus Switch Output Port 1 R NP S/P AF FIFO P/S NP T 2 R NP S/P 512b Shared Bus AF BW=80Gbps FIFO P/S NP T 8 R NP S/P AF FIFO P/S NP T 160MHz x 512b 20Mz x 512b 1GHz x 10b Bottleneck 90Gbps FIFO buffer 3

4 Motivation FIFO Requirements Max. Input BW: 80Gbps Max. Output BW: Buffer Capacity: 1Mbits (=2048 packets) 512b 80Gbps FIFO 1Mb 512b (1) Dual Port SRAM t_cycle = 6.25nsec Area: 16mm 0.18µm CMOS LAT e1 (2) Parallel e buffer t_cycle = 40nsec 9 e s Cell efficiency is degraded. Area: 20mm 2 inc. Bus and Latch 80Gbps 512b Shared Bus LAT LAT LAT e2 e3 e9 4

5 Hierarchical Output Buffer 80G SRAM 10G large bandwidth, small capacity 80G K 10G small bandwidth, Large capacity Funnel 80G Large bandwidth Large capacity 10G FIFO Max.80G K SRAM D R A M 10G input b/w time regurated b/w time intermediate bandwidth (30Gbps) SRAM Hierarchical Buffer = SRAM + e 5

6 Hierarchical Output Buffer (Cont d) HOB FIFO 512bits I/O K=30Gbps 512bits I/O e 80Gbps Dual- Port SRAM 30Gbps D M U e e M U e irregular input regulated address manager Determination of K, SRAM and e capacity Tradeoff b/w area cost and switch performance Target Performance Packet loss probability: < 90% offered load Packet Latency < 100 cycles 6

7 Hierarchical Output Buffer (Cont d) Simulation Results (K=30Gbps) - Simulation Inputs: Trace of real Internet Protocol packets Buffer Size of e [cells] Buffer Capacity 1cell = 64Bytes e SRAM Offered Load(%) Buffer Size (SRAM) [cells] SRAM: 64 packets (= 4KBytes) : 1024packets (= 0.5Mbits) Latency / Packet Loss Rate Latency [cell-time] cell-time = 48nsec Latency Cell Loss Prob. Offered Load [%] Latency : 100 cycles (= 4.8µsec) Packet Loss Rate: ~ E-3 1E-4 1E-5 1E-6 1E-7 1 1E Cell Loss Prob. 7

8 Implementation of a Prototype Run-time Traffic Control Controller HOB FIFO 256b I/O ROM 1 ROM 2 PLL ROM 3 ROM 4 Input BUS (512b) Dual Port SRAM repeater 256b I/O Input Packet Generator 20Gbps / ROM x 4 = 80Gbps Traffic Emulation Run-Time Traffic Control PLL Generates Multiple Clocks, 200MHz for SRAM, 25MHz for e 8

9 Implementation (Cont d) HOB FIFO 256b I/O PLL Input Generator Input BUS (512b) Dual Port SRAM repeater 256b I/O Dual Port SRAM 200MHz, 512b I/O, 64 words (4kB) 1 Write Port, 1 Read Port 4.5mm 2 9

10 Implementation (Cont d) HOB FIFO HOB Controller PLL Input Generator Input BUS (512b) Dual Port SRAM repeater 256b I/O ctr. Latch (128x2) Latch Latch Latch (512x512) Latch (128x2) Latch Latch Latch 256b I/O e 25MHz, 512b I/O, 512 words x 4 s (=1Mb) Dual I/O Scheme for huge I/O bandwidth 3.4mm 2 10

11 Implementation (Cont d) Dual I/O Scheme Write CLK pulse odd / clock pulse even data Latches WDRV x b 128b WDRV 1 (512x512) Read Burst select e Dual I/O circuits MU/ DEMU driver 128b 256b 512b 512b WDRV x 64 cell array WDRV Dual-I/O Interface e - Doubles the I/O Bandwidth - I/O width = Page Size Energy Efficient 11

12 Die Photo PLL ROM SRAM S-D bus S-D bus 0.16um process 0.35um Peripheral process 0.16µm Process Die Area : 6 x 11mm 2 HOB FIFO : 14.7mm 2 7.6mm 0.18µm SRAM 12

13 Measurements Waveforms Chip On Board Measurement Setup 13

14 Measurements 25ns/div (1) 25MHz Clock (2) ROM1 enable (3) ROM SRAM : 200MHz (4) e output 4 (2) (3) PLL (1) ROM SRAM (4) 200MHz 512b 100Gbps 100MHz 512b 25MHz 512b 12.5Gbps 14

15 Conclusion Hierarchical Output Buffering (HOB) Technique is proposed for 8x8 Shared Bus Switch Area reduction 7.6mm 0.18 µm embedded Process ( < 50% than conventional approach) Performance summary Max. Bandwidth of 90Gbps with 1Mb capacity Latency: 100 cycles, Packet Loss Rate: 10-6 Dual I/O scheme expands the I/O width to 512bits 15