Xilinx 7 Series FPGA Power Benchmark Design Summary May 2015

Transcription

1 Xilinx 7 Series FPGA Power Benchmark Design Summary May 15

2 Application-centric Benchmarking Process 1G Packet Processor OTN Muxponder ASIC Emulation Wireless Radio & Satellite Modem Edge QAM AVB Switcher Military Radio Mobil Backhaul FPGA resource counts, toggle rates, clock speeds Xilinx Power Estimator (XPE) version 151 MAX condition used to estimate worst-case static power XPE Competitor s Estimator Early Power Estimator (EPE) versions 15 MAX condition used to estimate worst-case static power Page

3 s Interlaken Traffic Management Interlaken s Power Benchmark: Traffic Manager in 1G Line Card Virtex-7 X69T FPGA 35 13X Interlaken 16 at 1315G SDRAM Interlaken 16 at 1315G 3 5 NPU Backplane Interface Environment Tj = 1 C Process Virtex -7 X69T -LE Stratix V 5SGXA7 I-Grade 6K Interface s GTs Rate 8 x 3-bit 5-16 Mb/s Interlaken Gb/s LC/LEs 3K 167K 15,516 Kb DSP Blocks PLLs 8 Core Freq 5 MHz *Design results sourced from Xilinx Power Estimator (XPE) version 151 and Altera Early Power Estimator (EPE) version 15 Page 3

4 s 1G EFEC OTU- Framer 1GE Mapper s Power Benchmark: 1GE over OTU Transponder Virtex-7 X69T FPGA 1G OUT- Optical Module OTL1 1X1118G CAUI 1G OUT- Optical Module X Overhead Processing 1GE Clients Overhead bus Environment Tj = 1 C Process Virtex -7 X69T -LE Stratix V 5SGXA7 I-Grade 6K Interface s GTs Rate LVCMOS 5-5 Mb/s GT Gb/s GT Gb/s LC / LEs Core Freq 39K 5K 9,36 Kb 35, 175 MHz *Design results sourced from Xilinx Power Estimator (XPE) version 151 and Altera Early Power Estimator (EPE) version 15 Page

5 Power Benchmark: ASIC Prototyping Virtex-7 FPGA T 6 X Virtex -7 T -LE Stratix V EEB (x) I-Grade x 95K Interface s GTs Rate Environment Process Tj = 1 C LC / LEs 1,K 3 6-bit Mb/s LVDS 8-1 Mb/s Core Freq 765 K 1,6 Kb MHz *Design results sourced from Xilinx Power Estimator (XPE) version 151 and Altera Early Power Estimator (EPE) version 15 Page 5

6 Channel Encoder QAM DeMod MIMO Decoder OFDM Demod Layer 1/ API DUC / DDC Channel Encoder QAM DeMod MIMO Modulator OFDM Modulator Power Benchmark: Wireless WCDMA / LTE Picocell Kintex-7 35T FPGA X GbE 6 MB 6 MB DAC 1 1 PCIe ADC MicroBlaze Processor Kintex -7 35T -LI(95V) Stratix V 5SGXA -I K Interface s GTs Rate 6 MB 3 x 16-bit Mb/s GT - Gb/s GT Gb/s GT Gb/s *Design results sourced from Xilinx Power Estimator (XPE) version 151 and Altera Early Power Estimator (EPE) version 15 Environment Process Tj = 1 C LC / LEs K 15K 1,56 Kb DSP Blocks 3 PCIe Blocks 1 Core Freq 37 MHz Page 6

7 1G Network Interface s 1 Gig EMAC FIFO J83 Annex A/B/C Modulator FIFO RRC Filter Digital Up Converter Dense Edge QAM Modulator Kintex-7 35T FPGA 18 X RF 16 1 DAC IF 6 Gigasample 1-Bit DAC Channels RF Port #1 6 Kintex -7 35T -LI(95V) Stratix V 5SGXEA -3I 36K External External Memory Memory Interface s GTs Rate LVDS Mb/s LVCMOS 1-15 MHz x 8-bit 55-8 Mb/s GT Gb/s Environment Process Tj = 1 C LC / LEs 18K 157K 1, Kb DSP Blocks 61 Core Freq 38, 576,156, 19, MHz *Design results sourced from Xilinx Power Estimator (XPE) version 151 and Altera Early Power Estimator (EPE) version 15 Page 7

8 SD / HD / 3G Receive Interface Frame Buffer Control / Frame Sync Chroma Keyer Mixes, Wipes, Effects SD / HD / 3G Transmit Interface Power Benchmark: AVB Switcher Kintex-7 35T FPGA X SDRAM SD/HD/3G Inputs 1 8 SD/HD/3G Outputs Kintex -7 35T -LI (95V) Arria V 5AGXB3 I-Grade 36K Interface s GTs Rate 3 x 7-bit 5-8 Mb/s GT Gb/s Environment Tj = 1 C LC / LEs Process 3K 188K 1,8 Kb DSP Blocks 5 Core Freq 185 MHz *Design results sourced from Xilinx Power Estimator (XPE) version 151 and Altera Early Power Estimator (EPE) version 15 Page 8

9 SD / HD / 3G Receive Interface Frame Buffer Control / Frame Sync Chroma Keyer Mixes, Wipes, Effects SD / HD / 3G Transmit Interface AVB Switcher (-channel) Artix-7 1T FPGA DDR /3 SDRAM 5 17X SD/HD/3G Inputs * SD/HD/3G Outputs * 3 3 Control Interface *Note: SD/HD/3G inputs and outputs share GTs 1 1 Artix -7 1T -1LI (95V) Cyclone V 5CGXC7 C-Grade 19K Interface s GTs Rate 1 x 6-bit 11-8 Mb/s GT - 97 Gb/s Environment Process Tj = 85 C LC / LEs 75K 7K,5 Kb DSP Blocks 15 PLL 1 Phaser Block 1 Core Freq 185, MHz *Design results sourced from Xilinx Power Estimator (XPE) version 151 and Altera Early Power Estimator (EPE) version 15 Page 9

10 s s Power Benchmark: Single Channel Mobile Backhaul Artix-7 T FPGA Control Plane Processor SRAM 8 1X Ethernet Switch 7 6 Traffic Management, Packet Processing Timing Synchronization Modem Environment Process Tj = 1ºC LC / LEs 13K Artix -7 T -1LI(95V) Arria V 5AGXA5 I-Grade 19K Interfaces s GTs Rate 1 x 3-bit 7-8 Mb/s LVDS pairs 18-8 Mb/s SEIO 15-1 Mb/s Switch ports - 1 Gb/s 81K 5,76 Kb DSP Blocks 35 PLL Core Freq 5, MHz *Design results sourced from Xilinx Power Estimator (XPE) version 151 and Altera Early Power Estimator (EPE) version 15 Page 1

11 Power Benchmark: Satellite Modem Artix-7 1T FPGA x 157x Artix -7 1T -1LI(95V) Cyclone V 5CGEA7 I-grade 15K Environment Tj = 85 C LC/LEs Process 85 K 5 K 3, Kb DSP Blocks 16 Interface s GTs Rate PLLs 1x 3-bit DDR 69-5 Mb/s Core Freq 3, 65, 15 MHz *Design results sourced from Xilinx Power Estimator (XPE) version 151 and Altera Early Power Estimator (EPE) version 15 Page 11

12 Military Network Protocol Platform Data Aggregator Artix-7 T FPGA 7 11X Artix -7 T -1LI(95V) Arria V 5AGXA5 C-Grade 19K Interface s GTs Rate x 36-bit RLDRAMs 1-5 Mb/s GT Gb/s GT Gb/s GT Gb/s Environment Process Tj = 85 C LC / LEs 63K 58K 3,6 Kb DSP Blocks PCIe Blocks 1 Core Freq 15 MHz *Design results sourced from Xilinx Power Estimator (XPE) version 151 and Altera Early Power Estimator (EPE) version 15 Page 1