Asynchronous Bypass Channels

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1 Asynchronous Bypass Channels Improving Performance for Multi-Synchronous NoCs T. Jain, P. Gratz, A. Sprintson, G. Choi, Department of Electrical and Computer Engineering, Texas A&M University, USA

2 Table of Contents Motivation Architecture and Operation Topology and Routing Algorithm Evaluation Conclusion and Future Work

3 Motivation Feature size is decreasing and number of cores on a chip is increasing. Interconnect latency forms a major portion of the total latency seen by an application.

4 Motivation

5 Objectives of ABC Offer asynchronous bypass channels (ABCs) at the intermediate nodes to avoid Synchronization delay Latching delay Explore network topologies and routing algorithms to complement the ABC router. Offer a skew tolerant solution for multisynchronous networks.

Explore network topologies and routing algorithms to complement the

6 Table of Contents Motivation Architecture and Operation Topology and Routing Algorithm Evaluation Conclusion and Future Work

7 ABC Network Architecture Clocking scheme Mesochronous Source-synchronous Routing algorithm Unicast Deterministic Source coded Flow control Wormhole On/Off

8 ABC Network Architecture 5 input and output ports Paths connecting the opposite cardinal directions are referred to as straight-paths All other paths are known as turnpaths. - + PE ROUTER NODE

are referred to as straight-paths All other paths

9 Router Micro-Architecture Straight path : ABC path Pair of bi-synchronous FIFO and a synchronous FIFO. Turn path: bisynchronous FIFOs. A clock signal is also transmitted along with the data.

10 Router Operation ABC state Incoming flits utilize the ABC path. In this state a flit faces only the link delay and the multiplexer overhead. (Assumed to be 3/4 th of a clock cycle). The incoming clock is retained and transmitted with the data. Flits are also latched into the synchronous FIFO. FIFO state Incase of late arriving control flow from downstream Flushed away when not needed Flits are read out from one of the bisynchronous FIFOs. The flit faces a delay of 2 cycles to appear at the output of the bisynchronous FIFO. Same as in traditional synchronizing router designs. The local clock at the node is transmitted with the data.

FIFO state Incase of late arriving control flow from downstream Flushed away when not needed Flits are read out from one of the bisynchronous FIFOs.

11 Router Operation

12 Table of Contents Motivation Architecture and Operation Topology and Routing Algorithm Evaluation Conclusion and Future Work

13 Topology Cost of turn : 3 cycles. Cost of ABC : Link delay + Multiplexer overhead assumed.75 clock cycles. ABC routers favor straight paths over turns. Need to search for complementary topologies.

14 Topology Observations: Reduce the number of turns to improve performance 1-D topology? Removes all turns Hop count does not scale well with node count >2-D topology? High impact on resources required by ABC router (number of FIFOs grows exponentially w/ dimension above 2) 2-D topology? 2-D topologies a good fit for planar silicon implementation 2-D mesh requires a turn for most source and destination pairs

High impact on resources required by ABC router (number of FIFOs grows exponentially w/ dimension

15 2-D Topologies Number of router ports required must be five. It must consist of only two chains. Each chain must pass through all the nodes. Chains must be ordered. Connection between neighboring nodes only. Overall maximum bisection bandwidth must be equivalent to a standard mesh topology.

Each chain must pass through all the nodes. Chains must be ordered.

16 2-D Topologies SERPENTINE HOOK H-SHAPE SICKLE

17 Routing Algorithm A modified version of standard XY dimension order routing (DOR). Routing algorithm selects the path with the least delay in terms of clock cycles with a bias towards the straight path. Route encoded at source node. Chains are ordered to avoid deadlocks S D

Routing algorithm selects the path with the least delay in terms of

18 Table of Contents Motivation Architecture and Operation Topology and Routing Algorithm Evaluation Conclusion and Future Work

19 Methodology Baseline Network 7x7, 2-D mesh network XY DOR routing Router Two VCs per port 8-flit-deep Packets synchronized at every hop 3 cycle penalty ABC Network 7x7, Serpentine network ABC routing Router 8 bi-synch 6-flit-deep 4 synch FIFOs 3-flit-deep Packet length was varied randomly between two to five flits. Fully Synthesizable Verilog model used for simulations.

network ABC routing Router 8 bi-synch 6-flit-deep 4 synch FIFOs 3-flit-deep Packet length

20 Methodology Synthetic load Traffic Generated: Uniform Random Bit Complement Transpose 1000 cycles of warm-up 5000 packets monitored Realistic Workload SPLASH-2 suite of benchmarks obtained from a forty-nine node, shared memory CMP system simulator 10,000 cycles of warm-up 500,000 cycles from the middle of each trace

SPLASH-2 suite of benchmarks obtained from a forty-nine node, shared memory CMP

21 Evaluation (Synthetic Traffic) Uniform Random Lower no-load latency. Higher saturation throughput. Kink at 15% injection rate.

22 Evaluation (Synthetic Traffic) Bit Complement Lower no-load latency. Higher saturation throughput. Kink at 10% injection rate. Better performance because of better utilization of ABC.

23 Evaluation (Synthetic Traffic) Transpose Higher throughput because of higher bisection bandwidth. Marginal improvement in no load latency.

24 RELATIVE LATENCY Evaluation (Realistic Traffic) ABC BASELINE SPLASH-2 SUITE

25 Table of Contents Motivation Architecture and Operation Topology and Routing Algorithm Evaluation Conclusion and Future Work

26 Conclusion Introduced Asynchronous Bypass channel router. Avoids synchronization and latching at each hop required in multi-synchronous designs. Lower per-hop latency New topology and routing algorithm to match ABC's strengths. Lower number of hops Provides improved performance versus baseline for all workloads examined.

27 Future Work Lower latency solutions for turn paths Optimal topologies for ABC enhanced routers Implementing algorithms based on dynamic congestion information for Routing Polymorphic Topologies Switch between the FIFO and ABC

28 Thank You

29 NUMBER OF CLOCK CYCLES Evaluation (Topologies) AVERAGE WORST TOPOLOGY

Use-it or Lose-it: Wearout and Lifetime in Future Chip-Multiprocessors

Use-it or Lose-it: Wearout and Lifetime in Future Chip-Multiprocessors Hyungjun Kim, 1 Arseniy Vitkovsky, 2 Paul V. Gratz, 1 Vassos Soteriou 2 1 Department of Electrical and Computer Engineering, Texas