AFDX networks. Computers and Real-Time Group, University of Cantabria

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1 AFDX networks By: J. Javier Gutiérrez Computers and Real-Time Group, University of Cantabria ArtistDesign Workshop on Real-Time System Models for Schedulability Analysis Santander, 7-8 February 2011 GRUPO DE COMPUTADORES Y TIEMPO REAL By: J. Javier Gutiérrez 1

ArtistDesign Workshop on Real-Time System Models for Schedulability

2 Introduction to AFDX networks AFDX (Avionics Full Duplex Switched Ethernet) is a communications network defined in the ARINC-664, Part 7 standard: point to point full duplex Ethernet links (redundant) special purpose switches with preconfigured routing two main types of communication ports: - Sampling Port: the arriving message overwrites the current message stored in the buffer - Queueing Port: the arriving message is appended to a FIFO queue UDP/IP protocol is used for transmission traffic regulation is made in transmission via Virtual Links GRUPO DE COMPUTADORES Y TIEMPO REAL By: J. Javier Gutiérrez 2

Port: the arriving message overwrites the current message stored in the buffer - Queueing Port: the arriving message is appended to a FIFO queue UDP/IP

3 Traffic regulation in AFDX Each virtual link (VL) is characterized by two parameters: the largest Ethernet frame (Lmax): a value in bytes that can be transmitted on the VL the Bandwidth Allocation Gap (BAG): - the minimum interval in milliseconds between Ethernet frames transmitted on the VL - a power of 2 value in the range [1,128] Each virtual link has a FIFO queue for all the fragmented packets: the same VL can be shared by several ports, tasks or partitions - It can cause a poor schedulability of the system there is no way to prioritize messages on a VL GRUPO DE COMPUTADORES Y TIEMPO REAL By: J. Javier Gutiérrez 3

2 value in the range [1,128] Each virtual link has a FIFO queue for all the fragmented packets: the same VL can be shared by several ports, tasks or

4 Maximum jitter The maximum allowed jitter on each VL at the output of the end system should comply with both of the following formulas: MaxJitter 40μs + i { setofvls} (( 20 + Lmax i ) 8) N bw MaxJitter 500μs N bw is the speed of the Ethernet link in bits per second 40 μs is the typical minimum fixed technological jitter GRUPO DE COMPUTADORES Y TIEMPO REAL By: J. Javier Gutiérrez 4

------------------------------------------------------------------------ N bw MaxJitter 500μs N bw is the speed

5 Ethernet frame 64 bytes 7 bytes Preamble 1 byte Start Frame Delimiter 6 bytes 6 bytes Destination Address Source Address 2 bytes Type (0x800 IP V4) IP Structure UDP Structure 20 bytes 8 bytes 46 bytes 4 bytes AFDX Payload 1 to 17 bytes Padding 0 to 16 SN 1 Frame Check Seq 12 bytes Inter Frame Gap 1518bytes 7 bytes Preamble 1 byte Start Frame Delimiter 6 bytes 6 bytes Destination Address Source Address 2 bytes Type (0x800 IP V4) IP Structure UDP Structure 20 bytes 8 bytes 1500 bytes 4 bytes AFDX Payload 1471 bytes SN 1 Frame Check Seq 12 bytes Inter Frame Gap Lmax should be in the interval [64,1518] GRUPO DE COMPUTADORES Y TIEMPO REAL By: J. Javier Gutiérrez 5

Start Frame Delimiter 6 bytes 6 bytes Destination Address Source Address 2 bytes Type (0x800 IP V4) IP Structure UDP Structure 20 bytes 8 bytes 1500 bytes 4 bytes

6 Sub-Virtual Links A virtual link can be composed of a number of Sub-Virtual Links Each Sub-VL has: a dedicated FIFO queue a round robin algorithm working over IP fragmented packets GRUPO DE COMPUTADORES Y TIEMPO REAL By: J. Javier Gutiérrez 6

a round robin algorithm working over IP fragmented packets

7 Latency in the transmission If fragmentation is not required and the messages are produced at a frequency that is equal to or lower than the BAG of the VL: MaxLatency BAG + MaxJitter + L T L T is the technological latency in the transmission (it should be lower than 150μs). If fragmentation is required or messages are produced in bursts, the latency for packet p (with p-1 packets waiting in the VL FIFO queue): MaxLatency( p) p BAG + MaxJitter + L T GRUPO DE COMPUTADORES Y TIEMPO REAL By: J. Javier Gutiérrez 7

8 AFDX switch Transmissions to or from the switch are made using the full capacity of the physical link Packets are delivered in a store and forward way: the hardware latency of the switch should be taken into account A new source of jitter appears in the FIFO queue where packets should wait to be sent to the destination end system GRUPO DE COMPUTADORES Y TIEMPO REAL By: J. Javier Gutiérrez 8

be taken into account A new source of jitter appears in the FIFO queue where packets should wait

9 Latency in the reception Once a message is completely received, it is enqueued at the corresponding AFDX port it could potentially overflow The technological latency of the end system in reception, L R, should be lower than 150μs GRUPO DE COMPUTADORES Y TIEMPO REAL By: J. Javier Gutiérrez 9

The technological latency of the end system in reception, L R, should be

10 Modelling The model is similar to the one for the analysis of tasks We consider two types of messages: Synchronized: - the release times of these messages are relative to a general and common reference of time - an offset to represent the interval between the start of the MAF (Major Frame) and the earliest release of the message Non-synchronized: messages can be released at any time GRUPO DE COMPUTADORES Y TIEMPO REAL By: J. Javier Gutiérrez 10

offset to represent the interval between the start of the MAF (Major Frame) and the earliest release of the

11 Modelling (cont d) Different types of parameters to model AFDX communication: message stream parameters b - M i, p i, Np i, N i, M b i, p b i, Np b b i, N i, T i, Φ i, J i, Source(σ i ), L i, L i VL parameters - BAG j, Lmax j, SourcePorts(VL j ), DestinationPorts(VL j ) hardware parameters L R b - N bw, L T, L Tmin, J Tech, L R,, L S b Ethernet frame and protocol parameters - O Eth, O Prot, N min GRUPO DE COMPUTADORES Y TIEMPO REAL By: J. Javier Gutiérrez 11

SourcePorts(VL j ), DestinationPorts(VL j ) hardware parameters L R b - N bw, L T, L Tmin, J Tech, L R,, L S b

12 Latency Model SENDING END SYSTEM RECEIVING END SYSTEM SWITCH C Send L VL L Tr L SW L Tr L Rec C Receive AFDX API Ethernet Hardware Ethernet Hardware AFDX API Physical Links 5 steps in the communication process 2 contention points: queueing in the sending end system (L VL ) and queueing in the switch (L SW ) GRUPO DE COMPUTADORES Y TIEMPO REAL By: J. Javier Gutiérrez 12

in the communication process 2 contention points: queueing in the sending end system (L VL )

13 AFDX in MAST-2 Processing Resources - Network: AFDX_Link - Network_Switch: AFDX_Switch Scheduling Policy - AFDX_Policy Scheduling Parameter - AFDX_Virtual_Link Schedulable Resource - Communication_Channel Event Handler - Message_Event_Handler: Message_Delivery, Message_Fork GRUPO DE COMPUTADORES Y TIEMPO REAL By: J. Javier Gutiérrez 13

Schedulable Resource - Communication_Channel Event Handler - Message_Event_Handler:

14 AFDX in MAST-2: Network GRUPO DE COMPUTADORES Y TIEMPO REAL By: J. Javier Gutiérrez 14

15 AFDX in MAST-2: Scheduling Policy GRUPO DE COMPUTADORES Y TIEMPO REAL By: J. Javier Gutiérrez 15

16 AFDX in MAST-2: Scheduling Policy (cont d) AFDX_Policy: messages are scheduled through virtual links messages are scheduled in FIFO order when they are originated at an AFDX switch This policy may only be assigned to a scheduler that has an AFDX_Link as its host GRUPO DE COMPUTADORES Y TIEMPO REAL By: J. Javier Gutiérrez 16

originated at an AFDX switch This policy may only be assigned to a scheduler that

17 AFDX in MAST-2: Scheduling Parameters GRUPO DE COMPUTADORES Y TIEMPO REAL By: J. Javier Gutiérrez 17

18 AFDX in MAST-2: Schedulable Resource GRUPO DE COMPUTADORES Y TIEMPO REAL By: J. Javier Gutiérrez 18

19 AFDX in MAST-2: Schedulable Resource (cont d) DEFAULT_COMMUNICATION_CHANNEL: used for communications through AFDX links when the message is originated at an AFDX switch the implicit scheduling policy is FIFO ordering for the messages GRUPO DE COMPUTADORES Y TIEMPO REAL By: J. Javier Gutiérrez 19

when the message is originated at an AFDX switch the implicit scheduling

20 AFDX in MAST-2: Switch It is capable of delivering messages arriving at an input port to one or more output ports The delivery operations are specified through special-purpose message event handlers MAST does not require to define the network topology (it is implicit in the end-to-end-flow) It is assumed a shared memory switch in which messages do not need to be copied Contention occurs when several messages need to be sent to the same output port, in which case a queue is used at the output port GRUPO DE COMPUTADORES Y TIEMPO REAL By: J. Javier Gutiérrez 20

end-to-end-flow) It is assumed a shared memory switch in which messages do not need to be copied Contention occurs when several messages

21 AFDX in MAST-2: Switch (cont d) GRUPO DE COMPUTADORES Y TIEMPO REAL By: J. Javier Gutiérrez 21

22 AFDX in MAST-2: Message_Event_Handler GRUPO DE COMPUTADORES Y TIEMPO REAL By: J. Javier Gutiérrez 22

23 Example: sending a message through a switch CPU1 SWITCH CPU2 Task1 Message Task2 Task1 M1 MD1 M2 Task2 Step: Regular_P Thread Fixed_P_P Step: AFDX Link Comm_Chan AFDX Policy Message_E_H: Switch Step: AFDX Link Default_C_C FIFO Step: Regular_P Thread Fixed_P_P GRUPO DE COMPUTADORES Y TIEMPO REAL By: J. Javier Gutiérrez 23

Response time analysis in AFDX networks with sub-virtual links and prioritized switches

Response time analysis in AFDX networks with su-virtual links and prioritized switches J. Javier Gutiérrez, J. Carlos Palencia, and Michael González Harour Computers and Real-Time Group, Universidad de