DUAL UP-COUNTER High-Voltage Silicon-Gate CMOS

Transcription

1 IW4B DUAL UP-COUNTER High- Silicon-Gate CMOS The IW4B Dual Binary Up-Counter coists two identical, internally synchronous 4-stage counters. The counter stages are D-type flip-flops having interchangeable CLOCK and ENABLE lines for incrementing on either the positive-going or negative-going traition. For singleunit operation the ENABLE input is maintained high and the counter advances on each positive-going traition of the CLOCK. The counters are cleared by high levels on their RESET lines. The counter can be cascaded in the ripple mode by connecting Q4 to the enable input of the subsequent counter while the CLOCK input of the latter is held low. Operating Range: 3.0 to 18 V Maximum input current of 1 µa at 18 V over full packagetemperature range; 0 na at 18 V and 2 Noise margin (over full package temperature range): 1.0 V V supply 2.0 V V supply 2. V V supply ORDERING INFORMATION IW4BN Plastic IW4BD SOIC T A = - to 12 C for all packages PIN ASSIGNMENT LOGIC DIAGRAM PIN 16=V CC PIN 8= GND FUNCTION TABLE Inputs Outputs CLOCK ENABLE RESET Mode H L Increment Counter L L Increment Counter X L No Change X L No Change L L No Change H L No Change X X H Q1 thru Q4=L X = don t care 1

2 IW4B MAXIMUM RATINGS * Symbol Parameter Value V CC DC Supply (Referenced to GND) -0. to + V V IN DC Input (Referenced to GND) -0. to V CC +0. V V OUT DC Output (Referenced to GND) -0. to V CC +0. V I IN DC Input, per Pin ± ma P D Power Dissipation in Still Air, Plastic DIP+ 70 mw SOIC Package+ 00 P D r Dissipation per Output Traistor 0 mw Tstg Storage Temperature -6 to +0 T L Lead Temperature, 1 mm from Case for Seconds (Plastic DIP or SOIC Package) 260 * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditio. +Derating - Plastic DIP: - mw/ from 6 to 12 SOIC Package: : - 7 mw/ from 6 to 12 RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max V CC DC Supply (Referenced to GND) V V IN, V OUT DC Input, Output (Referenced to 0 V CC V GND) T A Operating Temperature, All Package Types This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. However, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, V IN and V OUT should be cotrained to the range GND (V IN or V OUT ) V CC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC ). Unused outputs must be left open. 2

3 IW4B DC ELECTRICAL CHARACTERISTICS(s Referenced to GND) Symbol Parameter Test Conditio V V IH Minimum High- V OUT = 0. V or V CC - 0.V V Level Input V OUT = 1.0 V or V CC V V OUT = 1. V or V CC - 1.V V IL Maximum Low - V OUT = 0. V or V CC - 0.V V Level Input V OUT = 1.0 V or V CC V V OUT = 1. V or V CC - 1.V V OH Minimum High- V IN =GND or V CC V Level Output V OL Maximum Low- V IN =GND or V CC V Level Output I IN Maximum Input V IN = GND or V CC 18 ±0.1 ±0.1 ±1.0 µa Leakage I CC Maximum Quiescent Supply (per Package) V IN = GND or V CC µa I OL Minimum Output Low (Sink) I OH Minimum Output High (Source) V IN = GND or V CC U OL =0.4 V U OL =0. V U OL =1. V V IN = GND or V CC U OH =2. V U OH =4.6 V U OH =9. V U OH =13. V ma ma 3

4 IW4B AC ELECTRICAL CHARACTERISTICS(C L =0pF, R L =kω, Input t r =t f = ) Symbol Parameter V f max Maximum ClockFrequency, (Figure 1) t PHL, t PLH t PHL Maximum Propagation Delay, Clock or Enable to Output (Figures 1,3) Maximum Propagation Delay, Reset to Output (Figure 2) t THL, t TLH Maximum Output Traition Time, Any Output (Figure 1) C IN Maximum Input Capacitance - 7. pf MHz TIMING REQUIREMENTS(C L =0pF, R L = kω, Input t r =t f = ) Symbol Parameter V t w Minimum Pulse Width, Clock (Figure 1) t w Minimum Pulse Width, Reset (Figure 2).0 t w t r, t f Minimum Pulse Width, Enable (Figure 3) Maximum Input Rise and Fall Times (Figure 1) µs Figure 1. Switching Waveforms Figure 2. Switching Waveforms 4

5 IW4B Figure 3. Switching Waveforms TIMING DIAGRAM EXPANDED LOGIC DIAGRAM (1/2 of the Device)