FOW/PLP Consortium. Kick-off meeting

Transcription

1 FOW/PLP Consortium Kick-off meeting

2 Fan-Out Wafer/Panel-Level Packaging (FOW/PLP) Consortium (9:30 16:30, September 8, 2016) Unimicron ( 欣興電子 ) No. 290, Chung-Lun Village, Hsinfeng, Hsinchu ( 新竹縣新豐鄉中崙村 290 號 ) AGENDA 9:30 9:35 Welcome (TJ Tseng, Chairman, Unimicron) 9:35 9:40 Welcome (Nelson Fan, Vice President, ASM-HK) 9:40 9:50 Self-introduction (all participants) 9:50 10:45 Objectives, scope, key tasks, approach, deliverables, IP issues, communication methods, membership fee (all participants) 10:45 11:00 Tea break (all participants) 11:00 12:30 Key capability of each participant company ( 15 minutes for each company) 12:30 1:30 Lunch (all participants) 1:30 3:00 Test vehicles (all participants) 3:00 3:10 Tea break (all participants) 3:10 3:50 Test vehicles and company task assignments (all participants) 3:50 4:30 Plant tour (all participants) 4:30 - So long (all participants)

3 FOW/PLP Consortium Chip-First (die-up and die-down) Fan-Out Wafer/Panel-Level Packaging (FOW/PLP)

4 FOW/PLP Consortium Project Title: Chip-First (die-up and die-down) FOW/PLP Duration: 24 months Fee: US$50,000* Die-down Panel Die-up Panel Passi vatio n Over mold Rthe reconfi DL gured s R carrier Sold er Sold balls er DL balls s CHIP CHIP Passivatio Sputter Al or Cu n Spin UBM coat and a polymer electroplate and dice contact CHIP the CHIP wafer pad *Please see The Rights and Fee of FOPLP Consortium Members. Over mol d the reco Sol R nfig der D ured ball L carri s s er R D L s

5 PURPOSES The objective of the consortium is to develop low-cost and high-throughput manufacturable processes for FOW/PLP with emphasis on: (a) WLSiP (wafer-level System-in-Package) and PLSiP (panel-level System-in- Package) (b) P&P (pick & place) technology (c) Low-warpage molding (d) RDLs (redistribution-layers) technology (e) Line width and spacing

6 Fan-Out Wafer/Panel-Level Packaging (FOW/PLP) CHIP1 EMC CHIP2 Solder ball RDLs Printed Circuit Board (PCB)

7 Panel Sizes: 340mmx340mm (area: 1.6 times of 12 wafer) 457mmx610mm (area: 3.8 times of 12 wafer) Wafer Size: 300mm SCOPES Line width/spacing 10µm: Formation is chip-first with die-down P&P use high-precision and SMT equipment RDLs use PCB + LDI (laser direct imaging) technology RDLs use polymer +ECD Line width/spacing <10µm: Formation is chip-first with die-up P&P use high-precision equipment RDLs use polymer + ECD

8 Key Tasks Design of Test Vehicles Electrical design & characterization of FOW/PLP Structural design and optimization of FOW/PLP Thermal design and optimization of FOW/PLP FOPLP Technology P&P process development Compression molding process development Redistribution layer (RDL) process development Solder ball mounting Material selections Warpage Control Assembly and Reliability PCB Assembly processes development Testing Characterizations Reliability assessment and failure analysis

9 Chip-First (Die-Down) FOW/PLP 2-side (thermal release ) tape Device Wafer Die-first (face-down) Temporary panel carrier KGD KGD KGD Passivation Al or Cu KGD Test for known good die (KGD) Over mold the reconfigured panel carrier EMC (epoxy mold compound) Remove carrier and tape Build RDLs and mount solder balls RDLs Solder balls Dice the molded panel into individual packages EMC KGD CHIP KGD CHIP KGD RDLs Solder balls

10 RDLs by Polymer and Cu Electroplating (Die-Down) Al or Cu Passivation KGD PI, BCB, or PBO EMC Mask aligner or Stepper (Litho) Spin Polymer Cu Plating Photoresist RDL1 Polymer Strip Resist & Etch TiCu Mask aligner or Stepper (Litho) RDL1 RDL2 TiCu TiCu Etch Polymer, Strip Resist Sputter TiCu Photoresist Al or Cu KGD KGD Passivation Solder ball Contact pad EMC RDL2 Dielectric2 RDL1 Dielectric1 TiCu UBM EMC

11 RDLs by PCB + LDI Technology (Die-Down) Al or Cu Passivation KGD EMC Cu etching Cu Resin Lamination of a RCC on the reconfigured panel RDL1 Strip photoresist Photoresist Drilling Cu plating to fill the hole and connect to the pad Contact pad RDL2 Cu Resin RDL1 Cu Resin KGD Solder ball EMC Solder mask Repeat all the processes to get RDL2 Photoresist Laser direct imaging (LDI) KGD Al or Cu Cu Resin RDL2 Cu Resin RDL1 Cu Resin EMC Passivation Repeat all the processes to get Cu contact pads, spin coat solder mask, and mount solder balls

12 Chip-First (Die-Up) FOW/PLP 2-side tape Reinforced wafer (optional) Device Wafer Die-first (face-up) KGD Temporary panel carrier KGD KGD UBM Contact pad KGD Sputter UBM and electroplate contact pad Over mold the reconfigured panel carrier EMC UBM Polymer Contact pad Backgrind the over-mold to expose the contact pad KGD Passivation Al or Cu Spin coat a polymer and dice the wafer Solder balls RDLs Build RDLs on contact pads and mount solder balls Remove carrier and tape and then dice the molded wafer or panel into individual packages RDLs Solder balls KGD KGD KGD

13 Polymer RDLs by Polymer and Cu Electroplating (Die-Up) UBM Contact Passivation Cu EMC KGD Polymer, e.g., PI, BCB, or PBO Mask aligner or Stepper (Litho) Spin Polymer Photoresist Mask aligner or Stepper (Litho) Etch Polymer, Strip Resist RDL1 Polymer RDL1 TiCu RDL2 Cu Plating Strip Resist & Etch TiCu Sputter TiCu TiCu Contact Solder Ball UBM RDL1 RDL2 Dielectric2 Photoresist Polymer UBM Cu KGD Contact Passivation Dielectric1 EMC

14 APPROACH Members input Finalize FOW/PLP project scope and test vehicle specification Electrical/Thermal design P&P development Molding process development RDL process development Electrical characterization Test vehicle fabrication Quick reliability assessment Design/process/assembly Improvement Final electrical/ Thermal characterization Final test vehicle fabrication and assembly Final reliability test and failure analysis

15 DELIVERABLES Design guidelines of using FOW/PLP. Materials guidelines of using FOW/PLP. Process guidelines (such as P&P, molding, RDLs, ball mounting, dicing, and PCB assembly) of using FOW/PLP. Electrical modeling results and characterization data for FOW/PLP. Mechanical & thermal modeling results and optimization for FOW/PLP. Reliability data and failure analysis report of FOW/PLP. Cost models for FOW/PLP. The limitations of FOW/PLP.

16 IP Issues In order to use a prior-art IP (intellectual property), it has to be voted on by a simple majority by the members of this consortium prior to its use. The title, and interest to any IP developed during the course of this project development shall be owned and the cost of all IPs will be shared by the members of this consortium who have contributed to the development of the IP. Notwithstanding the foregoing, all the members of this consortium (including those who have not contributed to the development of the IP during the course of this project development) shall have the right to use the IP developed during the course of this project development in their normal course of business without the need to pay any royalty fee for their usage thereof.

17 Introduction to ASM FOW/PLP Membership

18 The Rights and Fee of FOW/PLP Consortium Members 1. The FOW/PLP consortium members shall A. have a right to participate any portion of the project. B. have a right to vote on the project expenses, which come from the member fee. C. have a right to jointly work out a future development roadmap for FOW/PLP project and timeframe. D. have a right to attend regular 3-month meeting/discussions of FOW/PLP project. E. have a right to obtain regular FOW/PLP project meetings, minutes, and joint development status report on a monthly basis. 2. Member fee is US$50,000, which covers project materials (e.g., Si-wafer. UBM, and raw materials) and sub-contract (e.g., reliability tests) cost.

19 FOW/PLP Consortium Test Vehicles

20 70µm 9mm Peripheral pads at 150µm pitch (Staggered) 50µm Chip Size (9mm x 9mm) for Test Vehicles (12 Wafer) 9mm Polymer Contact pad Passivation 60µm UBM (Ti/Cu) Peripheral pads at 150µm pitch (Staggered) Si 50µm CHIP 70µm Area-array pads at 150µm pitch CHIP Daisy-Chain > 2500 pads 150µm

21 70µm 50µm 5mm Chip Size (5mm x 5mm) for Test Vehicles (12 Wafer) 5mm 50µm Passivation CHIP Si For the 5x5mm chip, there are ~200 peripheral pads on a 100µm-pitch. 50µm CHIP 70µm Daisy-Chain Peripheral s 100µm

22 70µm 50µm 3mm Chip Size (3mm x 3mm) for Test Vehicles (12 Wafer) 3mm 50µm Passivation CHIP Si For the 3x3mm chip, there are ~120 peripheral pads on a 100µm-pitch. 50µm CHIP 70µm Daisy-Chain Peripheral s 100µm

23 Phase - I

24 5mm TV9W (Phase-I) > mm (Wafer) Carrier 9mm 9mm 5mm 10mm

25 TV9 (Phase-I) 14mm 9mm FO Package (14mm x 14mm) 9mm EMC CHIP 2.5mm 14mm Line width/spacing of: 1st RDL are 5/5µm 2 nd RDL are 10/10µm 3 rd RDL are 15/15µm 2.5mm

26 TVWSiP (Phase-I) > mm (Wafer) Carrier 3.88mm 3.88mm 8.12mm 8.12mm

27 TVSiP (Phase-I) 1.94mm 12mm 5mm 3mm 120µm 3mm 3mm 1.94mm EMC FO Package (12mm x 12mm) 3mm 1.94mm CHIP4 CHIP2 CHIP3 3mm 120µm 3mm CHIP1 CHIP2 5mm µm 1.94mm 12mm Line width/spacing of: 1st RDL are 10/10µm 2 nd RDL are 15/15µm

28 340mm 9mm TV9P (Phase-I) 529 (23x23) 340mm 5mm 9mm 5mm 9mm 9mm

29 TV9 (Phase-I) 14mm 9mm FO Package (14mm x 14mm) 9mm EMC CHIP 2.5mm 14mm Line width/spacing of: 1st RDL are 5/5µm 2 nd RDL are 10/10µm 3 rd RDL are 15/15µm 2.5mm

30 340mm TVPSiP (Phase-I) 676 (26x26) 340mm 3.88mm 8.12mm 8.12mm 3.88mm 14mm 14mm

31 TVSiP (Phase-I) 1.94mm 12mm 5mm 3mm 120µm 3mm 3mm 1.94mm EMC FO Package (12mm x 12mm) 3mm 1.94mm CHIP4 CHIP2 CHIP3 3mm 120µm 3mm CHIP1 CHIP2 5mm 1.94mm 12mm Line width/spacing of: 1st RDL are 10/10µm 2 nd RDL are 15/15µm

32 50µm 50µm First-Layer of RDL (Die-Down) (Polymer + ECD) 20µm Top-View 10µm (Die-down) Daisy Chain (RDL) X-View CHIP 4µm Top-View CHIP 50µm 70µm Daisy Chain

33 70µm 50µm 50µm First-Layer of RDL (Die-Up) (Polymer + ECD) 20µm 5µm (Die-up) Daisy Chain (RDL) 60µm Si Top-View CHIP 50µm Daisy Chain 70µm Daisy-Chain 150µm

34 50µm 30µm First-Layer of RDL (PCB +LDI) Top-View 10µm (Die-down) Daisy Chain (RDL) X-View CHIP 15µm Top-View CHIP 50µm Daisy Chain

35 Die-Up Die-Down Die-Down CHIP C4 C3 C4 C3 C1 C2 C1 C2 Line width/spacing of: 1st RDL are 5/5µm 2 nd RDL are 10/10µm 3 rd RDL are 15/15µm Line width/spacing of: 1st RDL are 10/10µm 2 nd RDL are 15/15µm Line width/spacing of: 1st RDL are 10/10µm 2 nd RDL are 15/15µm P&P RDL NUCLEUS (ASM) Molding ORCAS (ASM) ORCAS (ASM) ORCAS (ASM) Ball Mount PCA Material JCAP DEK (ASM) Huawei DOW, Indium NUCLEUS (ASM), SiPLACE (ASM) Unimicron, JCAP DEK (ASM) Huawei DOW, Indium NUCLEUS (ASM), SiPLACE (ASM) Unimicron, JCAP (?) DEK (ASM) Huawei DOW, Indium

36 Phase - II

37 1.94mm 5mm 12mm 120µm 3mm 457mm (18 ) 3mm 3mm 1.94mm TV2PSiP (Phase-II) 1813 (49x37) 11mm 6.5mm 610mm (24 ) 49 x 37 = 1813 units (packages) FO Package (12mm x 12mm) 1.94mm EMC 3mm CHIP4 120µm 3mm CHIP3 CHIP 2 3mm CHIP1 CHIP2 5mm 1.94mm 12mm Line width/spacing of RDL are 10/10µm

38 457mm (18 ) 610mm (24 ) 1813 SiPs Line width/spacing of RDL are 10/10µm P&P NUCLEUS (ASM) SiPLACE (ASM) RDL Molding Ball Mount PCA Material Unimicron, JCAP (?) ORCAS (ASM) DEK (ASM) Huawei DOW, Indium

39 Company Task Assignments

40 Test-Chip Wafer Fabrication Layout the Test Chips All Test-Chip Wafer Fabricate the Test-Chip Wafers Sub-contract DOW provide the materials for making the test-chip wafers Capacitor Backgrind the Test-Chip Wafers Dice the Test- Chip Wafers Sub-contract Sub-contract

41 9mm Peripheral pads at 150µm pitch (Staggered) 9mm x 9mm Test Chip 50µm 70µm 9mm Polymer Contact pad Passivation 60µm UBM (Ti/Cu) Peripheral pads at 150µm pitch (Staggered) Si DAF 50µm CHIP 70µm Area-array pads at 150µm pitch CHIP Daisy-Chain > 2500 pads 150µm Note: Before dicing the test-chip wafer, laminate a die-attach film (DAF) on the back-side of the test-chip wafer.

42 70µm 50µm 5mm 5mm x 5m Test Chip 5mm 50µm Passivation CHIP Si For the 5x5mm chip, there are ~200 peripheral pads on a 100µm-pitch. 50µm CHIP 70µm Daisy-Chain Peripheral s 100µm

43 70µm 50µm 3mm 3mm x 3mm Test Chip 3mm 50µm Passivation CHIP Si For the 3x3mm chip, there are ~120 peripheral pads on a 100µm-pitch. 50µm CHIP 70µm Daisy-Chain Peripheral s 100µm

44 TV9W (Phase-I) >300 Glass or Si Carrier Wafer (ASM) P&P the Test Chips (face-up) on the Carrier Wafer (NUCLEUS) Compression Molding the Test Chips on Carrier Wafer (ORCAS) Backgrind the EMC and Polymer to explore the Cu Contact (JCAP) Build-up the RDLs with Polymer and ECD (JCAP) DOW provide materials on making the RDLs Indium provide flux on ball mounting Solder-Ball Mounting (DEK) Remove the Carrier Wafer (ASM) Dicing the Molded Wafer into Individual Packages (JCAP)

45 TVWSiP (Phase-I) >350 Si Carrier Wafer with 2-side thermal release tape (ASM) P&P the Test Chips (face-down) on the Carrier Wafer with NUCLEUS P&P the Test Chips (face-down) on the Carrier Wafer with SiPLACE P&P the Capacitors with SiPLACE Compression Molding the Test Chips and Capacitors on Carrier Wafer (ORCAS) Remove the Carrier Wafer and tape (?) RDLs with Polymer/ECD JCAP RDLs with PCB/LDI UNIMICRON DOW provide materials on making the RDLs Indium provide flux on ball mounting Solder-Ball Mounting (DEK) Dicing the Molded Wafer into Individual Packages (JCAP)

46 TVPSiP (Phase-I) 676 (26x26) Steel Panel with 2-side thermal release tape (ASM) P&P the Test Chips (face-down) on the Panel with NUCLEUS P&P the Test Chips (face-down) on the Panel with SiPLACE P&P the Capacitors with SiPLACE Compression Molding the Test Chips and Capacitors on the Panel (ORCAS) Remove the Panel and tape (?) DOW provide materials on making the RDLs Indium provide flux on ball mounting RDLs with PCB/LDI UNIMICRON RDLs with Polymer/ECD JCAP (?) Solder-Ball Mounting (DEK) Dicing the Panel into Individual Packages (UNIMICRON)

47 5mm 3mm 14mm 9mm 12mm 3mm Component Qualification Test A test socket for BGA-like packages: 9mm CHIP CHIP4 3mm CHIP3 P2 CHIP1 CHIP2 5mm 14mm 12mm

48 Test Board Layout, Fabrication, Assembly and Reliability Test JESD22-B111 for Drop Test JESD22-A104D for Temperature Cycling Test Huawei Indium PCB

49 Things Needed to be Discussed For the large chip (face-up) Die-attach film (kind, company, de-bond, shelf life, etc.) For the large chip (face-up) Polymer (kind, company, can the polymer backgrind with the EMC? Transparent for alignment mark?) Carrier materials glass, Si, metal such as steel, etc. P&P accuracy for large die with fine (5µm) line width/spacing P&P accuracy for small die with 10µm line width/spacing EMC Sumitomo (solid) and Nagase (liquid) RDL JCAP say something RDL Unimicron say something RDL DOW say something Solder-Ball Mounting DEK say something Removing the carrier wafer (large chip) De-bond the die-attach film Dicing the molded wafer into individual package Test socket for the 14x14mm package and the 12x12mm package Test board layout, fabrication, assembly, and reliability tests Huawei and Indium 0402 Termination metal

50 Thank you very much for your attention!