Intel Q3GM ES 32 nm CPU (from Core i5 660)

Size: px

Start display at page:

Download "Intel Q3GM ES 32 nm CPU (from Core i5 660)"

Meagan Ball
7 years ago
Views:

1 Intel Q3GM ES Layout and DFM Feature Analysis For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor and electronics technology, please call Sales at Chipworks Richmond Road, Suite 500, Ottawa, ON K2H 5B7, Canada Tel: Fax:

semiconductor and electronics technology, please call Sales at Chipworks.

2 Layout and DFM Feature Analysis Table of Contents 1.1 List of Figures 1.2 List of Tables 1.3 Company Profile 1.4 Introduction 1.5 Device and Report Overview 1.6 Device Summary 1.7 Brief Comparison to Intel 45 nm Process Technology 2 Device Overview 2.1 Package and Die 2.2 CPU (8PWSCA Die Markings) Die Features and Die Utilization 3 Estimated Design Rules 3. and Summary Tables 4 Layer-by-Layer Design Rule and DFM Analysis Metal 8, Metal 9, and Via 8s 4.3 Metal 7 through Metal 4 and Via 7s through Via 4s 4.4 Metal 3 Through Metal 1 and Via 3s Through Via 1s 4.5 Via 0s, Metal 0, Contacts, and Transistor Gates 4.6 Isolation and Substrate 5 Selected Layout Feature Analysis Logic Region Features 5.3 L3 Cache SRAM 6 ICWorks Surveyor Circuit Layout Analysis Bevel Sample Layout Files 6.3 Targeted Region Files (L1/L2/L3 Cache, Standard Logic, and I/Os) 7 References 8 Statement of Measurement Uncertainty and Scope Variation About Chipworks

and Summary Tables 4 Layer-by-Layer Design Rule and DFM Analysis 4. 4.2 Metal 8, Metal 9, and Via 8s 4.3 Metal 7 through Metal 4 and Via 7s through Via 4s 4.

3 Overview List of Figures ICWorks Surveyor Folders Example ICWorks Surveyor Window Bevel Sample Example ICWorks Surveyor Window Interactive Regions 2 Device Overview Package Top Package and Lid CPU Die Photograph (8PWSCA Die Markings) PWSCA Die Markings PWSCA Die Markings (RDL Removed) PWSCA Die Photograph (RDL Removed) Metal 1 CPU Die Photograph CPU Die Corner A CPU Die Corner B CPU Die Corner C CPU Die Corner D High Density Bump Via Windows (on CPU) CPU Die Utilization Analysis CPU Standard Logic Cell Size 3 Estimated Design Rules Interconnect Measurement Reference Interconnect Scaling Minimum Feature Size/Pitch 4 Layer-by-Layer Design Rule and DFM Analysis General Metal 9 Patterning Metal 9 Minimum Feature Size Via 8 Distribution Via 8 Pitch General Metal 8 Patterning (A) General Metal 8 Patterning (B) Metal 8 Minimum Feature Size Metal 8 Orthogonal Routing Metal 8 Minimum Gap Via 7 Overview Via 7 Distribution Via 7 Pitch Metal 7 Minimum Feature Size Metal 7 Orthogonal Routing Via 6 Pitch General Metal 6 Patterning Metal 6 Minimum Feature Size Metal 6 Orthogonal Routing

2.1 CPU Die Corner A 2.2.2 CPU Die Corner B 2.2.3 CPU Die Corner C 2.2.4 CPU Die Corner D 2.2.5 High Density Bump Via Windows (on CPU) 2.2.6 CPU Die Utilization Analysis 2.2.7 CPU Standard Logic Cell Size 3 Estimated Design Rules 3.

4 Overview Via 5 Distribution Via 5 Pitch Metal 5 Minimum Feature Size, Orthogonal Routing Metal 5 Minimum Line End-to-End Gap Planar TEM of Metal 5 (A) Planar TEM of Metal 5 (B) Via 4 Pitch Planar TEM of Via 4 and Metal Metal 4 Minimum Feature Size Metal 4 Orthogonal Routing Via 3 Distribution Via 3 Pitch Metal 3 Minimum Feature Size Metal 3 Orthogonal Routing Via 2 Pitch Via 2 Distribution Metal 2 Minimum Feature Size Metal 2 Minimum Line End-to-End Gap Via 1 Distribution Via 1 Pitch Metal (Standard Logic Region) Metal 1 Pitch Metal 1 Line End Uniformity (A) Metal 1 Line End Uniformity (B) Metal Metal 1 Line End-to-End Gap Via 0 Pitch Metal 0 Minimum Feature Size Metal 0 Distribution Contacted Gate Pitch General Gate and Local Interconnect Layout Gate End Uniformity Planar TEM of PMOS Gate Fingers Planar TEM of Dummy Gate Structure (PMOS Gate Metal) Planar TEM of NMOS Gate Fingers Planar TEM of Dummy NMOS Gate Multiple Width Gate Metal TEM Micrograph Cross Section of Wide NMOS Gate Diffusion Level Layout (A) Diffusion Level Layout (B)

4.4 Metal 3 Orthogonal Routing 4.4.5 Via 2 Pitch 4.4.6 Via 2 Distribution 4.4.7 Metal 2 Minimum Feature Size 4.4.8 Metal 2 Minimum Line End-to-End Gap 4.4.9 Via 1 Distribution 4.4.10 Via 1 Pitch 4.4.11 Metal (Standard Logic Region) 4.

5 Overview Selected Layout Feature Analysis Standard Logic Dummy Pattern at Metal Standard Logic Dummy Pattern at Gate Level Standard Logic Dummy Pattern at Diffusion Alignment Feature at Metal Alignment Feature at Gate Level Alignment Feature at Diffusion Edge of L3 Cache Array Metal Edge of L3 Cache Array Gate Level Edge of L3 Cache Array Diffusion L3 Cache SRAM at Metal L3 Cache SRAM at Metal L3 Cache SRAM at Metal L3 Cache SRAM at Gate Level L3 Cache SRAM at Diffusion Level Planar TEM of L3 Cache at Metal Planar TEM of L3 Cache at Gate/Metal Level Planar TEM of L3 Cache at Gate/W Contact Level Planar TEM of L3 Cache at Active Silicon Level 6 ICWorks Surveyor Circuit Layout Analysis Bevel Sample Location Bevel Sample Analysis Sites Interactive Layer Analysis Imaging Sites Example ICWorks Surveyor Screen Shot All Levels 1.2 List of Tables Available Companion Reports on Intel 32 nm Device Identification PWSCA Die Summary Comparison of Intel 45 nm Process to 32 nm Process 2 Device Overview CPU Die Utilization CPU Package, Die, and Standard Logic Cell Size 3 Estimated Design Rules Estimated Interconnect Design Rules Estimated Via and Contact Design Rules Estimated Transistor and Isolation Design Rules 4 Layer-by-Layer Design Rule and DFM Analysis Observed Gate Finger Widths 6 ICWorks Surveyor Circuit Layout Analysis Bevel Site and Software Folder Sample Reference Targeted Region Interactive Files

3.5 L3 Cache SRAM at Metal 2 5.3.6 L3 Cache SRAM at Metal 1 5.3.7 L3 Cache SRAM at Gate Level 5.3.8 L3 Cache SRAM at Diffusion Level 5.3.9 Planar TEM of L3 Cache at Metal 0 5.3.10 Planar TEM of L3 Cache at Gate/Metal Level 5.

6 About Chipworks Chipworks is the recognized leader in reverse engineering and patent infringement analysis of semiconductors and electronic systems. The company s ability to analyze the circuitry and physical composition of these systems makes them a key partner in the success of the world s largest semiconductor and microelectronics companies. Intellectual property groups and their legal counsel trust Chipworks for success in patent licensing and litigation earning hundreds of millions of dollars in patent licenses, and saving as much in royalty payments. Research & Development and Product Management rely on Chipworks for success in new product design and launch, saving hundreds of millions of dollars in design, and earning even more through superior product design and faster launches. Contact Chipworks To find out more information on this report, or any other reports in our library, please contact Chipworks at: Chipworks 3685 Richmond Rd. Suite 500 Ottawa, Ontario K2H 5B7 Canada T: F: Web site: info@chipworks.com Please send any feedback to feedback@chipworks.com

Intellectual property groups and their legal counsel trust Chipworks for success in patent licensing and litigation earning hundreds of millions of dollars in patent licenses, and saving as much in

Intel Q3GM ES 32 nm CPU (from Core i5 660)

Intel Q3GM ES 32 nm CPU (from Core i5 660) Intel Q3GM ES Structural Analysis For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor and electronics technology, please call