Chapter 15: Design Examples

Transcription

1 Chapter 15: Design Examples Prof. Ming-Bo Lin Department of Electronic Engineering National Taiwan University of Science and Technology Digital System Designs and Practices Using Verilog HDL and , John Wiley 15-1

2 Syllabus Objectives Bus Data transfer General-purpose input and output Timers Universal asynchronous receiver and transmitter A simple CPU design Digital System Designs and Practices Using Verilog HDL and , John Wiley 15-2

3 Objectives After completing this chapter, you will be able to: Describe basic structures of µp systems Understand the basic operations of bus structures Understand the essential operations of data transfer Understand the design principles of GPIOs Understand the design principles of timers Understand the design principles of UARTs Describe the design principles of CPUs Digital System Designs and Practices Using Verilog HDL and , John Wiley 15-3

4 Syllabus Objectives Bus A µp system architecture Bus structures Bus arbitration Data transfer General-purpose input and output Timers Universal asynchronous receiver and transmitter A simple CPU design Digital System Designs and Practices Using Verilog HDL and , John Wiley 15-4

5 A Basic µp System Digital System Designs and Practices Using Verilog HDL and , John Wiley 15-5

6 Syllabus Objectives Bus A µp system architecture Bus structures Bus arbitration Data transfer General-purpose input and output Timers Universal asynchronous receiver and transmitter A simple CPU design Digital System Designs and Practices Using Verilog HDL and , John Wiley 15-6

7 Bus Structures Tristate bus using tristate buffers often called bus for short Multiplexer-based bus using multiplexers Digital System Designs and Practices Using Verilog HDL and , John Wiley 15-7

8 A Tristate Bus Digital System Designs and Practices Using Verilog HDL and , John Wiley 15-8

9 A Tristate Bus Example // a tristate bus example module tristate_bus (data, enable, qout); parameter N = 2; // define bus width input enable; input [N-1:0] data; output [N-1:0] qout; wire [N-1:0] qout; // the body of tristate bus assign qout = enable? data : {N{1'bz}}; endmodule Digital System Designs and Practices Using Verilog HDL and , John Wiley 15-9

10 A Bidirectional Bus Example // a bidirectional bus example module bidirectional_bus (data_to_bus, send, receive, data_from_bus, qout); parameter N = 2; // define bus width input send, receive; input [N-1:0] data_to_bus; output [N-1:0] data_from_bus; inout [N-1:0] qout; // bidirectional bus wire [N-1:0] qout, data_from_bus; // the body of tristate bus assign data_from_bus = receive? qout : {N{1'bz}}; assign qout = send? data_to_bus : {N{1'bz}}; endmodule Digital System Designs and Practices Using Verilog HDL and , John Wiley 15-10

11 A Multiplexer-Based Bus Digital System Designs and Practices Using Verilog HDL and , John Wiley 15-11

12 Syllabus Objectives Bus A µp system architecture Bus structures Bus arbitration Data transfer General-purpose input and output Timers Universal asynchronous receiver and transmitter A simple CPU design Digital System Designs and Practices Using Verilog HDL and , John Wiley 15-12

13 Daisy-Chain Arbitration Types of bus arbitration schemes daisy-chain arbitration radial arbitration Digital System Designs and Practices Using Verilog HDL and , John Wiley 15-13

14 Syllabus Objectives Bus Data transfer Synchronous transfer mode Asynchronous transfer mode General-purpose input and output Timers Universal asynchronous receiver and transmitter A simple CPU design Digital System Designs and Practices Using Verilog HDL and , John Wiley 15-14

15 Data Transfer Modes Data transfer modes synchronous mode asynchronous mode The actual data can be transferred in parallel: a bundle of signals in parallel serial: a stream of bits Digital System Designs and Practices Using Verilog HDL and , John Wiley 15-15

16 Synchronously Parallel Data Transfers Chapter 15: Design Examples Each data transfer is synchronous with clock signal Bus master Bus slave Two types Single-clock bus cycle Multiple-clock bus cycle Digital System Designs and Practices Using Verilog HDL and , John Wiley 15-16

17 Synchronously Parallel Data Transfers Chapter 15: Design Examples Digital System Designs and Practices Using Verilog HDL and , John Wiley 15-17

18 Synchronously Serial Data Transfers Explicitly clocking scheme Implicitly clocking scheme Chapter 15: Design Examples Digital System Designs and Practices Using Verilog HDL and , John Wiley 15-18

19 Synchronously Serial Data Transfers Examples Chapter 15: Design Examples Digital System Designs and Practices Using Verilog HDL and , John Wiley 15-19

20 Syllabus Objectives Bus Data transfer Synchronous transfer mode Asynchronous transfer mode General-purpose input and output Timers Universal asynchronous receiver and transmitter A simple CPU design Digital System Designs and Practices Using Verilog HDL and , John Wiley 15-20

21 Asynchronous Data Transfers Each data transfer occurs at random Control approaches strobe scheme handshaking scheme Digital System Designs and Practices Using Verilog HDL and , John Wiley 15-21

22 Strobe Digital System Designs and Practices Using Verilog HDL and , John Wiley 15-22

23 Handshaking Four events are proceeded in a cycle order ready (request) data valid data acceptance acknowledge Digital System Designs and Practices Using Verilog HDL and , John Wiley 15-23

24 Handshaking Two types source-initiated transfer destination-initiated transfer Digital System Designs and Practices Using Verilog HDL and , John Wiley 15-24

25 Asynchronously Serial Data Transfers Transmitter Receiver Chapter 15: Design Examples Digital System Designs and Practices Using Verilog HDL and , John Wiley 15-25

26 Asynchronously Serial Data Transfers Chapter 15: Design Examples Digital System Designs and Practices Using Verilog HDL and , John Wiley 15-26

27 Syllabus Objectives Bus Data transfer General-purpose input and output Timers Universal asynchronous receiver and transmitter A simple CPU design Digital System Designs and Practices Using Verilog HDL and , John Wiley 15-27

28 General-Purpose Input and Output Devices The general-purpose input and output (GPIO) input output bidirectional Digital System Designs and Practices Using Verilog HDL and , John Wiley 15-28

29 General-Purpose Input and Output Devices An example of 8-bit GPIO Digital System Designs and Practices Using Verilog HDL and , John Wiley 15-29

30 Design Issues of GPIO Devices Readback capability of PORT register Group or individual bit control Selection the value of DDR Handshaking control Readback capability of DDR Input latch Input/Output pull-up Drive capability Digital System Designs and Practices Using Verilog HDL and , John Wiley 15-30

31 General-Purpose Input and Output Devices The ith-bit of two GPIO examples Digital System Designs and Practices Using Verilog HDL and , John Wiley 15-31

32 Syllabus Objectives Bus Data transfer General-purpose input and output Timers Interface Basic operation modes Advanced operation modes Universal asynchronous receiver and transmitter A simple CPU design Digital System Designs and Practices Using Verilog HDL and , John Wiley 15-32

33 Timers Important applications time-delay creation event counting time measurement period measurement pulse-width measurement time-of-day tracking waveform generation periodic interrupt generation Digital System Designs and Practices Using Verilog HDL and , John Wiley 15-33

34 Timers Digital System Designs and Practices Using Verilog HDL and , John Wiley 15-34

35 Syllabus Objectives Bus Data transfer General-purpose input and output Timers Interface Basic operation modes Universal asynchronous receiver and transmitter A simple CPU design Digital System Designs and Practices Using Verilog HDL and , John Wiley 15-35

36 Basic Timer Operations Timers What is a timer? What is a counter? What is a programmable counter? What is a programmable timer? Basic operation modes terminal count (binary/bcd event counter) rate generation (digital) monostable (or called one-shot) square-wave generation Digital System Designs and Practices Using Verilog HDL and , John Wiley 15-36

37 Terminal Count Digital System Designs and Practices Using Verilog HDL and , John Wiley 15-37

38 Rate Generation Digital System Designs and Practices Using Verilog HDL and , John Wiley 15-38

39 Retriggerable Monostable (One-Shot) Operation Digital System Designs and Practices Using Verilog HDL and , John Wiley 15-39

40 Square-Wave Generation clk (4) (4) out Latch register = 4 (a) A waveform example of square-wave mode wr latch_load Data bus Latch rd clk gate timer_load generator timer_load Shift plus LSB timer_enable timer timer is 1 D Q CK out logic out (b) Block diagram of square-wave mode Digital System Designs and Practices Using Verilog HDL and , John Wiley 15-40

41 Syllabus Objectives Bus Data transfer General-purpose input and output Timers Universal asynchronous receiver and transmitter Interface Basic transmitter structure Basic receiver structure Baud-rate generators A simple CPU design Digital System Designs and Practices Using Verilog HDL and , John Wiley 15-41

42 UARTs Hardware model the CPU interface the I/O interface Software model receiver data register (RDR) transmitter data register (TDR) status register (SR) control register (CR) Digital System Designs and Practices Using Verilog HDL and , John Wiley 15-42

43 UARTs Digital System Designs and Practices Using Verilog HDL and , John Wiley 15-43

44 Syllabus Objectives Bus Data transfer General-purpose input and output Timers Universal asynchronous receiver and transmitter Interface Basic transmitter structure Basic receiver structure Baud-rate generators A simple CPU design Digital System Designs and Practices Using Verilog HDL and , John Wiley 15-44

45 Design Issues of UARTs Baud rate Sampling clock frequency Stop bits Parity check Digital System Designs and Practices Using Verilog HDL and , John Wiley 15-45

46 A Transmitter of UARTs The transmitter a transmitter shift data register (TSDR) a TDR empty flag (TE) a transmitter control circuit a TDR parity generator Digital System Designs and Practices Using Verilog HDL and , John Wiley 15-46

47 A Transmitter of UARTs Digital System Designs and Practices Using Verilog HDL and , John Wiley 15-47

48 Syllabus Objectives Bus Data transfer General-purpose input and output Timers Universal asynchronous receiver and transmitter Interface Basic transmitter structure Basic receiver structure Baud-rate generators A simple CPU design Digital System Designs and Practices Using Verilog HDL and , John Wiley 15-48

49 A Receiver of UARTs The receiver a RDR a receiver shift data register (RSDR) a status register a receiver control circuit Digital System Designs and Practices Using Verilog HDL and , John Wiley 15-49

50 A Receiver of UARTs Digital System Designs and Practices Using Verilog HDL and , John Wiley 15-50

51 Syllabus Objectives Bus Data transfer General-purpose input and output Timers Universal asynchronous receiver and transmitter Interface Basic transmitter structure Basic receiver structure Baud-rate generators A simple CPU design Digital System Designs and Practices Using Verilog HDL and , John Wiley 15-51

52 Baud-Rate Generators The baud-rate generator provides TxC and RxC Design approaches Multiplexer-based approach Timer-based approach Others Digital System Designs and Practices Using Verilog HDL and , John Wiley 15-52

53 Baud-Rate Generators Digital System Designs and Practices Using Verilog HDL and , John Wiley 15-53

54 Syllabus Objectives Bus Data transfer General-purpose input and output Timers Universal asynchronous receiver and transmitter A simple CPU design Programming model Datapath design Control unit design Digital System Designs and Practices Using Verilog HDL and , John Wiley 15-54

55 CPU Basic Operations Digital System Designs and Practices Using Verilog HDL and , John Wiley 15-55

56 The Software Model of CPU The programming model Instruction formats Addressing modes Instruction set Digital System Designs and Practices Using Verilog HDL and , John Wiley 15-56

57 The Programming Mode Digital System Designs and Practices Using Verilog HDL and , John Wiley 15-57

58 Instruction Formats Two major parts Opcode Operand Digital System Designs and Practices Using Verilog HDL and , John Wiley 15-58

59 Addressing Modes The ways that operands are fetched register indexed register indirect immediate Digital System Designs and Practices Using Verilog HDL and , John Wiley 15-59

60 The Instruction Set Double-operand instruction set Digital System Designs and Practices Using Verilog HDL and , John Wiley 15-60

61 The Instruction Set Single-operand instruction set Digital System Designs and Practices Using Verilog HDL and , John Wiley 15-61

62 The Instruction Set Jump instruction set Digital System Designs and Practices Using Verilog HDL and , John Wiley 15-62

63 Syllabus Objectives Bus Data transfer General-purpose input and output Timers Universal asynchronous receiver and transmitter A simple CPU design Programming model Datapath design Control unit design Digital System Designs and Practices Using Verilog HDL and , John Wiley 15-63

64 A Datapath Design Digital System Designs and Practices Using Verilog HDL and , John Wiley 15-64

65 ALU Functions Digital System Designs and Practices Using Verilog HDL and , John Wiley 15-65

66 Syllabus Objectives Bus Data transfer General-purpose input and output Timers Universal asynchronous receiver and transmitter A simple CPU design Programming model Datapath design Control unit design Digital System Designs and Practices Using Verilog HDL and , John Wiley 15-66

67 A Control Unit The decoder-based approach Digital System Designs and Practices Using Verilog HDL and , John Wiley 15-67

68 A Control Unit A better approach Digital System Designs and Practices Using Verilog HDL and , John Wiley 15-68

69 A Control Unit The operations of T3 and T4 are determined separately by each instruction Digital System Designs and Practices Using Verilog HDL and , John Wiley 15-69