Digital Logic Design: An Embedded Systems Approach Using VHDL. Chapter 3 Numeric Basics

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1 Dgtal Logc Desgn. Chapter 3 6 March 7 Dgtal Logc Desgn: An Embedded Systems Approach Usng VHDL Chapter 3 Numerc Bascs Portons of ths work are from the book, Dgtal Logc Desgn: An Embedded Systems Approach Usng VHDL, by Peter J. Ashenden, publshed by Morgan Kaufmann Publshers, Copyrght 7 Elsever Inc. All rghts reserved. Numerc Bascs Representng and processng numerc data s a common requrement unsgned ntegers sgned ntegers fxed-pont real numbers floatng-pont real numbers complex numbers Dgtal Logc Desgn. Chapter 3 KU EECS 4/4

2 Dgtal Logc Desgn. Chapter 3 6 March 7 Unsgned Integers Non-negatve numbers (ncludng ) Represent real-world data e.g., temperature, poston, tme, Also used n controllng operaton of a dgtal system e.g., countng teratons, table ndces Coded usng unsgned bnary (base ) representaton analogous to decmal representaton Dgtal Logc Desgn. Chapter 3 3 Bnary Representaton Decmal: base 4 = Bnary: base 4 = = In general, a number x s represented usng n bts as x n, x n,, x, where x = x n n n + xn + + x Dgtal Logc Desgn. Chapter 3 4 KU EECS 4/4

3 Dgtal Logc Desgn. Chapter 3 6 March 7 Bnary Representaton Unsgned bnary s a code for numbers n bts: represent numbers from to n : ; n : To represent x: x N, need log N bts Computers use 8-bt bytes:,, 55 3-bt words:,, ~4 bllon Dgtal crcuts can use what ever sze s approprate Dgtal Logc Desgn. Chapter 3 5 Unsgned Integers n VHDL Package numerc_std provdes unsgned vector type and arthmetc operatons lbrary eee; use eee.std_logc_64.all, eee.numerc_std.all; entty multplexer_6bt_4_to_ s port ( a, a, a, a3 : n unsgned (5 downto ); sel : n std_logc_vector ( downto ); z : out unsgned (5 downto ) ); end entty multplexer_6bt_4_to_; archtecture eqn of multplexer_6bt_4_to_ s begn wth sel select z <= a when "", a when "", a when "", a3 when others; end archtecture eqn; Dgtal Logc Desgn. Chapter 3 6 KU EECS 4/4 3

4 Dgtal Logc Desgn. Chapter 3 6 March 7 Octal and Hexadecmal Short-hand notatons for vectors of bts Octal (base 8) Each group of 3 bts represented by a dgt :, :, :,, 7: 53 8 = = 33 8 Hex (base 6) Each group of 4 bts represented by a dgt :,, 9:, A:,, F: 3CE 6 = = CB 6 Dgtal Logc Desgn. Chapter 3 7 Extendng Unsgned Numbers To extend an n-bt number to m bts Add leadng bts e.g., 7 = = x() x() x(n ) y() y) y(n ) y(n) y(m ) y(m ) sgnal x : unsgned(3 downto ); sgnal y : unsgned(7 downto ); y <= "" & x; y <= resze(x, 8); Dgtal Logc Desgn. Chapter 3 8 KU EECS 4/4 4

5 Dgtal Logc Desgn. Chapter 3 6 March 7 Truncatng Unsgned Numbers To truncate from m bts to n bts Dscard leftmost bts Value s preserved f dscarded bts are Result s x mod n y() y) x() x() x <= y(3 downto ); y(n ) y(n) y(m ) y(m ) x(n ) x <= resze(y, 4); Dgtal Logc Desgn. Chapter 3 9 Unsgned Addton Performed n the same way as decmal carry bts overflow Dgtal Logc Desgn. Chapter 3 KU EECS 4/4 5

6 Dgtal Logc Desgn. Chapter 3 6 March 7 Addton Crcuts Half adder for least-sgnfcant bts s = x y = x y c Full adder c for remanng bts s = = x ( x y ) c y + ( x y ) c x y c s c + + Dgtal Logc Desgn. Chapter 3 Rpple-Carry Adder Full adder for each bt, c = x n y n x y x y x y c n full adder c n c + full adder c c full adder c full adder c s n s n s s s overflow Worst-case delay from x, y to s n carry must rpple through ntervenng stages, affectng sum bts Dgtal Logc Desgn. Chapter 3 KU EECS 4/4 6

7 Dgtal Logc Desgn. Chapter 3 6 March 7 Improvng Adder Performance Carry kll: Carry propagate: Carry generate: Adder equatons k p g = x y = x y = x y x y c s c + s = p c c+ = g + p c Dgtal Logc Desgn. Chapter 3 3 Fast-Carry-Chan Adder Also called Manchester adder x y x y +V p g p k c + c c + c Xlnx FPGAs nclude ths structure s s Dgtal Logc Desgn. Chapter 3 4 KU EECS 4/4 7

8 Dgtal Logc Desgn. Chapter 3 6 March 7 Carry Lookahead c + = g + p c c = g + p c c ( g + p c ) = g + p g + p p = g + p c c 3 = g + p g + p p g + p p p c c 4 = g 3 + p 3 + p p 3 g + p p g 3 p + p 3 g p p p c Dgtal Logc Desgn. Chapter 3 5 Carry-Lookahead Adder Avods chaned carry crcut x 3 y 3 x y x y x y g 3 p 3 g p g p g p c 4 carry-lookahead generator c p 3 c 3 p c p c p s 3 s s s Use multlevel lookahead for wder numbers Dgtal Logc Desgn. Chapter 3 6 KU EECS 4/4 8

9 Dgtal Logc Desgn. Chapter 3 6 March 7 Other Optmzed Adders Other adders are based on other reformulatons of adder equatons Choce of adder depends on constrants e.g., rpple-carry has low area, so s ok for low performance crcuts e.g., Manchester adder ok n FPGAs that nclude carry-chan crcuts Dgtal Logc Desgn. Chapter 3 7 Adders n VHDL Use operatons from numerc_std lbrary eee; use eee.numerc_std.all;... sgnal x, y, s: unsgned(7 downto );... s <= a + b; sgnal tmp_result : unsgned(8 downto ); sgnal c : std_logc;... tmp_result <= ('' & a) + ('' & b); c <= tmp_result(8); s <= tmp_result(7 downto ); Dgtal Logc Desgn. Chapter 3 8 KU EECS 4/4 9

10 Dgtal Logc Desgn. Chapter 3 6 March 7 Unsgned Subtracton As n decmal borrow bts Dgtal Logc Desgn. Chapter 3 9 Subtracton Crcuts For least-sgnfcant bts d = x y b = x y For remanng bts b + d = ( x y ) b = x y + ( x y ) b x y b s b + Dgtal Logc Desgn. Chapter 3 KU EECS 4/4

11 Dgtal Logc Desgn. Chapter 3 6 March 7 Adder/Subtracter Crcuts Many systems add and subtract Trck: use complemented borrows c + s = = x ( x y ) c y + ( x y ) c Addton b + d = = x Subtracton ( x y ) b y + ( x y ) b Same hardware can perform both For subtracton: complement y, set b = Dgtal Logc Desgn. Chapter 3 Adder/Subtracter Crcuts x n x x y n y y add/sub ovf/und x n x x y n y c n adder y c s n s s s n /d n s /d s /d Adder can be any of those we have seen depends on constrants Dgtal Logc Desgn. Chapter 3 KU EECS 4/4

12 Dgtal Logc Desgn. Chapter 3 6 March 7 Subtracton n VHDL lbrary eee; use eee.std_logc_64.all, eee.numerc_std.all; entty adder_subtracter s port ( x, y : n unsgned( downto ); s : out unsgned( downto ); mode : n std_logc; error : out std_logc ); end entty adder_subtracter; archtecture behavor of adder_subtracter s sgnal s_tmp : unsgned( downto ); begn s_tmp <= ('' & x) + ('' & y) when mode = '' else ('' & x) - ('' & y); s <= s_tmp( downto ); error <= s_tmp(); end archtecture behavor; Dgtal Logc Desgn. Chapter 3 3 Increment and Decrement Addng : set y = and c = s = x c c+ = x c These are equatons for a half adder x n c n x c x c x +V c n half adder c + half adder c half adder half adder s n s n s s s Smlarly for decrementng: subtractng Dgtal Logc Desgn. Chapter 3 4 KU EECS 4/4

13 Dgtal Logc Desgn. Chapter 3 6 March 7 Increment/Decrement n VHDL Just add or subtract sgnal x, s: unsgned(5 downto );... s <= x + ; -- ncrement x s <= x ; -- decrement x Note: (nteger), not '' (bt) Dgtal Logc Desgn. Chapter 3 5 Equalty Comparson XNOR gate: equalty of two bts Apply btwse to two unsgned numbers x y x y x n y n eq In VHDL, x = y gves a boolean result false or true can't assgn to a std_logc sgnal eq <= '' when x = y else ''; Dgtal Logc Desgn. Chapter 3 6 KU EECS 4/4 3

14 Dgtal Logc Desgn. Chapter 3 6 March 7 Inequalty Comparson Magntude comparator for x > y x n y n x n > y n x n = y n gt x n y n x n > y n x n = y n x n > y n x y x > y x > y x = y x y x > y Dgtal Logc Desgn. Chapter 3 7 Comparson Example n VHDL Thermostat wth target termperature Heater or cooler on when actual temperature s more than 5 from target entty thermostat s port ( target, actual : n unsgned(7 downto ); heater_on, cooler_on : out std_logc ); end entty thermostat; archtecture rtl of thermostat s begn heater_on <= '' when actual < target - 5 else ''; cooler_on <= '' when actual > target + 5 else ''; end archtecture rtl; Dgtal Logc Desgn. Chapter 3 8 KU EECS 4/4 4

15 Dgtal Logc Desgn. Chapter 3 6 March 7 Scalng by Power of x = x n n n + xn + + x Ths s x shfted left k places, wth k bts of added on the rght logcal shft left by k places e.g., 3 = Truncate f result must ft n n bts overflow f any truncated bt s not k ( ) + () k x = x + k + n k + n k n + xn + + x + Dgtal Logc Desgn. Chapter 3 9 x Scalng by Power of x = x n n n + xn + + x k n k n k / xn + xn + + xk + xk + + x = Ths s x shfted rght k places, wth k bts truncated on the rght logcal shft rght by k places e.g., / 3 = Fll on the left wth k bts of f result must ft n n bts k Dgtal Logc Desgn. Chapter 3 3 KU EECS 4/4 5

16 Dgtal Logc Desgn. Chapter 3 6 March 7 Scalng n VHDL shft_left and shft_rght operatons result s same sze as operand s = = 9 s = = 9 y <= shft_left(s, ); y <= shft_rght(s, ); y = = 76 y = = 4 Dgtal Logc Desgn. Chapter 3 3 Unsgned Multplcaton xy = x = y n n ( y + y + + y ) n n x n + y n n x n y x s called a partal product f y =, then y x = f y =, then y x s x shfted left by Combnatonal array multpler AND gates form partal products adders form full product + + y x Dgtal Logc Desgn. Chapter 3 3 KU EECS 4/4 6

17 Dgtal Logc Desgn. Chapter 3 6 March 7 Unsgned Multplcaton Adders can be any of those we have seen Optmzed multplers combne parts of adjacent adders y x n x n x x y n y n c n adder y c s n s s s x n x n x x y y x n x n x x y n y n c n adder s n s s x n x n y c s x x y x n x n x x y n y n y c n adder y c s n s s s x n x n x x y x n x n x x y n y x n x n x x y n y n c n adder s s y c s n s p n p n p n+ p n p n p p p Dgtal Logc Desgn. Chapter 3 33 Product Sze Greatest result for n-bt operands: ( n )( n ) = n n n + = n n+ ( ) Requres n bts to avod overflow Addng n-bt and m-bt operands requres n + m bts sgnal x : unsgned(7 downto ); sgnal y : unsgned(3 downto ); sgnal p : unsgned( downto );... p <= x * y; Dgtal Logc Desgn. Chapter 3 34 KU EECS 4/4 7

18 Dgtal Logc Desgn. Chapter 3 6 March 7 Other Unsgned Operatons Dvson, remander More complcated than multplcaton Large crcut area, power Complcated operatons are often performed sequentally n a sequence of steps, one per clock cycle cost/performance/power trade-off Dgtal Logc Desgn. Chapter 3 35 Gray Codes Important for poston encoders Only one bt changes at a tme Segment Code Segment Code See book for n-bt Gray code Dgtal Logc Desgn. Chapter 3 36 KU EECS 4/4 8

19 Dgtal Logc Desgn. Chapter 3 6 March 7 Sgned Integers Postve and negatve numbers (and ) n-bt sgned magntude code bt for sgn: +, n bts for magntude Sgned-magntude rarely used for ntegers now crcuts are too complex Use s-complement bnary code Dgtal Logc Desgn. Chapter 3 37 s-complement Representaton x = x n n n + xn + + x Most-negatve number = n Most-postve number = + n x n = negatve, x n = non-negatve n + + = n Snce Dgtal Logc Desgn. Chapter 3 38 KU EECS 4/4 9

20 Dgtal Logc Desgn. Chapter 3 6 March 7 s-complement Examples = = 53 = = = 75 = = = 8 = +7 Dgtal Logc Desgn. Chapter 3 39 Sgned Integers n VHDL Type sgned from numerc_std lbrary eee; use eee.numerc_std.all;... s : sgned(5 downto ); Types sgned and unsgned are dstnct sgnal s : unsgned( downto ); sgnal s : sgned( downto );... s <= s; -- llegal s <= unsgned(s); -- s s known to be non-negatve... s <= sgned(s); -- s s known to be less than ** Dgtal Logc Desgn. Chapter 3 4 KU EECS 4/4

21 Dgtal Logc Desgn. Chapter 3 6 March 7 Octal and Hex Sgned Integers Don t thnk of sgned octal or hex Just treat octal or hex as shorthand for a vector of bts E.g., 844 s In hex: 34C E.g., 4 s In octal: 76 ( bts) Dgtal Logc Desgn. Chapter 3 4 Reszng Sgned Integers To extend a non-negatve number Add leadng bts e.g., 53 = = To truncate a non-negatve number Dscard leftmost bts, provded dscarded bts are all sgn bt of result s E.g., 4 s Truncatng to 6 bts: error! Dgtal Logc Desgn. Chapter 3 4 KU EECS 4/4

22 Dgtal Logc Desgn. Chapter 3 6 March 7 Reszng Sgned Integers To extend a negatve number Add leadng bts See textbook for proof e.g., 75 = = To truncate a negatve number Dscard leftmost bts, provded dscarded bts are all sgn bt of result s Dgtal Logc Desgn. Chapter 3 43 Reszng Sgned Integers In general, for s-complement ntegers Extend by replcatng sgn bt sgn extenson Truncate by dscardng leadng bts Dscarded bts must all be the same, and the same as the sgn bt of the result x() x() x(n ) y() y) y(n ) y(n) y(m ) y(m ) sgnal x : sgned (7 downto ); sgnal y : sgned (5 downto );... y <= resze(x, y'length);... x <= resze(y, x'length); Dgtal Logc Desgn. Chapter 3 44 KU EECS 4/4

23 Dgtal Logc Desgn. Chapter 3 6 March 7 Sgned Negaton Complement and add x = x + = ( x = Note that n = ( x n = x n + x n n ) n n + ( n + x n + n n + ( x + n x n n + + = x n x ) n n ) + n + + x + + ( x ) + + E.g., 43 s so 43 s + = ) + + Dgtal Logc Desgn. Chapter 3 45 x Sgned Negaton What about negatng n? + = Result s n! Recall range of n-bt numbers s not symmetrc Ether check for overflow, extend by one bt, or ensure ths case can t arse In VHDL: use operator E.g., y <= x; Dgtal Logc Desgn. Chapter 3 46 KU EECS 4/4 3

24 Dgtal Logc Desgn. Chapter 3 6 March 7 Sgned Addton = n n x x n + xn y = y n + yn x n + y = ( xn + yn ) + xn + yn yelds c n Perform addton as for unsgned Overflow f c n dffers from c n See textbook for case analyss Can use the same crcut for sgned and unsgned addton Dgtal Logc Desgn. Chapter 3 47 Sgned Addton Examples 7: 49: 63: 3: 4: 8: : 95: 34: no overflow no overflow no overflow 7: 5: 63: 96: 4: 8: 34: postve overflow negatve overflow no overflow Dgtal Logc Desgn. Chapter 3 48 KU EECS 4/4 4

25 Dgtal Logc Desgn. Chapter 3 6 March 7 Sgned Addton n VHDL Result of + s same sze as operands sgnal v, v : sgned( downto ); sgnal sum : sgned( downto );... sum <= resze(v, sum'length) + resze(v sum'length); To check overflow, compare sgns sgnal x, y, z: sgned(7 downto ); sgnal ovf : std_logc;... z <= x + y; ovf <= (not x(7) and not y(7) and z(7)) or (x(7) and y(7) and not z(7)); Dgtal Logc Desgn. Chapter 3 49 Sgned Subtracton x y = x + ( y) = x + y + Use a s-complement adder Complement y and set c = x n x x y n y y add/sub unsgned ovf/und x n x x y n y c n adder y c sgned ovf c n s n s s s n /d n s /d s /d Dgtal Logc Desgn. Chapter 3 5 KU EECS 4/4 5

26 Dgtal Logc Desgn. Chapter 3 6 March 7 Other Sgned Operatons Increment, decrement same as unsgned Comparson =, same as unsgned >, compare sgn bts usng Multplcaton x n yn Complcated by the need to sgn extend partal products Refer to Further Readng Dgtal Logc Desgn. Chapter 3 5 Scalng Sgned Integers Multplyng by k logcal left shft (as for unsgned) truncate result usng s-complement rules Dvdng by k arthmetc rght shft dscard k bts from the rght, and replcate sgn bt k tmes on the left e.g., s = "" -- 3 shft_rght(s, ) = "" -- 3 / Dgtal Logc Desgn. Chapter 3 5 KU EECS 4/4 6

27 Dgtal Logc Desgn. Chapter 3 6 March 7 Fxed-Pont Numbers Many applcatons use non-ntegers especally sgnal-processng apps Fxed-pont numbers allow for fractonal parts represented as ntegers that are mplctly scaled by a power of can be unsgned or sgned Dgtal Logc Desgn. Chapter 3 53 Postonal Notaton In decmal.4 In bnary = = = Represent as a bt vector: bnary pont s mplct Dgtal Logc Desgn. Chapter 3 54 KU EECS 4/4 7

28 Dgtal Logc Desgn. Chapter 3 6 March 7 Unsgned Fxed-Pont n-bt unsgned fxed-pont m bts before and f bts after bnary pont x = x x m m + + x + x + + Range: to m f Precson: f m may be, gvng fractons only e.g., m= :. f f Dgtal Logc Desgn. Chapter 3 55 Sgned Fxed-Pont n-bt sgned s-complement fxed-pont m bts before and f bts after bnary pont x = x x m m + + x + x + + Range: m to m f Precson: f E.g.,, sgned fxed-pont, m =. = =.875 f f Dgtal Logc Desgn. Chapter 3 56 KU EECS 4/4 8

29 Dgtal Logc Desgn. Chapter 3 6 March 7 Choosng Range and Precson Choce depends on applcaton Need to understand the numercal behavor of computatons performed some operatons can magnfy quantzaton errors In DSP fxed-pont range affects dynamc range precson affects sgnal-to-nose rato Perform smulatons to evaluate effects Dgtal Logc Desgn. Chapter 3 57 Fxed-Pont n VHDL Use numerc_bt wth mpled scalng Use proposed fxed_pkg package Currently beng standardzed by IEEE Types ufxed and sfxed Arthmetc operatons, reszng, converson lbrary eee_proposed; use eee_proposed.fxed_pkg.all; entty fxed_converter s port ( nput : n ufxed(5 downto -7); output : out sfxed(7 downto -7) ); end entty fxed_converter; Dgtal Logc Desgn. Chapter 3 58 KU EECS 4/4 9

30 Dgtal Logc Desgn. Chapter 3 6 March 7 Fxed-Pont Operatons Just use nteger hardware e.g., addton: f f f x + y = ( x + y ) / a 7 a 6 a 5 a 4 x -bt adder Ensure bnary ponts are algned a 3 x 7 x 8 x 9 b 4 b 3 y y 7 s s 7 s 8 s 9 c 4 c 3 c 4 c 5 b 4 b 5 y 8 y 9 Dgtal Logc Desgn. Chapter 3 59 Floatng-Pont Numbers Smlar to scentfc notaton for decmal e.g., , Allow for larger range, wth same relatve precson throughout the range mantssa radx exponent Dgtal Logc Desgn. Chapter 3 6 KU EECS 4/4 3

31 Dgtal Logc Desgn. Chapter 3 6 March 7 IEEE Floatng-Pont Format e bts m bts s exponent mantssa x = M E = ( s). mantssa exponent e + s: sgn bt ( non-negatve, negatve) Normalze:. M <. M always has a leadng pre-bnary-pont bt, so no need to represent t explctly (hdden bt) Exponent: excess representaton: E + e Dgtal Logc Desgn. Chapter 3 6 Floatng-Pont Range Exponents... and... reserved Smallest value exponent:... E = e + mantssa:... M =. Largest value exponent:... E = e mantssa:... M. Range: e + x < e Dgtal Logc Desgn. Chapter 3 6 KU EECS 4/4 3

32 Dgtal Logc Desgn. Chapter 3 6 March 7 Floatng-Pont Precson Relatve precson approxmately m all mantssa bts are sgnfcant m bts of precson m log m.3 decmal dgts Dgtal Logc Desgn. Chapter 3 63 Example Formats IEEE sngle precson, 3 bts e = 8, m = 3 range ±. 38 to ±.7 38 precson 7 decmal dgts Applcaton-specfc, bts e = 5, m = 6 range ±6. 5 to ±6.6 4 precson 5 decmal dgts Dgtal Logc Desgn. Chapter 3 64 KU EECS 4/4 3

33 Dgtal Logc Desgn. Chapter 3 6 March 7 Denormal Numbers Exponent =... hdden bt s x = M E = ( s). mantssa Smaller than normal numbers allow for gradual underflow, wth dmnshng precson Mantssa =... x = M E = ( s). e + = ± e +. Dgtal Logc Desgn. Chapter 3 65 Infntes and NaNs Exponent =..., mantssa =... ±Infnty Can be used n subsequent calculatons, avodng need for overflow check Exponent =..., mantssa... Not-a-Number (NaN) Indcates llegal or undefned result e.g.,. /. Can be used n subsequent calculatons Dgtal Logc Desgn. Chapter 3 66 KU EECS 4/4 33

34 Dgtal Logc Desgn. Chapter 3 6 March 7 Floatng-Pont Operatons Consderably more complcated than nteger operatons E.g., addton unpack, algn bnary ponts, adjust exponents add mantssas, check for exceptons round and normalze result, adjust exponent Combnatonal crcuts not feasble Ppelned sequental crcuts Dgtal Logc Desgn. Chapter 3 67 Floatng-Pont n VHDL Use proposed float_pkg package Currently beng standardzed by IEEE Types float, float3, float64, float8 Arthmetc operatons, reszng, converson Not lkely to be syntheszable Rather, use to verfy results of handoptmzed crcuts Dgtal Logc Desgn. Chapter 3 68 KU EECS 4/4 34

35 Dgtal Logc Desgn. Chapter 3 6 March 7 Summary Unsgned: Sgned: x = x = x Octal and Hex short-hand n n xn + xn + + x n n n + xn + + x Operatons: resze, arthmetc, compare Arthmetc crcuts trade off speed/area/power Fxed- and floatng-pont non-ntegers Gray codes for poston encodng Dgtal Logc Desgn. Chapter 3 69 KU EECS 4/4 35