UC2842B/3B/4B/5B UC3842B/3B/4B/5B

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1 UCB/B/B/B UCB/B/B/B HIGH PEFOMANCE CUENT MODE PWM CONTOLLE TIMMED OSCILLATO FO PECISE FE QUENCY CONTOL OSCILLATO FEQUENCY GUAANTEED AT 0kHz CUENT MODE OPEATION TO 00kHz AUTOMATIC FEED FOWAD COMPENSA TION LATCHING PWM FO CYCLEBYCYCLE CUENT LIMITING INTENALLY TIMMED EFEENCE WITH UNDEVOLTAGE LOCKOUT HIGH CUENT TOTEM POLE OUTPUT. UNDEVOLTAGE LOCKOUT WITH HYSTE ESIS LOW STATUP AND OPEATING CUENT DESCIPTION The UCxB family of control ICs provides the necessary features to implement offline or DC to DC fixed frequency current mode control schemes with a minimal external parts count. Internally implemented circuits include a trimmed oscillator for precise DUTY CYCLE CONTOL under voltage lockout featuring startup current less than 0.mA, a precision reference trimmed for accuracy at the error amp input, logic to insure latched operation, a PWM Minidip SO comparator which also provides current limit control, and a totem pole output stage designed to source or sink high peak current. The output stage, suitable for driving NChannel MOSFETs, is low in the offstate. Differences between members of this family are the undervoltage lockout thresholds and maximum duty cycle ranges. The UCB and UCB have UVLO thresholds of 6V (on) and 0V (off), ideally suited offline applications The corresponding thresholds for the UCB and UCB are. V and.9 V. The UCB and UCB can operate to duty cycles approaching 00%. A range of the zero to < 0 % is obtained by the UCB and UCB by the addition of an internal toggle flip flop which blanks the output off every other clock cycle. BLOCK DIAGAM (toggle flip flop used only in UCB and UCB) Vi GOUND V UVLO S/ V EF VEF V 0mA.0V INTENAL BIAS T/CT OSC VEF GOOD LOGIC T 6 OUTPUT VFB COMP CUENT SENSE EO AMP. S PWM V LATCH CUENT SENSE COMPAATO UCB D9IN March 999 /

2 UCB/B/B/B UCB/B/B/B ABSOLUTE MAXIMUM ATINGS Symbol Parameter Value Unit V i Supply Voltage (low impedance source) 0 V V i Supply Voltage (Ii < 0mA) Self Limiting I O Output Current ± A E O Output Energy (capacitive load) µj Analog Inputs (pins, ) 0. to. V Error Amplifier Output Sink Current 0 ma P tot Power Dissipation at T amb C (Minidip). W P tot Power Dissipation at Tamb C (SO) 00 mw T stg Storage Temperature ange 6 to 0 C T J Junction Operating Temperature 0 to 0 C T L Lead Temperature (soldering 0s) 00 C * All voltages are with respect to pin, all currents are positive into the specified terminal. PIN CONNECTION (top view) Minidip/SO COMP V EF V FB Vi I SENSE 6 OUTPUT T /C T GOUND D9IN PIN FUNCTIONS No Function Description COMP This pin is the Error Amplifier output and is made available for loop compensation. V FB This is the inverting input of the Error Amplifier. It is normally connected to the switching power supply output through a resistor divider. I SENSE A voltage proportional to inductor current is connected to this input. The PWM uses this information to terminate the output switch conduction. T /C T The oscillator frequency and maximum Output duty cycle are programmed by connecting resistor T to Vref and cpacitor C T to ground. Operation to 00kHz is possible. GOUND This pin is the combined control circuitry and power ground. 6 OUTPUT This output directly drives the gate of a power MOSFET. Peak currents up to A are sourced and sunk by this pin. V CC This pin is the positive supply of the control IC. V ref This is the reference output. It provides charging current for capacitor C T through resistor T. ODEING NUMBES SO UCBD; UCBD UCBD; UCBD UCBD; UCBD UCBD; UCBD Minidip UCBN; UCBN UCBN; UCBN UCBN; UCBN UCBN; UCBN /

3 UCB/B/B/B UCB/B/B/B THEMAL DATA Symbol Description Minidip SO Unit th jamb Thermal esistance Junctionambient. max C/W ELECTICAL CHAACTEISTICS ( [note ] Unless otherwise stated, these specifications apply for < Tamb < C for UCXB; 0 < Tamb < 0 C for UCXB; Vi = V (note ); T = 0K; CT =.nf) Symbol Parameter Test Conditions UCXB UCXB Min. Typ. Max. Min. Typ. Max. Unit EFEENCE SECTION V EF Output Voltage T j = C I o = ma V V EF Line egulation V V i V 0 0 mv V EF Load egulation I o 0mA mv V EF / T Temperature Stability (Note ) mv/ C Total Output Variation Line, Load, Temperature.9... V e N Output Noise Voltage 0Hz f 0KHz T j = C 0 0 µv (note ) Long Term Stability T amb = C, 000Hrs mv (note ) I SC Output Short Circuit ma OSCILLATO SECTION f OSC Frequency T j = C T A = T low to T high T J = C ( T = 6.k, C T = nf) f OSC / V Frequency Change with Volt. V CC = V to V % f OSC / T Frequency Change with Temp. T A = T low to T high 0. % V OSC Oscillator Voltage Swing (peak to peak).6.6 V 9 I dischg Discharge Current (V OSC =V) T J = C. T A = T low to T high. EO AMP SECTION V Input Voltage V PIN =.V V I b Input Bias Current V FB = V µa A VOL V V o V db BW Unity Gain Bandwidth T J = C MHz PS Power Supply ejec. atio V V i V db I o Output Sink Current VPIN =.V V PIN =.V ma I o Output Source Current VPIN =.V V PIN = V ma V OUT High V PIN =.V; V L = KΩ to Ground V OUT Low V PIN =.V; V L = KΩ to Pin CUENT SENSE SECTION G V Gain (note & ).... V/V V Maximum Input Signal V PIN = V (note ) V SV Supply Voltage ejection V i V (note ) 0 0 db I b Input Bias Current 0 0 µa Delay to Output ns KHz KHz KHz ma ma /

4 UCB/B/B/B UCB/B/B/B ELECTICAL CHAACTEISTICS (continued) Symbol Parameter Test Conditions UCXB UCXB Min. Typ. Max. Min. Typ. Max. Unit OUTPUT SECTION V OL Output Low Level I SINK = 0mA V I SINK = 00mA V V OH Output High Level I SOUCE = 0mA.. V I SOUCE = 00mA.. V V OLS UVLO Saturation VCC = 6V; I SINK = ma V t r ise Time T j = C C L = nf () ns t f Fall Time T j = C C L = nf () ns UNDEVOLTAGE LOCKOUT SECTION Start Threshold XB/B V XB/B V Min Operating Voltage XB/B V After Turnon XB/B V PWM SECTION Maximum Duty Cycle XB/B % XB/B 0 0 % Minimum Duty Cycle 0 0 % TOTAL STANDBY CUENT I st Startup Current V i = 6.V for UCXB/B ma V i = V for UCXB/B ma I i Operating Supply Current V PIN = V PIN = 0V ma V iz Zener Voltage I i = ma V Notes :. Max package power dissipation limits must be respected; low duty cycle pulse techniques are used during test maintain Tj as close to T amb as possible.. These parameters, although guaranteed, are not 00% tested in production.. Parameter measured at trip point of latch with V PIN = 0.. Gain defined as : VPIN A = ; 0 V PIN 0. V VPIN. Adjust Vi above the start threshold before setting at V. /

5 UCB/B/B/B UCB/B/B/B Figure : Open Loop Test Circuit..KΩ T V EF EO AMP. ADJUST.KΩ N 00KΩ KΩ I SENSE ADJUST KΩ COMP V FB I SENSE T /C T V EF UCB 6 0.µF V i OUTPUT GOUND 0.µF A W KΩ V i OUTPUT C T D9IN GOUND High peak currents associated with capacitive loads necessitate careful grounding techniques. Timing and bypass capacitors should be connected close to pin in a single point ground. The transistor and KΩ potentiometer are used to sample the oscillator waveform and apply an adjustable ramp to pin. Figure : Timing esistor vs. Oscillator Frequency T (KΩ) C T=nF CT=00pF CT=nF CT=00pF CT=00pF D9IN C T=nF C T=0nF V i=v T A= C 0. 0K 0K 0K 0K 00K 00K 00K 00K f OSC(KHz) Figure : Output DeadTime vs. Oscillator Frequency % C T=00pF C T=00pF C T=nF C T=0nF C T=nF C T=00pF C T=nF D9IN V i=v T A= C 0K 0K 0K 0K 00K 00K 00K 00K fosc(khz) /

6 UCB/B/B/B UCB/B/B/B Figure : Oscillator Discharge Current vs. Temperature. Figure : Maximum Output Duty Cycle vs. Timing esistor. I dischg (ma). V i =V V OSC =V D9IN D max (%) 90 0 I dischg=.ma D9IN6.0 0 I dischg=.ma V i=v C T=.nF T A= C T A ( C) 0 0. T(KΩ) Figure 6: Error Amp OpenLoop Gain and Phase vs. Frequency. Figure : Current Sense Input Threshold vs. Error Amp Output Voltage. (db) Gain D9IN V i =V V O =V to V L =00K T A = C Phase φ V th (V) V i =V T A = C T A = C D9IN T A =0 C K 0K 00K M f(hz) Figure : eference Voltage Change vs. Source Current V i =V D9IN V O (V) Figure 9: eference Short Circuit Current vs. Temperature. I SC (ma) 00 V i =V L 0.Ω D9IN0 0 0 T A = C T A =0 C TA= C I ref (ma) T A ( C) 6/

7 UCB/B/B/B UCB/B/B/B Figure 0: Output Saturation Voltagevs. Load Current. Figure : Supply Current vs. Supply Voltage. V sat (V) V i Source Saturation (Load to Ground) T A = C D9IN T A =0 C I i (ma) 0 D9IN V i =V 0µs Pulsed Load 0Hz ate T A =0 C T A = C Sink Saturation GND (Load to V i ) I O (ma) Figure : Output Waveform. 0 0 UCX/ UCX/ T =0K C T =.nf V FB =0V I Sense =0V T A = C V i (V) Figure : Output Cross Conduction 90% V i =V C L =.0nF T A = C V i =0V C L = pf T A = C V O 0V/DIV 0% I CC 00mA/DIV 0ns/DIV Figure : Oscillator and Output Waveforms. 00ns/DIV V i CT V EG T PWM 6 OUTPUT OUTPUT LAGE T /SMALL C T CLOCK OSCILLATO CT I D C T OUTPUT GND SMALL T /LAGE C T D9IN /

8 UCB/B/B/B UCB/B/B/B Figure : Error Amp Configuration..V ma Z i V FB COMP Z f D9IN Figure 6 : Under Voltage Lockout. V i ON/OFF COMMAND TO EST OF IC I CC UCB UCB UCB UCB <ma V ON V OFF 6V.V 0V.6V <0.mA V OFF V ON V CC D9IN6 During UVLO, the Output is low Figure : Current Sense Circuit. EO AMPL. I S COMP V CUENT SENSE COMPAATO S C CUENT SENSE GND D9IN Peak current (is) is determined by the formula.0 V IS max S A small C filter may be required to suppress switch transients. /

9 UCB/B/B/B UCB/B/B/B Figure : Slope Compensation Techniques. V EG V EG T T I S SLOPE CT T /C T UCB I S SLOPE C T T /C T UCB S I SENSE GND S I SENSE GND D9IN Figure 9 : Isolated MOSFET Drive and Current Transformer Sensing. V CC V in.0vref ISOLATION BOUNDAY V GS Waveforms 6 Q 0 0 0% DC % DC S Q I pk = V (pin ). S ( ) N S N P COMP/LATCH C S N S N P D9IN9 9/

10 UCB/B/B/B UCB/B/B/B Figure 0 : Latched Shutdown. OSC BIAS ma EA N 90 N 90 D9IN0 SC must be selected for a holding current of less than 0.mA at T A(min). The simple two transistor circuit can be used in place of the SC as shown. All resistors are 0K. Figure : Error Amplifier Compensation From V O.V ma i d C f f EA Error Amp compensation circuit for stabilizing any currentmode topology except for boost and flyback converters operating with continuous inductor current. From V O.V ma P C P i d C f f EA D9IN Error Amp compensation circuit for stabilizing currentmode boost and flyback topologies operating with continuous inductor current. 0/

11 UCB/B/B/B UCB/B/B/B Figure : External Clock Synchronization. V EF T BIAS C T OSC EXTENAL SYNC INPUT 0.0µF Ω EA The diode clamp is required if the Sync amplitude is large enough to cause the bottom side of C T to go more than 00mV below ground D9IN Figure : External Duty Cycle Clamp and Multi Unit Synchronization. V EF A B K BIAS 6 OSC K Q C K S NE EA. f = ( A B )C D max = B A B TO ADDITIONAL UCXXAs D9IN /

12 Figure : SoftStart Circuit V ref BIAS OSC MΩ EA ma V S Q C D9IN V ref UCB/B/B/B UCB/B/B/B Figure : SoftStart and Error Amplifier Output Duty Cycle Clamp. V CC V in BIAS OSC 6 Q EA ma V Clamp V S Q Comp/Latch C BC09 S V CLAMP = where 0 <V CLAMP <V I pk(max) = V CLAMP S D9IN /

13 UCB/B/B/B UCB/B/B/B DIM. mm inch MIN. TYP. MAX. MIN. TYP. MAX. A a a a b b C c (typ.) D () E e e. 0.0 F () L M S (max.) OUTLINE AND MECHANICAL DATA SO () D and F do not include mold flash or protrusions. Mold flash or potrusions shall not exceed 0.mm (.006inch). /

14 UCB/B/B/B UCB/B/B/B DIM. mm inch MIN. TYP. MAX. MIN. TYP. MAX. OUTLINE AND MECHANICAL DATA A. 0. a B b b D E e e e F I L Z Minidip /

15 UCB/B/B/B UCB/B/B/B Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 999 STMicroelectronics Printed in Italy All ights eserved STMicroelectronics GOUP OF COMPANIES Australia Brazil Canada China France Germany Italy Japan Korea Malaysia Malta Mexico Morocco The Netherlands Singapore Spain Sweden Switzerland Taiwan Thailand United Kingdom U.S.A. /