TDA CHANNEL VOLUME CONTROLLER 1 FEATURES 2 DESCRIPTION. Figure 1. Package

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1 6 CHANNEL CONTROLLER FEATURES 6 CHANNEL INPUTS 6 CHANNEL OUTPUTS ATTENUATION RANGE OF 0 TO -79dB CONTROL IN.0dB STEPS 6 CHANNEL INDEPENDENT CONTROL ALL FUNCTION ARE PROGRAMMABLE VIA SERIAL BUS DESCRIPTION Figure. Package SO-0 Table. Order Codes Part Number TDA7448 TDA74483TR Package SO-0 Tape & Reel The TDA7448 is a 6 channel volume controller for quality audio applications in Multi-Channels Audio Systems Thanks to the used BIPOLAR/CMOS Technology, Low Distortion, Low Noise and DC stepping are obtained. Figure. Block Diagram IN 7 OUT IN 9 4 OUT IN3 3 6 OUT3 IN4 8 5 OUT4 IN5 4 5 OUT5 IN6 7 6 OUT6 GND CREF 0 SUPPLY I C BUS DECODER 0 9 SCL ADDR V S D0AU396 June 004 REV. 3 /4

2 Table. Absolute Maximum Ratings Symbol Parameter Value Unit V S Operating Supply Voltage 0.5 V T amb Operating Ambient Temperature 0 to 70 C T stg Storage Temperature Range -55 to 50 C Figure 3. Pin Connection (Top view) V S IN IN3 IN5 OUT5 OUT3 OUT N.C CREF IN IN IN6 OUT6 OUT4 OUT N.C. ADDR SCL 0 GND D0AU397 Table 3. Thermal Data Symbol Parameter Value Unit R th j-pin thermal Resistance junction-pins 50 C/W Table 4. Quick Reference Data Symbol Parameter Min. Typ. Max. Unit V S Supply Voltage V V CL Max Input Signal Handling Vrms THD Total Harmonic Distortion V = Vrms f =KHz % S/N Signal to Noise Ratio Vout = Vrms 00 db S C Channel Separation f = KHz 90 db Volume Control (db step) db Mute Attenuation 90 db /4

3 Table 5. Electrical Characteristcs (refer to the test circuit T amb = 5 C, V S = 9V, R L = 0KΩ, R G = 600Ω, unless otherwise specified) Symbol Parameter Test Condition Min. Typ. Max. Unit SUPPLY V S Supply Voltage V I S Supply Current 7 ma SVR Ripple Rejection 80 db INPUT STAGE R IN Input Resistance KΩ V CL Clipping Level THD = 0.3%.5 Vrms S IN Input Separation The selected input is grounded through a.µ capacitor CONTROL 90 db C RANGE Control Range 79 db A VMAX Max. Attenuation 79 db A STEP Step Resolution db E A Attenuation Set Error A V = 0 to -4dB - 0 db A V = -4 to -79dB db E T Tracking Error A V = 0 to -4dB - 0 db A V = -4 to -79dB - 0 db V DC DC Step adyacent attenuation steps mv A mute Mute Attenuation 90 db AUDIO OUTPUTS V CLIP Clipping Level THD = 0.3%.5 Vrms R L Output Load Resistance KΩ V DC DC Voltage Level 4.5 V GENERAL E NO Output Noise BW = 0Hz to 0KHz All gains = 0dB, Flat 0 5 µv S/N Signal to Noise Ratio All gains = 0dB; V O = Vrms 00 db S C Channel Separation left/right db THD Distortion A V = 0; V I = Vrms % BUS INPUT V Il Input Low Voltage V V IH Input High Voltage.5 V I IN Input Current V IN = 0.4V -5 5 µa V O Output Voltage Achnowledge I O =.6mA V 3/4

4 Figure 4. Test circuit IN IN 7 OUT IN IN 9 4 OUT IN3 IN3 3 6 OUT3 IN4 IN4 8 5 OUT4 IN5 IN5 4 5 OUT5 IN6 IN6 7 6 OUT6 0µF GND CREF 0 SUPPLY V S I C BUS DECODER 0 SCL 9 ADDR D0AU406 3 APPLICATION SUGGESTIONS The volume control range is 0 to -79dB, by db step resolution. The very high resolution allows the implementation of systems free from any noise acoustical effect. Figure 6. THD vs. R LOAD 3. CREF The suggested 0µF reference capacitor (CREF) value can be reduced to 4.7µF if the application requires faster power ON. Figure 5. THD vs. frequency Figure 7. Channel separation vs. frequency 4/4

5 4 I C BUS INTERFACE Data transmission from microprocessor to the TDA7448 and vice versa takes place through the wires I C BUS interface, consisting of the two lines and SCL (pull-up resistors to positive supply voltage must be connected). 4. Data Validity As shown in fig. 8, the data on the line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW. 4. Start and Stop Conditions As shown in fig. 9 a start condition is a HIGH to LOW transition of the line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the line while SCL is HIGH. 4.3 Byte Format Every byte transferred on the line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first. 4.4 Acknowledge The master (µp) puts a resistive HIGH level on the line during the acknowledge clock pulse (see fig. 0). The peripheral (audio processor) that acknowledges has to pull-down (LOW) the line during this clock pulse. The audio processor which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer. 4.5 Transmission without Acknowledge Avoiding to detect the acknowledge of the audio processor, the µp can use a simpler transmission: simply it waits one clock without checking the slave acknowledging, and sends the new data. This approach of course is less protected from misworking. Figure 8. Data Validity on the I CBUS SCL DATA LINE STABLE, DATA VALID CHANGE DATA ALLOWED D99AU03 Figure 9. Timing Diagram of I CBUS SCL I CBUS START D99AU03 STOP Figure 0. Acknowledge on the I CBUS SCL START MSB D99AU033 ACKNOWLEDGMENT FROM RECEIVER 5/4

6 5 SOFTWARE SPECIFICATION Interface Protocol The interface protocol comprises: A start condition (S) A chip address byte, containing the TDA7448 address A subaddress bytes A sequence of data (N byte + acknowledge) A stop condition (P)) CHIP ADDRESS SUBADDRESS DATA to DATA n MSB LSB MSB LSB MSB LSB S ACK X X X B DATA ACK DATA ACK P ACK = Acknowledge; S = Start; P = Stop; A = Address; B = Auto Increment 5. EXAMPLES D96AU No Incremental Bus The TDA7448 receives a start condition, the correct chip address, a subaddress with the B = 0 (no incremental bus), N-data (all these data concern the subaddress selected), a stop condition. CHIP ADDRESS SUBADDRESS DATA MSB LSB MSB LSB MSB LSB S ACK X X X 0 D3 D D D0 ACK DATA ACK P D96AU4 5.. Incremental Bus The TDA7448 receivea start conditions, the correct chip address, a subaddress with the B = (incremental bus): now it is in a loop condition with an autoincrease of the subaddress whereas SUBADDRESS from "XXX000" to "XXX" of DATA are ignored.the DATA concern the subaddress sent, and the DATA concern the subaddress sent plus one in the loop etc, and at the end it receivers the stop condition. CHIP ADDRESS SUBADDRESS DATA to DATA n MSB LSB MSB LSB MSB LSB S ACK X X X D3 D D D0 ACK DATA ACK P D96AU4 5. DATA BYTES Address= 88 (HEX) (000000): ADDR open; 8A (HEX) (00000): connect to supply Table 6. FUNCTION SELECTION: subaddress MSB LSB D7 D6 D5 D4 D3 D D D0 SUBADDRESS X X X B SPEAKER ATTENUATION OUT X X X B SPEAKER ATTENUATION OUT X X X B SPEAKER ATTENUATION OUT 3 X X X B 0 0 SPEAKER ATTENUATION OUT 4 X X X B SPEAKER ATTENUATION OUT 5 X X X B 0 0 SPEAKER ATTENUATION OUT 6 X X X B 0 0 NOT USED X X X B 0 NOT USED B=: INCREMENTAL BUS; ACTIVE B=0: NO INCREMENTAL BUS X= DON T CARE 6/4

7 In Incremental Bus Mode, the three not used functions must be addressed in any case. For example to refresh Speaker Attenuation 3 = 0dB and Speaker Attenuation 6 = -40 db ; the following bytes must be sent: Table 7. SUBADDRESS SPEAKER ATTENUATION OUT SPEAKER ATTENUATION OUT XXX000 XXXXXXXX XXXXXXXX SPEAKER ATTENUATION OUT SPEAKER ATTENUATION OUT 4 SPEAKER ATTENUATION OUT 5 XXXXXXXX XXXXXXXX SPEAKER ATTENUATION OUT Table 8. SPEAKER ATTENUATION SELECTION MSB LSB D7 D6 D5 D4 D3 D D D0 SPEAKER ATTENUATION dB 0 0 -db 0 0 -db 0-3dB 0 0-4dB 0-5dB 0-6dB -7dB dB dB dB dB dB dB dB dB 0-64dB 0-7dB MUTE value = 0 to -79dB and MUTE 7/4

8 Figure. PIN:0 Figure 4. PINS: 0 V S V S 0K 0µA CREF SCL 0K D96AU430 D96AU44 Figure. PINS: 5, 6, 7, 4, 5, 6 Figure 5. PINS: 9 V S OUT to OUT6 4 0µA 0µA D96AU43 D0AU398 Figure 3. PINS:, 3, 4, 7, 8, 9 V S 0µA IN 00K V REF D96AU45 8/4

9 Figure 6. Test and Application Circuit J J IN OUT IN J3 C IC IN TDA7448 OUT 7 C µf 6V + J4 OUT IN C3 9 IN OUT 4 C4 µf 6V + OUT IN3 3 C5 3 IN3 OUT3 6 C6 µf 6V + 3 OUT3 IN4 4 C7 8 IN4 OUT4 5 C8 µf 6V + 4 OUT4 IN5 5 C9 4 5 IN5 OUT5 C0 + µf 6V 5 OUT5 IN6 6 C 7 IN6 OUT6 6 C + µf 6V 6 OUT6 GND 7 C3 0µF 6V + 0 CREF SCL 0 7 GND 8 N.C. 9 3 N.C. VS GND ADDR JP R 0 J5 VS DGND + C4 C5 3 SCL 00µF 6V 0.µF 4 IC R R3 J6 K K VS GND 9/4

10 Figure 7. Component Layout (65 x 7mm) Figure 8. PC Board (Component side) 0/4

11 Figure 9. PC Board (Solder side) /4

12 Figure 0. SO-0 Mechanical Data & Package Dimensions mm inch DIM. MIN. TYP. MAX. MIN. TYP. MAX. A OUTLINE AND MECHANICAL DATA A B C D () E e H h L k 0 (min.), 8 (max.) ddd () D dimension does not include mold flash, protusions or gate burrs. Mold flash, protusions or gate burrs shall not exceed 0.5mm per side. SO D /4

13 Table 9. Revision History Date Revision Description of Changes January 004 First Issue June Modified the style-sheet in compliance with the last revision of the Corporate Technical Pubblications Design Guide. 3/4

14 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. 004 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States 4/4

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