css Custom Silicon Solutions, Inc.

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1 css Custom Silicon Solutions, Inc. GENERAL PART DESCRIPTION The is a micropower version of the popular timer IC. It features an operating current under µa and a minimum supply voltage of., making it ideal for battery-operated applications. A six-decade programmable counter is included to allow generation of long timing delays. Configuration data for the counter is held in EEPROM to maintain the standard pin count of eight. The analog circuits are temperature compensated to provide excellent stability over a wide ambient temperature range. A simple four-wire interface provides Read/Write access to the EEPROM. Key Features Lowest power timer (by > X)! Active mode current < µa Wide operating range Wide supply range:. to. Temperature range: -0 C to + C Pin Configuration Internal decade, programmable counter PDIP or SOIC Settings =,,,,, & Multiplies delay time by up to Figure Delay times from microseconds to days Pin-for-pin compatible with series timers Typical Application Circuit Monostable or Astable operation Extremely low transient switching current Break-Before-Make output driver Temperature stability 0% per C Applications Portable & Battery-Powered Systems Precision Timing & Pulse Generation Figure Ultra Long Period Delay Generation Single Cell Battery Applications Ordering Information Ultra Low Power Timers Part Number Package Description Pulse Width Modulation -ID pin plastic DIP Low Cost, High Reliability Applications -IS pin plastic SOIC See page 9 for more details and options. Custom Silicon Solutions Inc. 9 Sky Park Circle, Suite F Irvine, CA 9 (99) 9-90 FAX: (99) GND TRIGGER OUTPUT RESET + DISCHARGE THRESHOLD CONTROL Long Period Delay Generator DD Operating conditions: R A = R B =.MΩ, Internal counter = (maximum) = 0pF, Delay =. minutes Average power =. µw at DD =.0 R A R B Custom Silicon Solutions, Inc. 009 ersion., May 009

2 Block Diagrams Standard Timer Configuration (Std. Mode) (Programmable counter bypassed, Divider setting = ) DD R R+R+R ~ MΩ For DD >., H = / x DD, L = / x DD Control oltage Threshold H For DD <., H = 0.9 x DD, L = 0. x DD _ Comp + R L _ Comp + R Q Flip Flop S Q Discharge R SS Figure Extended Period Configuration (EP Mode) (Programmable counter enabled, Divider setting ) DD Control oltage Threshold R H R L _ Comp + _ Comp + Configuration EEPROM R Q Flip Flop S Q Clk Mode Run Mode Control Q Trig Enbl Clk Sel Decade Counter Q Sel In0 Out In : Mux Discharge R SS EEPROM Bit Assignments Figure Counter Configuration Divider Setting (Mult) Mode Control Bits Function xxxxx000 (Std. ) xxxx0xxx Astable Mode ( Don t Care if Std. ) xxxxx00 xxxxxxx Monostable Mode ( Don t Care if Std. ) xxxxx0 0 xxx0xxxx Micro Power xxxxx0 K xxxxxxx Low Power xxxxx0 K xx0xxxxx Standard oltage (Trip levels = ⅓ & ⅔ DD) xxxxx 0K xxxxxxx Low oltage (Trip levels = % & 90% DD) xxxxx M Bit Unused xxxxx (Std. ) Bit 0 (Read Only) Table A Table B Note: For detailed programming information, see Application Note AN- (_App_Note_Serial_Interface) Custom Silicon Solutions, Inc. 009 ersion., May 009

3 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings Supply oltage ( DD) oltage at any Pin Total Current into DD Pin (Source) Total Current out of GND Pin (Sink) Storage Temperature Range -0. to DD ma 0 ma - C to +0 C Note: Absolute maximum ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings. Electrical Characteristics Temperature = C, Test Circuit #, unless otherwi se specified (If DD <., Low oltage mode must be selected to provide adequate comparator input levels. EE Bit = ) Parameter Symbol Conditions Min Typ Max Units Supply Range DD Standard DD (EE Bit = 0) Low DD (EE Bit = ) Supply Current (Power = Micro) (No DC load on OUTPUT pin, R L = ) Timing Accuracy (Micro power setting, EE Bit = 0) (Monostable & Astable Modes) Timing Drift with Temperature (Monostable & Astable Modes) Timing Shift with Supply oltage (Monostable & Astable Modes) IDD DD = DD =.0 DD =.0 TA DD TD TEMP TS DD R A(B) = MΩ, = 0µF DD = DD =.0 DD =.0 R A(B) = MΩ, = 0µF DD = DD =.0 DD =.0 R A(B) = MΩ, = 0µF DD = DD =.0 DD = µa µa µa % % % ppm/ C ppm/ C ppm/ C Maximum Oscillator Frequency f MAX R A,B =.KΩ, I = 0 pf MHz Control oltage CTRL Standard DD (EE Bit = 0) Low DD (EE Bit = ) oltage TRIG Standard DD (EE Bit = 0) Low DD (EE Bit = ) oltage RST 0. x DD x DD 0. x DD oltage (Timer Pin) Discharge Saturation oltage (Discharge Pin) Input Current (, & Threshold Inputs) OL OH DIS DD =, I SINK = ma DD =.0, I SINK = ma DD =.0, I SINK = ma DD =, I SOURCE = ma DD =.0, I SOURCE = ma DD =.0, I SOURCE = ma DD =, I SINK =. ma DD =.0, I SINK = ma DD =.0, I SINK = ma I IN DD =. IN = to %/ %/ %/ % % % % pa Discharge Leakage Current I DIS DD =. 0 na Rise & Fall Times t R, t F DD =.0, C L = pf ns Input Capacitance C IN pf Table Custom Silicon Solutions, Inc. 009 ersion., May 009

4 Electrical Characteristics (cont) Temperature = -0 C to + C, Test Circuit #, unle ss otherwise specified (If DD <., Low oltage mode must be selected to provide adequate comparator input levels. EE Bit = ) Parameter Symbol Conditions Min Typ Max Units Supply Range DD Standard DD (EE Bit = 0) Low DD (EE Bit = ) Supply Current (Power = Micro) (No DC load on OUTPUT pin, R L = ) Timing Accuracy (Micro power setting, EE Bit = 0) (Monostable & Astable Modes) Timing Drift with Temperature (Monostable & Astable Modes) Timing Shift with Supply oltage (Monostable & Astable Modes) IDD DD = DD =.0 DD =.0 TA DD TD TEMP TS DD R A(B) = MΩ, = 0µF DD = DD =.0 DD =.0 R A(B) = MΩ, = 0µF DD = DD =.0 DD =.0 R A(B) = MΩ, = 0µF DD = DD =.0 DD = µa µa µa % % % ppm/ C ppm/ C ppm/ C Maximum Oscillator Frequency f MAX R A,B =.KΩ, I = 0 pf MHz Control oltage CTRL Standard DD (EE Bit = 0) Low DD (EE Bit = ) oltage TRIG Standard DD (EE Bit = 0) Low DD (EE Bit = ) oltage RST 0. x DD x DD 0. x DD oltage (Timer Pin) Discharge Saturation oltage (Discharge Pin) Input Current (, & Threshold Inputs) OL OH DIS DD =, I SINK = ma DD =.0, I SINK = ma DD =.0, I SINK = ma DD =, I SOURCE = ma DD =.0, I SOURCE = ma DD =.0, I SOURCE = ma DD =, I SINK =. ma DD =.0, I SINK = ma DD =.0, I SINK = ma I IN DD =. IN = to %/ %/ %/ % % % % pa Discharge Leakage Current I DIS DD =. 0 na Rise & Fall Times t R, t F DD =.0, C L = pf ns Input Capacitance C IN pf Table Test Circuit # DD RA SS DD Dischg Thresh Control R B Note: = External Timing Capacitor Figure Custom Silicon Solutions, Inc. 009 ersion., May 009

5 Pin Descriptions Pin Number Pin Name Primary Function (Normal Mode) Secondary Function (EE Programming) SS Ground TRIGGER Initiates timing cycles (Active low) Serial Clock OUTPUT Timer (CMOS Levels) Serial Data Out RESET Asynchronous timer reset (Active low) Serial Data In CONTROL Upper comparator switch level R/W enable (Active if CTRL < ) THRESHOLD Upper comparator analog input DISCHARGE Open drain FET, on when OUTPUT = DD Positive voltage supply Table Applications Information General The IC may be used in many applications as a direct replacement for the popular timer. It features the lowest operating current and a minimum supply voltage of.. It also features a programmable decade counter for generating long time delays. An internal EEPROM stores the counter configuration: Divide by (standard ) or divide by, 0,,, or. The internal counter allows long time delays to be generated with small value capacitors. Delay Time Equations: For standard supply voltages ( LOW Bit = 0) Charge time ( TH = 0 to ⅔ DD) =. x R A x For low voltage mode ( LOW Bit = ) Charge time ( TH = 0 to 0.9 DD) =. x R A x where = External timing capacitor RESET TRIGGER Monostable Operation (Standard Mode) The circuit in Figure shows a monostable or one shot configuration. A single, positive output pulse is generated on the falling edge of the TRIGGER input. When TRIGGER goes low, a flip-flop is set, the OUTPUT pin is set high and DISCHARGE allows the timing capacitor to charge towards DD via R A. When TH reaches the upper comparator trip level, the flip-flop is reset, OUTPUT is forced low and DISCHARGE pulls TH to GND. After TH has discharged, the circuit is ready for the next trigger pulse. Typical signal waveforms are shown in Figure. The RESET input must be held high (inactive) during the timing cycle. If RESET is brought low, the OUTPUT pin is immediately forced low and the cycle is terminated. SS Figure Monostable Circuit (Std. Mode) In the monostable configuration, the duration of the timing cycle is simply the time required to charge the timing capacitor from GND to the upper comparator trip level. The trip level is nominally ⅔ DD. At low supply voltages it is increased to 0.9 DD. (An EEPROM bit controls this selection.) The delay time equations for both conditions are provided in the following paragraph. DD Dischg Thresh Control TH DD R A Figure Monostable Waveforms (Std. Mode) Figure provides a log-log selection chart. It shows the time delay for various combinations of R A and. With the counter bypassed (Mult = ), time delays from usec to second are easily generated with capacitor values from 0pF to uf. For long time delays (or medium delay times using small capacitor values) the Extended Period configuration should be used. (See the next section.) Timing Cap (Ct) (uf) OUTPUT CAP Mult = Blue: Std. DD ⅔ DD 0 RA = K K 0K Green: Low DD Delay Time (ms) Figure Time Delay Chart M M Custom Silicon Solutions, Inc. 009 ersion., May 009

6 Monostable Operation (Extended Period or EP Mode) For longer time delays, the circuit in Figure 9 uses the internal decade counter to effectively multiply the value of the timing capacitor. Three bits in the EEPROM select a multiplier value from to. The analog block is configured as a free running oscillator, which is the input clock to the counter. On the falling edge of TRIGGER, the oscillator is enabled, OUTPUT is set high, the decade counter is enabled and a new timing cycle begins. The timing cycle ends when the counter reaches the selected terminal count. Waveforms for an extended delay cycle are shown in Figure. SS Figure 9 Extended Period Delay Circuit DD Dischg TH Thresh Control DD RA R B Extended Delay Time Equations: For standard supply voltages ( LOW Bit = 0) Oscillator Period (t OSC) = 0.9 x (R A+R B) x Total Delay Time = Counter Setting (or Mult) x t OSC Total Delay Time = Mult x 0.9 x (R A+R B) x where = External timing capacitor For low voltage mode ( LOW Bit = ) Oscillator Period (t OSC) =.9 x (R A+R B) x Total Delay Time = Counter Setting (or Mult) x t OSC Total Delay Time = Mult x.9 x (R A+R B) x The chart in Figure shows nominal delay times for multiplier settings from to and resistor values (R A+R B) from KΩ to MΩ. (The external timing capacitor,, equals 0pF.) The resulting delay times cover an eight-decade range! Counter alue Blue: Std. DD CT = 0pF RA+RB = K K 0K M M Green: Low DD.E-0.E-0.E+00.E+0.E+0.E+0.E+0.E+0.E+0 RESET Delay Time (sec) TRIGGER Figure Extended Period Delay Chart OUTPUT Mult = ⅔ DD The component values required for some common delay times are listed in Table. For this calculation, the value of R A and R B are equal. To keep the overall power low, values above MΩ were selected. CAP 0 ⅓ DD Figure Extended Period Waveforms In the Extended Period monostable configuration, the duration of the timing cycle is the oscillator period multiplied by the counter setting. The oscillator is configured for astable operation. (The internal TRIGGER signal to the oscillator is internally tied to THRESHOLD. See Figure.) CAP oscillates between ⅓ & ⅔ DD (or % & 90% if low voltage mode is selected). The delay time equations for both supply conditions are provided in the following paragraph. Delay Multiplier alue R A & R B msec 0pF. MΩ sec. K 0pF. MΩ min. 0K 0pF.9 MΩ hour M 00pF. MΩ day M uf. MΩ week M 0.uF.9 MΩ Table Extended Period Delay Table Note: = External timing capacitor Custom Silicon Solutions, Inc. 009 ersion., May 009

7 Astable Operation (Standard Mode) The circuit in Figure shows the astable or free running oscillator configuration. If the counter setting equals one, the counter is bypassed and the device operates like a standard timer. With the TRIGGER input tied to THRESHOLD, a new timing cycle is started each time TH drops below the lower comparator trip level. Free Running Oscillator Equations: For standard supply voltages ( LOW Bit = 0) Oscillator Period (t OSC) = 0.9 x (R A+R B) x Osc. Freq. (f OSC) = /t OSC =./[(R A+R B) x ] where = External timing capacitor For low voltage mode ( LOW Bit = ) Oscillator Period (t OSC) =.9 x (R A+R B) x Osc. Freq. (f OSC) = /t OSC = 0./[(R A+R B) x ] Duty Cycle = R B/(R A+R B) DD SS DD Dischg Thresh Control TH RA R B The chart in Figure shows nominal oscillator frequencies for resistor values (R A+R B) from KΩ to MΩ and capacitor values from 0pF to uf. The resulting frequency range extends from Hz to MHz. (For this chart, the counter is bypassed; Mult =.) Figure Astable Circuit (Std. Mode) The capacitor charges to ⅔ DD through (R A+R B) and discharges to ⅓ DD through R B. (As in the monostable mode, the trip levels are changed to % & 90% for low supply voltages. This selection is made via the EEPROM.) The duty cycle is determined by the ratio of R A and R B. Typical signal waveforms are shown in Figure. The RESET input must be held high for the oscillator to be active. If RESET is brought low, the OUTPUT pin is immediately forced low and oscillation halts. Equations for the free running oscillator are provided in the following paragraph. RESET OUTPUT CAP Mult = 0 ⅔ DD ⅓ DD Figure Astable Waveforms (Std. Mode) Note: The TRIGGER signal is connected to TH Timing Capacitor (uf) RA+RB = M M 0K K K Green: Low DD Frequency (Hz) Figure Astable Frequency Chart (Std. Mode) Astable Operation (Extended Period or EP Mode) Blue: Std. DD The circuit in Figure employs the internal decade counter to divide the oscillator frequency by the multiplier setting. The multiplier value, to, is selected by the EEPROM. The analog block is configured as a free running oscillator, which supplies the input clock to the counter. The oscillator runs when RESET is high (logic one) and TRIGGER is low. Each divide by stage of the decade counter consists of a divide by followed by a divide by. This configuration provides a 0% output duty cycle no matter which multiplier setting is selected. Waveforms for this mode are shown in Figure. Custom Silicon Solutions, Inc. 009 ersion., May 009

8 Figure Astable Circuit (EP Mode) RESET TRIGGER OUTPUT CAP Mult = 0 SS ⅔ DD ⅓ DD Figure Astable Waveforms (EP Mode) Free Running Oscillator Equations: For standard supply voltages ( LOW Bit = 0) Oscillator Period (t OSC) = 0.9 x (R A+R B) x Osc. Freq. (f OSC) = /t OSC =./[(R A+R B) x ] Frequency = f OSC/Mult where = External timing capacitor For low voltage mode ( LOW Bit = ) Oscillator Period (t OSC) =.9 x (R A+R B) x Osc. Freq. (f OSC) = /t OSC = 0./[(R A+R B) x ] Frequency = f OSC/Mult Duty Cycle = 0% The chart in Figure shows nominal oscillator frequencies for multiplier settings from to and resistor values (R A+R B) from KΩ to MΩ. (The external timing capacitor,, equals 0pF.) The resulting frequencies range from less than Hz to MHz. DD Dischg TH Thresh Control DD RA R B Counter alue RA+RB = M M 0K K K CT = 0pF Green: Low DD Blue: Std. DD Frequency (Hz) Figure Astable Frequency Chart (EP Mode) EEPROM (Configuration Memory) An internal EEPROM provides one byte of nonvolatile memory that stores the configuration information. The configuration bits control the multiplier setting ( to ), the power setting (micro or low) and the comparator trip levels (standard or low voltage). (See Tables A & B for more details.) By employing an internal EEPROM for configuration control, the pin count and pin functions remain compatible with existing IC s. The EEPROM includes a high voltage generator. No special signal levels are required to Read or Write to it. Access to the EEPROM is enabled by forcing the CONTROL pin to GND. (This pin is normally left open and an internal voltage divider holds it at ⅔ DD.) With CONTROL held at GND, the TRIGGER and RESET pins are redefined to be SCLK (Serial Clock) and SDIN (Serial Data In). Data from the EEPROM can be read at the OUTPUT pin. The interface is simple and straightforward. It can support programming individual units or devices installed in their application circuit. A detailed description of the serial interface is provided in Application Note AN- ( EEPROM Serial Interface ). A development kit is available and provides both programming and evaluation capabilities. It uses a standard PC and one USB port. Please contact Custom Silicon Solutions for more information. The core EEPROM cell is a differential, floating gate circuit. Like an SRAM, it features zero static current. Its output data is valid whenever the supply voltage is above. It has excellent data retention and endurance characteristics. Data retention is greater than years at C and its endurance (maximum number of Store cycles) is greater than 0,000 cycles. A typical Store operation can be performed in less than msec. Custom Silicon Solutions, Inc. 009 ersion., May 009

9 Supply Current Considerations The internal supply current used by the can be divided into three main components: ) ~.ua constant current (independent of DD) ) ~ MΩ from DD to GND (ua at DD = ) ) ~ ua switching current at DD =, F OSC = 0KHz (~ linearly proportional to DD & F OSC) To minimize the second component, keep DD as low as possible. To minimize the switching current, keep DD & F OSC low. (Choose a lower multiplier value so the oscillator frequency is well below 0 KHz.) The external current is determined by the values of R A and R B. They should be as high as practical. (PCB surface leakage typically limits the value to MΩ.) The has a Break-Before-Make driver for the OUTPUT signal. This circuit eliminates the large through current that flows directly from DD to GND during each output transition. This significantly reduces the noise injected into the power supply. The discharge path in the monostable configuration is another source of transient current. (When TH reaches the upper trip point, the capacitor is very quickly discharged to GND.) To minimize this transient current, simply add a resistor (R LIM) in series with the DISCHARGE pin. (see Figure ) The value of R LIM must be low enough to allow the timing capacitor to completely discharge before the next timing cycle. A typical value for R LIM is KΩ to KΩ. SS DD Dischg TH Thresh Control DD R LIM RA Ordering Information Part Number Package Description Shipping Options -ID pin plastic DIP 0 units / Rail -IS pin plastic SOIC 9 units / Rail -ISTR _IW pin plastic SOIC Die or Tested Wafers 00 units / Tape & Reel Contact CSS for options _DK Development Kit N.A. Table Ordering Options All packaging options use lead free materials. All part types are rated for operation from -0 C to + C. The default configuration stored in EEPROM is: Configuration Data = 00 HEX Operating Mode = Standard Power Setting = Micro oltage Setting = Standard Timing Capacitor = None Packaged parts may be ordered with alternate configuration settings. A minimum purchase and/or service charge may apply. Please contact CSS for details. Development Kit The Development Kit is a PC based system that allows the user to Read and Program the internal EEPROM. It includes an easy to use dialog box and serial interface (USB port required). The circuit card includes plenty of extra terminals so that most applications can be built and evaluated quickly and easily. For more information, please refer to the development kit s instruction manual. Figure Monostable with R LIM ESD Protection All input and output pins include protection devices to guard against ESD damage. A simplified schematic of the input protection circuit is shown in Figure 9. The voltage levels at all pins should be kept between ( SS 0.) and ( DD +0.) to prevent forward biasing the diodes. Input/ Pin DD To Internal Circuits Input Protection Diodes Figure 9 Input Protection Circuit Custom Silicon Solutions, Inc ersion., May 009

10 Typical Performance Characteristics IDD vs. DD & Temperature IDD vs. DD & Temperature IDD (ua) +C +C +C -0C Power Setting = Micro IDD (ua) 0 0 +C +C +C -0C Power Setting = Low DD () Figure Supply Current (Micro Power) DD () Figure Supply Current (Low Power) Normalized Frequency Drift vs. DD Normalized Frequency Drift vs. Temperature Std. DD Low DD Astable Mode CT = nf; RA,RB = Meg Temperature = C DD =.0 DD =.0 DD = Astable Mode CT = nf; RA,RB = 0K Delta Freq. (%) - Delta Freq. (%) DD () Temperature (deg. C) Figure Frequency Drift vs. DD Figure Frequency Drift vs. Temperature.0 Propagation Delay vs. Level.0 Propagation Delay vs. Level. Standard Trip Levels (/ & / DD). Low DD Trip Levels (% & 90%) Propagation Delay (usec) Power Setting Micro Low DD Propagation Delay (usec) Power Setting Micro Low DD Low Level (%DD) Figure Propagation Delay (Standard DD) 0 9 Low Level (%DD) Figure Propagation Delay (Low DD) Custom Silicon Solutions, Inc. 009 ersion., May 009

11 Typical Performance Characteristics (continued).0 Minimum Pulse Width vs. Level Standard Trip Levels (/ & / DD).0 Minimum Pulse Width vs. Level Low DD Trip Levels (% & 90% DD) Pulse Width (usec)..0. Power Setting Micro Low DD.0.0 Pulse Width (usec)..0. Power Setting Micro Low DD Low Level (%DD) Figure Pulse Width (Std. DD) 0 9 Low Level (%DD) Figure Pulse Width (Low DD) High oltage (DD-out) () Timer OUTPUT High oltage vs. Source Current DD DD.0 DD.0 Source Current (ma) 9 Timer OUTPUT Drive High vs. Temperature IOH measured at OH = DD - 0. DD =.0 DD =.0 DD = 0. Source Current (ma) Figure 9 OUTPUT OH vs. I OH Temperature (degrees C) Figure 0 OUTPUT I OH vs. Temperature Timer OUTPUT Low oltage vs. Sink Current Timer OUTPUT Drive Low vs. Temperature IOL measured at OL = 0. DD.0 DD.0 9 DD =.0 Low oltage () DD Sink Current (ma) DD =.0 DD = 0. Sink Current (ma) Figure OUTPUT OL vs. I OL Temperature (degrees C) Figure OUTPUT I OL vs. Temperature Custom Silicon Solutions, Inc. 009 ersion., May 009

12 Typical Performance Characteristics (continued) DISCHARGE Low oltage vs. Sink Current DISCHARGE Drive Low vs. Temperature DD.0 0 DD =.0 IOL measured at OL = 0. Low oltage () DD DD.0 Sink Current (ma) DD =.0 DD = 0. Sink Current (ma) Figure DISCHARGE OL vs. I OL Temperature (degrees C) Figure DISCHARGE I OL vs. Temperature Custom Silicon Solutions, Inc. 009 ersion., May 009

13 PACKAGE DRAWINGS Pinout Diagram SOIC Mechanical Drawing GND TRIGGER OUTPUT RESET DD DISCHARGE THRESHOLD CONTROL CSS -IS YYWWG E H Figure Pin Indicator SOIC Dimensions Inches Millimeters Symbol MIN MAX MIN MAX A 9.. A B C D E e 0. H h L α 0 0 Table 0 min α D e B Typ h L Figure A A C PDIP Mechanical Drawing PDIP Dimensions Inches Millimeters Symbol MIN MAX MIN MAX A A b 0. b.. b 0.. C D E E e 0.0. eb Q 0.0 S 0 α A CSS -ID YYWWG D S e E A b b b Q Table E C eb α Figure Custom Silicon Solutions, Inc. 009 ersion., May 009