JTAG (IEEE /P1149.4)

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1 (IEEE 49./P49.4) utorial Introductory L Sept ()-ut.I- 997 I est Symposium genda What Is? (5 minutes) he Increasing Problem of est (5 minutes) Conventional Methods of est ( minutes) he Boundary-Scan Idea (5 minutes) he Boundary-Scan rchitecture (5 minutes) ypical pplications (5 minutes) Interconnect esting Logic Cluster esting Memory esting System-Level est Real pplications ( minutes) For More Information (5 minutes) Q & ( minutes) L Sept ()-ut.I I est Symposium Standard pproach o est What Is? / IEEE 49. Developed by oint est ction roup (over 2 SC, test, and system vendors) starting in mid '8's Sanctioned by IEEE as Std 49. est ccess Port and Boundary-Scan rchitecture in 99 Solution: Build test facilities/test points into chips Focus: Ensure compatibility between all compliant ICs L Sept ()-ut.I I est Symposium L Sept ()-ut.I I est Symposium Standard est ccess Port... and Boundary-Scan rchitecture RS* P 4/5-Wire Interface at Chip-Level Serial Instruction/Serial Data Port Extensible to Include User Register Scan effectively partitions digital logic to facilitate control and observation of its function Chip-Internal Scan: Partitions chips at storage cells (latches/ flipflops) to effectively partition sequential logic into clusters of combinational logic Boundary-Scan: Partitions boards at chip I/Os for control and observation of board-level nodes user-defined instructions user-defined data registers L Sept ()-ut.I I est Symposium L Sept ()-ut.I I est Symposium

2 he Increasing Problem of est he Incredible Shrinking Board Miniaturization results in loss of test access Yesterday oday om orrow? L Sept ()-ut.I I est Symposium L Sept ()-ut.I I est Symposium he Ever-Expanding Chip Increasing integration at chip level complicates controllability? C D C D Can t fford Not o est Cost will increase by a factor of ten as fault finding moves from one level of complexity to the next. he result: Reduced Profit Margins Delayed Product Introduction Dissatisfied Customers Yesterday oday. Device level unit of cost 2. Board level units of cost 3. System level units of cost 4. Field level, units of cost L Sept ()-ut.I I est Symposium L Sept ()-ut.I- 997 I est Symposium Conventional Methods of est Conventional Methods of Board est Functional est ( Edge-Connector est) Based on board function, rather than structure est generation primarily manual est access limited to primary I/O only L Sept ()-ut.I- 997 I est Symposium L Sept ()-ut.I I est Symposium

3 Conventional Methods of Board est In-Circuit est ( Bed-of-Nails est) Based on board structure, but limited by chip complexity Expensive testers and fixtures required est access limited by: Fine pitch packages Double-sided boards Conformal coating MCMs Conventional Methods of Board est In-Circuit est ( Bed-of-Nails est) Chip function can be ignored for shorts testing Chip function must be considered for continuity test est generation, though automated, requires IC models L Sept ()-ut.I I est Symposium L Sept ()-ut.I I est Symposium he Boundary Scan Idea he Boundary-Scan Idea In-Circuit test points moved onto the silicon, creating Virtual Nails Boundary scan cells bound each net, providing for continuity testing Observe/Control cells provide for test and normal function L Sept ()-ut.I I est Symposium L Sept ()-ut.I I est Symposium he Boundary Scan Idea Boundary Scan Method of Board est Scan provides a means to arbitrarily observe test results and source test stimulus Based on board structure; Not limited by chip function/ complexity Scan method requires minimal on chip/board resources (pins/nets) est access is not limited by board physical factors L Sept ()-ut.I I est Symposium L Sept ()-ut.I I est Symposium

4 Boundary Scan Method of Board est he Boundary Scan Cell Chip function need not be considered for board test (shorted/open nets) est generation is highly automated; Simple In-Circuit Library models (BSDL) are vendorsupplied or ED-generated NI (Normal Input) SO (Serial Output) OBSERVE CONROL ES/D MUX CPURE/SCN MUX SCN UPDE LCH/FLOP LCH/FLOP SI (Serial Input) NO (Normal Output) L Sept ()-ut.I I est Symposium L Sept ()-ut.I I est Symposium P he Control rchitecture Boundary scan and other test data registers operate under control of instruction register Data is scanned from to through selected test data register or instruction register under control of est ccess Port (P) controller P operates synchronously to using for state selection state transitions occur on rising edge of based on the current state and the input value ONLY he est ccess Port est Logic Reset Run est/idle Select -Scan Capture Shift- Exit - Pause- Exit 2- Select -Scan Capture- Shift- Exit - Pause- Exit 2-6-state P provides 4 major operations: RESE RUN-ES SCN- SCN- Scans consist of 3 primary steps: CPURE SHIF UPDE Update- Update- L Sept ()-ut.I I est Symposium L Sept ()-ut.I I est Symposium P he Extest Instruction (REQUED) Provides for test external to chip, such as interconnect test Output pins operate in test mode, driven from contents of BSC update latch Input data captured in BSC scan latches prior to shift operation Shift operation allows test response to be observed at while next test stimulus inserted at Following shift operation, new test stimulus transferred to BSC update latches he Sample/Preload Instruction (REQUED) P Provides means to preload boundary before entry to test mode Output and input pins operate in normal mode Input pin data and core logic output data captured in BSC scan latches Shift operation allows test response to be observed while next test stimulus inserted at Following shift operation, new stimulus transferred to BSC update latches L Sept ()-ut.I I est Symposium L Sept ()-ut.I I est Symposium

5 he Bypass Instruction (REQUED) Provides for abbreviated scan path through chip Output and input pins operate in normal mode he one-bit bypass register is selected for scans ypical pplications P Mandatory that an all-ones value updated into the decodes to Bypass, as well as any opcodes which are otherwise undefined L Sept ()-ut.I I est Symposium L Sept ()-ut.I I est Symposium Interconnect est Full B/S Board Interconnect est Partial B/S Board ll nets bound by BSC's and/or primary I/O requiring no physical access Not all nets are bound by boundary scan and/or primary I/O, perhaps requiring some IC access Parallel access reduced to card edge only est generation and application fast and easy Expense and complexity reduced for test generation and test application for chips/nets with B/S access Cluster testing may be used to access non-scan nets L Sept ()-ut.I I est Symposium L Sept ()-ut.I I est Symposium Logic Cluster est Logic Cluster est LOIC "CLUSER" Random-logic cluster is bound by boundaryscannable chips Deterministic test stimulus (P-generated) can be driven to cluster from B/S outputs est response can be captured at B/S inputs BIS methods (PRP/PS) can be used for increased test throughput and near "t-speed" performance Microprocessor LV852 Parallel Data In LV852 LV852 Scan Path Control Logic (Non-Scan) IEEE 49. Latch B852 B852 LV854 ddress Control Registered ransceiver Data Memory rray L Sept ()-ut.I I est Symposium L Sept ()-ut.I I est Symposium

6 Memory est Memory est Latch B852 B852 ddress Control Registered ransceiver LV854 Data Memory rray Memory array bound by boundary scan chips utomatic test patterns can be generated and driven from B/S outputs est response can be captured at B/S inputs ransceivers can test for net shorts w/o memory R/W BIS methods (PRP/PS) can be used for increased test throughput B B2 B3 B4 2B 2B2 2B3 2B4 D SN74BC SN74BC8244 Y Y2 Y3 Y4 2Y 2Y2 2Y3 2Y4 256 x 8 RM rray D D D2 D3 D4 D5 D6 D7 WE CS MODE IEEE 49. EXES & SMPLE) IEEE 49. (with BIS capability) ime o pply Scans Patterns ime o pply Scans Patterns Y Y2 Y3 Y4 2Y 2Y2 2Y3 2Y4 SN74BC CCESSES Seconds Seconds 7 52,, CCESSES 375. Minutes 2,, 2,, <. Minutes 28, 2,, L Sept ()-ut.I I est Symposium L Sept ()-ut.I I est Symposium System-Level est S P S P S P P-addressable interface unit extends access beyond board-level System-level test System design verification Sys integration (Mfg test) Sys self-test (Field Svc) Supports in place board test and board-to-board test Real pplications llows reuse of device/ board test data SP-ddressable Scan Port Device L Sept ()-ut.I I est Symposium L Sept ()-ut.I I est Symposium Real pplications of the P Design Verification/Debug I N E R N L S C N E S BIS Emulation Programming P Scan access to chips, boards, systems for: Design verification/debug Manufacturing test Hardware/software integration Field test/diagnostics ccess built-in self-test (BIS) ccess on-chip/in-circuit emulation (ONCE/ICE) ccess in-system programming (ISP) of PLDs/EEPROMs Let your imagination run wild!!! Provides control and observation of system under test without need for physical access Ease of set-up for test Can be used in standard system configuration (no need for card extenders, etc.) Can be used in environmental chambers Can access on-chip emulation for software/debug Can access ISP for code download/offload/ changes L Sept ()-ut.I I est Symposium L Sept ()-ut.I I est Symposium

7 Manufacturing est System Configuration Maintenance IC Provides test and diagnostic capabilities of in-circuit test without need/expense of physical access Improved fault coverage/diagnostic without large capital expense Highly automated test generation reduces test development time Provides low-level test access within configured systems for: In-house system integration Fielded-system test and diagnostics Built-in self-test In-field upgradability via ISP, etc. Remote field test, diagnostic and upgrade L Sept ()-ut.I I est Symposium L Sept ()-ut.I I est Symposium I s Educational Products Call (24) to ORDER IEEE Standards Call (8) 678-IEEE to ORDER Scan Educator PC-based tutorial with interactive boundary-scan simulation. FREE download at IEEE 49. estability videotapes wo-part video presenting an overview and instructions for boundary scan. Item No. SV (NSC VHS) and SV2 (PL VHS), $49 each. In process of converting to MPE on CD-ROM IEEE 49. Boundary-Scan IEEE Std (Includes IEEE Std 49.a-993), IEEE Standard est ccess Port and Boundary-Scan rchitecture, ISBN , IEEE order number SH6626. he official document which specifies the international standard for a test access port and boundary-scan architecture. Informally known as the standard, it was officially ratified by the IEEE in February 99. Since, it has been supplemented twice. he first supplement, ratified in une 993, is included in the referenced document. he second supplement is currently a separate document, as referenced below. IEEE Std 49.b-994, Supplement to IEEE Std , ISBN , IEEE order number SH he official document which specifies the international standard for a boundary-scan description language. his supplement to IEEE Std was ratified in September 994. L Sept ()-ut.I I est Symposium L Sept ()-ut.I I est Symposium utorials/handbooks he est ccess Port and Boundary-Scan rchitecture, Colin M. Maunder, Rodham E. ulloss, ed., IEEE CS Press, ISBN Edited by two principal chairs of the IEEE 49. working group, this Computer Society tutorial compiles several of the seminal papers on boundaryscan along with several invited papers on various topics including applications, implementation, and others. It will primarily be of interest to the design and/or test engineer. he Boundary-Scan Handbook, Kenneth P. Parker, Kluwer cademic Publishers, ISBN uthored by the principal force behind the Boundary-Scan Description Language (BSDL) and an IEEE 49. working group principal as well as a long time manufacturing and design-for-test expert, this is truly considered HE indispensable handbook on boundary scan for the design and/or test engineer. Boundary-Scan est - Practical pproach, Harry Bleeker, Peter van den Eijnden, Frans de ong, Kluwer cademic Publishers, ISBN uthored by several and IEEE 49. working group principals, this book is a ready reference to boundary-scan technology, its benefits, and considerations for design and test managers and engineers. L Sept ()-ut.I I est Symposium SIC SP E P BIS B/S BSC BSDL BSR BS CE DF DSP ED ebc FP HSDL ICE IC bbreviations/cronyms pplication-specific Integrated Circuit ddressable Scan Port utomatic est Equipment utomatic est Pattern eneration Built-In Self-est Boundary-Scan Boundary-Scan Cell Boundary-Scan Description Language Boundary-Scan Register Boundary-Scan est Computer-ided Engineering Design-for-est Data Register Digital Signal Processing/Processor Electronic Design utomation Embedded est Bus Field-Programmable ate rray Hierarchical Scan Description Language In-Circuit Emulation In-Circuit est L Sept ()-ut.I I est Symposium IEEE ISP MCM Mfg PCB PLD PRP PS PWB SPL SVF P BC RS UU Institute of Electrical & Electronics Engineers In-System Programming oint est ction roup Multi-Chip Module Manufacturing Printed Circuit Board Programmable Logic Device Pseudo-Random Pattern eneration Parallel Signature nalysis Printed Wiring Board Scan Path Linker Serial Vector Format est ccess Port est Bus est Clock est Data Input est Data Output est Mode Select est Reset Unit Under est