Technical Innovation. Salland delivers fully Integrated Solutions for High Volume Testing of Ultra-fast SerDes Applications

Transcription

1 Technical Innovation Salland delivers fully Integrated Solutions for High Volume Testing of Ultra-fast SerDes Applications Increasing Speeds Present New Challenges The fundamental technology at the heart of all high speed serial communications today is SerDes (serializer/deserialzer.) Applications for these serial interfaces occur both on system backplanes as well as cable or optical links like multi-gigabit Ethernet, optical networking, imaging interfaces, etc. A SerDes can be an IO port on a large ASIC or CPU, or it can be a stand-alone component that interfaces with a host on a storage device, a multimedia device or display. SerDes are also used to interconnect servers in data centers, to communicate across backplanes on high-end routers, and to network multiple CPUs in computing intensive applications. All wireline communications today are based on SerDes using a variety of data rates and protocols such as OIF, SONET / SDH, Infiniband, PCIe, SATA, USB3, Fiber channel, DisplayPort, etc. Each standard requires different compliance tests, but are all based on the same SerDes architecture See Figure 1. Today's speeds are 10G, 16G, 25G and 100Gb/s (using 4 25G channels in parallel.) Semiconductor chip manufacturers who provide such serial interfaces in their devices have unique challenges when it comes to testing their products in high volume manufacturing. Most automated test equipment (ATE) installed today cannot support such speeds. Many times, existing instrumentation does not offer the full range of functionality required to properly test these devices. Additionally, special design considerations must be taken into account when interfacing load boards and devices to the testers. Figure 1: Basic SerDes Circuit

2 This paper describes the considerations that must be taken into account for both characterizing SerDes devices in the lab and testing them in high volume manufacturing. Issues highlighted include the measurement capabilities, the interconnection and software integration required. Two case studies are presented showing how Salland s expertise with integrating add-on instruments with mainstream ATE platforms addresses the challenges of high speed SerDes tesintg. One case study is for the Teradyne UltraFLEX test system and the other for the Verigy V93K tester. received signal which more closely resembles the original or desired signal, allowing the use of higher frequencies or producing fewer bit errors. Preemphasis is a relative measure of the emphasizing of the high frequency spectral component in the signal and is used by SerDes for channel loss in db. Rise and fall time: a measure of the BW and transition of the output signal in ps. Requirements for Test and Characterization SerDes are made up of a transmit section and a receive section. Each section requires a set of tests. Characterizing SerDes requires measuring and analyzing the output signal of the transmitter. For the receiver, one must measure the tolerance of the receiver to adverse stress conditions. Transmitter Test Requirements: Testing the transmitter is typically done with a wideband sampling scope that has a bandwidth exceeding that of the signal. Figure 2 shows a typical eye chart produced a digital sampling oscilloscope. The TX test list includes the following: Eye height: Measure of the vertical eye opening in mv. Eye width: Measure of the horizontal eye opening in ps. Figure 3: Measuring Rise and Fall Time Duty cycle distortion: a measure of the symmetry and balance of a transmitted signal. Jitter measurement and decomposition: a measure of the signal variations on the horizontal aixs. The jitter decomposition determines the scale of the parameters that make up the jitter such as Random Jitter (RJ), Sinusoidal Jitter (SJ), Deterministic Jitter (DJ) and Inter-Symbol-Interference (ISI.) Mask test and mask margin: a measure of the contour of the inner eye opening relative to a standard specified mask. Figure 2: Eye Chart from Salland DSO Pre-emphasis: In high speed digital transmission, preemphasis is used to improve signal quality at the output of a data transmission. In transmitting signals at high data rates, the transmission medium may introduce distortions, so pre-emphasis is used to distort the transmitted signal to correct for this distortion. When done properly this produces a Figure 4: Comparison with Standard Mask

3 receiver of a SerDes requires an instrument capable of generating a Pseudo Random bit Sequence (PRBS) and an error detector to measure the Bit Error Rate (BER). A typical characterization of a receiver includes the following tests starting with three jitter tests: Deterministic Jitter: This is the measure of jitter tolerance for a receiver at a specific Bit Error Rate. This test is typically done at different frequencies of phase modulation or periodic jitter and is repeated for different frequencies of sinusoidal jitter throughout the jitter tolerance spectrum. Figure 5: Tabular Measurement Data from DSO For high volume testing, this data needs to be accessible by the ATE as shown in Figure 5. Salland s expertise in ATE integration insures that this API interface is available and accurate for users. The eye charts and data shown in the above two examples are the output produced by Salland s dual lane, 15 Gb/s high performance digital sampling oscilloscope. This module has a very small footprint (4 x 5.6 ) making it suitable for mounting in the limited space on an ATE loadboard. Random Jitter: In this test, the random jitter (RJ) is increased while performing a closed loop BER test in order to determine the RJ tolerance of a receiver Jitter Tolerance: During this test, the level of the input signal at the receiver is typically reduced until it reaches the BER level in order to determine if the receiver can tolerate a minimum input signal level. For a more comprehensive characterization, a composite of phase and amplitude modulation of both random and sinusoidal jitter (SJ) is applied as the stress signal for the receiver characterization. Clock Recovery (CRU): In order to test the clock recovery circuit, jitter transfer and tolerance test are done by frequency modulating the input signal to the DUT (Figure 7.) The jitter transfer test of a CRU is performed with a digital sampling scope capable of time Interval error measurement or a frequency deviation measurement as a function of frequency modulated signal into the DUT. Figure 6: Dual 15GHz DSO for UltraFLEX Receiver Test Requirements: A different set of tests are required for the Receiver. The primary function of the SerDes receiver is to discriminate and between a 0 and a 1 in the presence of non-ideal input signals. Testing the Figure 7: Jitter vs. PM Amplitude The jitter tolerance test is a measure of BER as a function of inducing frequency modulated (FM) jitter

4 into the receiver. Note the frequency is typically swept between 1 KHz and 8 MHz for a 10 Gb/s SerDes as shown in Figure 8. Figure 10: Compact BERT-JIT Instrument Figure 8: Bit Error Rate (BER) vs. PM Amplitude Figure 9 is a block diagram showing the typical functions required in a BERT instrument. Salland s HIS-1X10-BERT-JIT (Figure 10) is an example of such a high performance instruments packaged in a very small footprint (3.2 x 4.9.) Electronic Dispersion Compensation: In high speed serial communication, intersymbol interference (ISI) is a form of distortion of a signal in which one symbol interferes with subsequent symbols. SerDes with electronic dispersion compensation (EDC) have a front-end circuit that compensates for the incoming ISI, or dispersion in the case of the optical signal prior to the decision circuit. Characterizing an EDC-capable SerDes is a BER test that requires the generator to spectrally shape the input signal to mimic Figure 9: Typical Features for BERT Instrument

5 the various stress conditions. For example, compliance testing for Long Reach Multi-Mode (LRM) SerDes requires that these devices operate error free in the presence of three stress conditions where the input pulse of 100ps is spread over 300ps. Figure 11 shows the three stress conditions applied (pre-cursor, post-cursor, and symmetric ) Figure 11: Stress Conditions to Test EDC Special Considerations for Wafer Sort Most SerDes testing today is done on packaged devices at Final Test due to the difficulty of signal delivery within the tight space available. Obvious reasons to perform high speed testing at Wafer Sort are to improve packaged device yield and KGD. Salland is developing a family of kits that will enable users to deploy high speed SerDes testing at wafer sort for popular ATE platforms. Our compact instruments will be able to be mounted on the loadboard. The instrument connects through blindmates to the probe card to make contact with the die. Test speeds up to 28Gbps SerDes will be possible. The stackup design is shown in Figure 12. Figure 12: Stackup Design for High Speed SerDes Testing

6 Trends and the future test requirements SerDes technology will continue to move towards higher density, higher bit rates, and more complex signals. For example, 100G SerDes and Ultra-Long Haul 100G SerDes use complex modulation (DPQSK.) Measuring these SerDes will require a 4 channel coherent phase sampling oscilloscope with a bandwidth of > 25GHz. A 4x25G BERT, with edge and phase alignment will be needed for characterizing 100G SerDes receivers. Higher port density will be required to test the coming 400GE which has 16x25G lanes on a single device. Techniques for optimization throughput during high volume production testing will be required. Salland s Roadmap In the near term, Salland plans on adding the following capabilities: A parallel bus interface to our instruments to enable them to communicate with and be controlled by the tester via the pins. We will soon add a PCIe interface capability on each of the instruments. A 4x25G BERT that fits into the cavity of the V93k. This 4x25G BERT will have full jitter tolerance capability. A 2 channel 30GHz DSO that fits into the cavity of the V93k. The module will be compatible with the existing measurement libraries and will incorporate a parallel bus interface. A test head, side-mounted frame that holds a larger port count of instruments for higher density applications. To address future trends in optical communications, a measurement library will be developed for signal analysis of non-nrz based SerDes. This will enable users to measure complex, modulated optical signals at 100Gbps, e.g. RZ-DQPSK, QAM, QPSK, on-off-keying (OOK) and transient, cross-phase modulation T- WM. We will develop a pluggable system that can be completely controlled from the tester to improve remote support. We will deveop better cooling capabilites to improve thermal dissipation. Abbreviations AM - amplitude modulation AWG - Arbitrary Waveform Generator BER Bit-Error Rate DCA - Digital Communications Analyzer DSO - Digital Sampling Oscilloscope DPQSK - Differential Phase Quadrature Shift Keying EDC - Electronic Dispersion Compensation FM - Frequency modulation ISI - Inter-Symbol-Interference KGD - Known Good Die LRM - Long Reach Mode PIB Probe Interface Board PM - Phase Modulation PPG - Pulse Pattern Generator PRPS - Pseudo-Random Pattern Sequence RJ - Random Jitter SSC - Switch-and Stay Combining SSG - Stress Signal Generator TWM - Two Wave Mixing

7 Case Study 1: Testing 44Gb/s SerDes on UltraFLEX A customer needed to characterize a 44Gb/s SerDes device on their existing Teradyne UltraFLEX system. We approached the project in three phases: First, a conceptual solution was validated using a standard UltraFLEX instrument. Second, a prototype was developed based on current technology. Finally, we developed a solution for atspeed testing of 40 and 100Gb/s SerDes. Concept Validation Receiver Test: Testing the receiver was performed with a Known Good transmitter, e.g. a regular SerDes transmitter performing a Bit Error Rate test using built in self-test (BIST) capability. This is a common approach in today s SerDes devices or IP. At this point, the receiver tests did not include any stress test conditions or any receiver tolerance testing. Transmitter Test: Testing and characterizing the transmitter was performed with two digital sampling oscilloscopes of comparable architectures. The customer benchmarked the same test signal from the DUT. In the first case, the signal was fed to a Gigadig scope (see eye capture in Figure 1). In second case, the signal was fed into the Teledyne TDSO-050 (eye capture shown in Figure 2). Figure 1: 44.4Gb/s at half speed on Gigidig Figure 2: Half rate of 44.4Gb/s testing on TDSO-050 Observations: The eye capture from the Gigadig showed excessive Jitter with eye closure occurring in both the vertical and horizontal. The source of the jitter is mainly bandwidth related, i.e. the bandwidth of the interconnect is much lower than half of the unit interval shown on the display. The Inter-Symbol-Interference (ISI) shown in Figure 4 is excessive for adequate signal measurements. The eye capture from the TDSO-050 shows a marginal result as the signal is running at the limit for basic eye measurements on this scope. The 3dB bandwidth of the TDSO-050 is 15GHz. This is the bare minimum for marginal eye measurements of a 22Gbps signal. We also observed that the intrinsic jitter of the TDO-050 is adequate for measuring signals at this rate and beyond.

8 There were other obstacles. The TDSO-050 has a Fast Ethernet / USB control which is inadequate for the throughput of this ATE applications. The size of the shell of the TDSO-050 was also too large to fit comfortably in the UltraFLEX stiffener. Finally, the sampling algorithm of the TDSO-050 (coherent statistical sampling) was different from that of the UltraFLEX. We needed the instrument measurements and performance to be compatible on the ATE. Prototype Development We therefore needed to develop a 2-channel, 15 Gb/s instrument with a smaller footprint. We accomplished this working with our SerDes partner, MultiLane SAL. The instrument developed is the Salland HSI-2X15-DSO. The parallel interface was designed to control, configure, and retrieve the data from the instrument. The interface consisted of a number of signals for read / writes on the parallel bus and control signals to select and define the bus master. This could be the microprocessor in the instrument or the UltraFLEX. We developed a specific protocol to configure, arm, and acquire data from either the Fast Ethernet port or the ATE bus. Trigger signals to arm and to start the data acquisition were included. There were no restrictions on the speed of the bus. We added a parallel interface between the HSI-2X15-DSO and the DUT board based on a modified IDE connector and then to the ATE pins from the test head. We made the sampling and utilization of the tester resources for clocking the acquisition system compatible with the existing UltraFLEX drivers and measurement libraries. The module had to fit in the UltraFLEX stiffener in order to be able to characterize and correlate signals on and off the tester. Figure 3 shows how two HSI-2X15-DSO modules can fit the UltraFLEX stiffener. We developed a software measurement library for the new instrument that was compatible with the existing TDSO The user used our library to correlate certain measurements with the existing UltraFLEX during bring up and the application development. Figure 4: Packaged result (4" x 5.6") Figure 3: HSI-2X15-DSO circuit board

9 Results All data analysis and calculations were performed on the host. The units were power by the DUT board and drew 2.1 Amps of a regular 5V supply. No additional cooling was required. The interface between the DUT card and the HSI-2X15-DSO was done with high performance coaxial cable and very well matched 26GHz edge launched connectors. We then correlated all measurements between the TDSO-050 and the HSI-2X15-DSO. The results were that measurement accuracy and throughput meet the user s requirements. The result was that the customer was able to deploy at-speed testing of the 44 Gb/s device on his existing fleet of UltraFLEX testers. Figure 5: Two instruments fit in UltraFLEX stiffener

10 Case Study 2: Testing Thunderbolt-class Device on V93K A customer needed to characterize and test a new device in the performance range of the Thunderbolt. Thunderbolt is new interconnect standard from Intel that was first available on new Apple Mac Book Pro notebooks. It supports two 10 Gb/s bi-directional channels on a common transport resulting in 40 Gb/s maximum aggregate throughput. PCI Express and DisplayPort protocols are supported on top of that transport. Our approach was to use the expertise of our partner, MultiLane SAL, to develop two new, high performance instruments that were compact enough to fit within the V93K stiffener. The block diagram below illustrates the plan for two channels only. In this application, we would need to support four channels. We developed two new instruments with footprints that could be stacked on top of each otheras well as fitting into the V93K stiffener. See load board photo next page. Since we did not want to use any tester resources, we installed an 8-port Ethernet switch that allowed the host controller to communicate with each of the eight instruments. We developed simple Linux-based drivers as shown ijn this sample script: client_socket_dso<<"connect:dso"; client_socket_dso>>reply; client_socket_bert<<"connect:bert"; client_socket_bert>>reply; client_socket_dso<<"configuredso"; // load script client_socket_dso>>reply; client_socket_bert<<"configurebert"; client_socket_bert>>reply; client_socket_dso<<"captureandmeasure"; client_socket_dso>>measurements; client_socket_bert<<"bertest"; client_socket_bert>>bertresult; client_socket_dso<<"exit"; client_socket_bert<<"exit";

11 The challenges we faced include the following: Thermal dissipation, the power dissipation of each BERT-JIT and DSO combination is about 20 Watts for a total of 80 watts for the 4 lane tester. This resulted in having to install a fan on the load board. We encountered initial repeatability issues, and traced it to power supply variation. We replaced the power supplies. We had few challenges supporting our customer remotely during the initial deployment and limited access to the tester to verify the code and to correlate. In the second phase of deployment we offered on-site support. We completed the integration, the calibration and optimized throughput to 800ms on all 4 channels in 8 days. Photo of V93K load board with 4x10G DSOs and 4x10-G BERTs with Jitter testing with details of close proximity of instruments and cabling to DUT.