Technical Innovation. Salland delivers fully Integrated Solutions for High Volume Testing of Ultra-fast SerDes Applications

Save this PDF as:
 WORD  PNG  TXT  JPG

Size: px
Start display at page:

Download "Technical Innovation. Salland delivers fully Integrated Solutions for High Volume Testing of Ultra-fast SerDes Applications"

Transcription

1 Technical Innovation Salland delivers fully Integrated Solutions for High Volume Testing of Ultra-fast SerDes Applications Increasing Speeds Present New Challenges The fundamental technology at the heart of all high speed serial communications today is SerDes (serializer/deserialzer.) Applications for these serial interfaces occur both on system backplanes as well as cable or optical links like multi-gigabit Ethernet, optical networking, imaging interfaces, etc. A SerDes can be an IO port on a large ASIC or CPU, or it can be a stand-alone component that interfaces with a host on a storage device, a multimedia device or display. SerDes are also used to interconnect servers in data centers, to communicate across backplanes on high-end routers, and to network multiple CPUs in computing intensive applications. All wireline communications today are based on SerDes using a variety of data rates and protocols such as OIF, SONET / SDH, Infiniband, PCIe, SATA, USB3, Fiber channel, DisplayPort, etc. Each standard requires different compliance tests, but are all based on the same SerDes architecture See Figure 1. Today's speeds are 10G, 16G, 25G and 100Gb/s (using 4 25G channels in parallel.) Semiconductor chip manufacturers who provide such serial interfaces in their devices have unique challenges when it comes to testing their products in high volume manufacturing. Most automated test equipment (ATE) installed today cannot support such speeds. Many times, existing instrumentation does not offer the full range of functionality required to properly test these devices. Additionally, special design considerations must be taken into account when interfacing load boards and devices to the testers. Figure 1: Basic SerDes Circuit

2 This paper describes the considerations that must be taken into account for both characterizing SerDes devices in the lab and testing them in high volume manufacturing. Issues highlighted include the measurement capabilities, the interconnection and software integration required. Two case studies are presented showing how Salland s expertise with integrating add-on instruments with mainstream ATE platforms addresses the challenges of high speed SerDes tesintg. One case study is for the Teradyne UltraFLEX test system and the other for the Verigy V93K tester. received signal which more closely resembles the original or desired signal, allowing the use of higher frequencies or producing fewer bit errors. Preemphasis is a relative measure of the emphasizing of the high frequency spectral component in the signal and is used by SerDes for channel loss in db. Rise and fall time: a measure of the BW and transition of the output signal in ps. Requirements for Test and Characterization SerDes are made up of a transmit section and a receive section. Each section requires a set of tests. Characterizing SerDes requires measuring and analyzing the output signal of the transmitter. For the receiver, one must measure the tolerance of the receiver to adverse stress conditions. Transmitter Test Requirements: Testing the transmitter is typically done with a wideband sampling scope that has a bandwidth exceeding that of the signal. Figure 2 shows a typical eye chart produced a digital sampling oscilloscope. The TX test list includes the following: Eye height: Measure of the vertical eye opening in mv. Eye width: Measure of the horizontal eye opening in ps. Figure 3: Measuring Rise and Fall Time Duty cycle distortion: a measure of the symmetry and balance of a transmitted signal. Jitter measurement and decomposition: a measure of the signal variations on the horizontal aixs. The jitter decomposition determines the scale of the parameters that make up the jitter such as Random Jitter (RJ), Sinusoidal Jitter (SJ), Deterministic Jitter (DJ) and Inter-Symbol-Interference (ISI.) Mask test and mask margin: a measure of the contour of the inner eye opening relative to a standard specified mask. Figure 2: Eye Chart from Salland DSO Pre-emphasis: In high speed digital transmission, preemphasis is used to improve signal quality at the output of a data transmission. In transmitting signals at high data rates, the transmission medium may introduce distortions, so pre-emphasis is used to distort the transmitted signal to correct for this distortion. When done properly this produces a Figure 4: Comparison with Standard Mask

3 receiver of a SerDes requires an instrument capable of generating a Pseudo Random bit Sequence (PRBS) and an error detector to measure the Bit Error Rate (BER). A typical characterization of a receiver includes the following tests starting with three jitter tests: Deterministic Jitter: This is the measure of jitter tolerance for a receiver at a specific Bit Error Rate. This test is typically done at different frequencies of phase modulation or periodic jitter and is repeated for different frequencies of sinusoidal jitter throughout the jitter tolerance spectrum. Figure 5: Tabular Measurement Data from DSO For high volume testing, this data needs to be accessible by the ATE as shown in Figure 5. Salland s expertise in ATE integration insures that this API interface is available and accurate for users. The eye charts and data shown in the above two examples are the output produced by Salland s dual lane, 15 Gb/s high performance digital sampling oscilloscope. This module has a very small footprint (4 x 5.6 ) making it suitable for mounting in the limited space on an ATE loadboard. Random Jitter: In this test, the random jitter (RJ) is increased while performing a closed loop BER test in order to determine the RJ tolerance of a receiver Jitter Tolerance: During this test, the level of the input signal at the receiver is typically reduced until it reaches the BER level in order to determine if the receiver can tolerate a minimum input signal level. For a more comprehensive characterization, a composite of phase and amplitude modulation of both random and sinusoidal jitter (SJ) is applied as the stress signal for the receiver characterization. Clock Recovery (CRU): In order to test the clock recovery circuit, jitter transfer and tolerance test are done by frequency modulating the input signal to the DUT (Figure 7.) The jitter transfer test of a CRU is performed with a digital sampling scope capable of time Interval error measurement or a frequency deviation measurement as a function of frequency modulated signal into the DUT. Figure 6: Dual 15GHz DSO for UltraFLEX Receiver Test Requirements: A different set of tests are required for the Receiver. The primary function of the SerDes receiver is to discriminate and between a 0 and a 1 in the presence of non-ideal input signals. Testing the Figure 7: Jitter vs. PM Amplitude The jitter tolerance test is a measure of BER as a function of inducing frequency modulated (FM) jitter

4 into the receiver. Note the frequency is typically swept between 1 KHz and 8 MHz for a 10 Gb/s SerDes as shown in Figure 8. Figure 10: Compact BERT-JIT Instrument Figure 8: Bit Error Rate (BER) vs. PM Amplitude Figure 9 is a block diagram showing the typical functions required in a BERT instrument. Salland s HIS-1X10-BERT-JIT (Figure 10) is an example of such a high performance instruments packaged in a very small footprint (3.2 x 4.9.) Electronic Dispersion Compensation: In high speed serial communication, intersymbol interference (ISI) is a form of distortion of a signal in which one symbol interferes with subsequent symbols. SerDes with electronic dispersion compensation (EDC) have a front-end circuit that compensates for the incoming ISI, or dispersion in the case of the optical signal prior to the decision circuit. Characterizing an EDC-capable SerDes is a BER test that requires the generator to spectrally shape the input signal to mimic Figure 9: Typical Features for BERT Instrument

5 the various stress conditions. For example, compliance testing for Long Reach Multi-Mode (LRM) SerDes requires that these devices operate error free in the presence of three stress conditions where the input pulse of 100ps is spread over 300ps. Figure 11 shows the three stress conditions applied (pre-cursor, post-cursor, and symmetric ) Figure 11: Stress Conditions to Test EDC Special Considerations for Wafer Sort Most SerDes testing today is done on packaged devices at Final Test due to the difficulty of signal delivery within the tight space available. Obvious reasons to perform high speed testing at Wafer Sort are to improve packaged device yield and KGD. Salland is developing a family of kits that will enable users to deploy high speed SerDes testing at wafer sort for popular ATE platforms. Our compact instruments will be able to be mounted on the loadboard. The instrument connects through blindmates to the probe card to make contact with the die. Test speeds up to 28Gbps SerDes will be possible. The stackup design is shown in Figure 12. Figure 12: Stackup Design for High Speed SerDes Testing

6 Trends and the future test requirements SerDes technology will continue to move towards higher density, higher bit rates, and more complex signals. For example, 100G SerDes and Ultra-Long Haul 100G SerDes use complex modulation (DPQSK.) Measuring these SerDes will require a 4 channel coherent phase sampling oscilloscope with a bandwidth of > 25GHz. A 4x25G BERT, with edge and phase alignment will be needed for characterizing 100G SerDes receivers. Higher port density will be required to test the coming 400GE which has 16x25G lanes on a single device. Techniques for optimization throughput during high volume production testing will be required. Salland s Roadmap In the near term, Salland plans on adding the following capabilities: A parallel bus interface to our instruments to enable them to communicate with and be controlled by the tester via the pins. We will soon add a PCIe interface capability on each of the instruments. A 4x25G BERT that fits into the cavity of the V93k. This 4x25G BERT will have full jitter tolerance capability. A 2 channel 30GHz DSO that fits into the cavity of the V93k. The module will be compatible with the existing measurement libraries and will incorporate a parallel bus interface. A test head, side-mounted frame that holds a larger port count of instruments for higher density applications. To address future trends in optical communications, a measurement library will be developed for signal analysis of non-nrz based SerDes. This will enable users to measure complex, modulated optical signals at 100Gbps, e.g. RZ-DQPSK, QAM, QPSK, on-off-keying (OOK) and transient, cross-phase modulation T- WM. We will develop a pluggable system that can be completely controlled from the tester to improve remote support. We will deveop better cooling capabilites to improve thermal dissipation. Abbreviations AM - amplitude modulation AWG - Arbitrary Waveform Generator BER Bit-Error Rate DCA - Digital Communications Analyzer DSO - Digital Sampling Oscilloscope DPQSK - Differential Phase Quadrature Shift Keying EDC - Electronic Dispersion Compensation FM - Frequency modulation ISI - Inter-Symbol-Interference KGD - Known Good Die LRM - Long Reach Mode PIB Probe Interface Board PM - Phase Modulation PPG - Pulse Pattern Generator PRPS - Pseudo-Random Pattern Sequence RJ - Random Jitter SSC - Switch-and Stay Combining SSG - Stress Signal Generator TWM - Two Wave Mixing

7 Case Study 1: Testing 44Gb/s SerDes on UltraFLEX A customer needed to characterize a 44Gb/s SerDes device on their existing Teradyne UltraFLEX system. We approached the project in three phases: First, a conceptual solution was validated using a standard UltraFLEX instrument. Second, a prototype was developed based on current technology. Finally, we developed a solution for atspeed testing of 40 and 100Gb/s SerDes. Concept Validation Receiver Test: Testing the receiver was performed with a Known Good transmitter, e.g. a regular SerDes transmitter performing a Bit Error Rate test using built in self-test (BIST) capability. This is a common approach in today s SerDes devices or IP. At this point, the receiver tests did not include any stress test conditions or any receiver tolerance testing. Transmitter Test: Testing and characterizing the transmitter was performed with two digital sampling oscilloscopes of comparable architectures. The customer benchmarked the same test signal from the DUT. In the first case, the signal was fed to a Gigadig scope (see eye capture in Figure 1). In second case, the signal was fed into the Teledyne TDSO-050 (eye capture shown in Figure 2). Figure 1: 44.4Gb/s at half speed on Gigidig Figure 2: Half rate of 44.4Gb/s testing on TDSO-050 Observations: The eye capture from the Gigadig showed excessive Jitter with eye closure occurring in both the vertical and horizontal. The source of the jitter is mainly bandwidth related, i.e. the bandwidth of the interconnect is much lower than half of the unit interval shown on the display. The Inter-Symbol-Interference (ISI) shown in Figure 4 is excessive for adequate signal measurements. The eye capture from the TDSO-050 shows a marginal result as the signal is running at the limit for basic eye measurements on this scope. The 3dB bandwidth of the TDSO-050 is 15GHz. This is the bare minimum for marginal eye measurements of a 22Gbps signal. We also observed that the intrinsic jitter of the TDO-050 is adequate for measuring signals at this rate and beyond.

8 There were other obstacles. The TDSO-050 has a Fast Ethernet / USB control which is inadequate for the throughput of this ATE applications. The size of the shell of the TDSO-050 was also too large to fit comfortably in the UltraFLEX stiffener. Finally, the sampling algorithm of the TDSO-050 (coherent statistical sampling) was different from that of the UltraFLEX. We needed the instrument measurements and performance to be compatible on the ATE. Prototype Development We therefore needed to develop a 2-channel, 15 Gb/s instrument with a smaller footprint. We accomplished this working with our SerDes partner, MultiLane SAL. The instrument developed is the Salland HSI-2X15-DSO. The parallel interface was designed to control, configure, and retrieve the data from the instrument. The interface consisted of a number of signals for read / writes on the parallel bus and control signals to select and define the bus master. This could be the microprocessor in the instrument or the UltraFLEX. We developed a specific protocol to configure, arm, and acquire data from either the Fast Ethernet port or the ATE bus. Trigger signals to arm and to start the data acquisition were included. There were no restrictions on the speed of the bus. We added a parallel interface between the HSI-2X15-DSO and the DUT board based on a modified IDE connector and then to the ATE pins from the test head. We made the sampling and utilization of the tester resources for clocking the acquisition system compatible with the existing UltraFLEX drivers and measurement libraries. The module had to fit in the UltraFLEX stiffener in order to be able to characterize and correlate signals on and off the tester. Figure 3 shows how two HSI-2X15-DSO modules can fit the UltraFLEX stiffener. We developed a software measurement library for the new instrument that was compatible with the existing TDSO The user used our library to correlate certain measurements with the existing UltraFLEX during bring up and the application development. Figure 4: Packaged result (4" x 5.6") Figure 3: HSI-2X15-DSO circuit board

9 Results All data analysis and calculations were performed on the host. The units were power by the DUT board and drew 2.1 Amps of a regular 5V supply. No additional cooling was required. The interface between the DUT card and the HSI-2X15-DSO was done with high performance coaxial cable and very well matched 26GHz edge launched connectors. We then correlated all measurements between the TDSO-050 and the HSI-2X15-DSO. The results were that measurement accuracy and throughput meet the user s requirements. The result was that the customer was able to deploy at-speed testing of the 44 Gb/s device on his existing fleet of UltraFLEX testers. Figure 5: Two instruments fit in UltraFLEX stiffener

10 Case Study 2: Testing Thunderbolt-class Device on V93K A customer needed to characterize and test a new device in the performance range of the Thunderbolt. Thunderbolt is new interconnect standard from Intel that was first available on new Apple Mac Book Pro notebooks. It supports two 10 Gb/s bi-directional channels on a common transport resulting in 40 Gb/s maximum aggregate throughput. PCI Express and DisplayPort protocols are supported on top of that transport. Our approach was to use the expertise of our partner, MultiLane SAL, to develop two new, high performance instruments that were compact enough to fit within the V93K stiffener. The block diagram below illustrates the plan for two channels only. In this application, we would need to support four channels. We developed two new instruments with footprints that could be stacked on top of each otheras well as fitting into the V93K stiffener. See load board photo next page. Since we did not want to use any tester resources, we installed an 8-port Ethernet switch that allowed the host controller to communicate with each of the eight instruments. We developed simple Linux-based drivers as shown ijn this sample script: client_socket_dso<<"connect:dso"; client_socket_dso>>reply; client_socket_bert<<"connect:bert"; client_socket_bert>>reply; client_socket_dso<<"configuredso"; // load script client_socket_dso>>reply; client_socket_bert<<"configurebert"; client_socket_bert>>reply; client_socket_dso<<"captureandmeasure"; client_socket_dso>>measurements; client_socket_bert<<"bertest"; client_socket_bert>>bertresult; client_socket_dso<<"exit"; client_socket_bert<<"exit";

11 The challenges we faced include the following: Thermal dissipation, the power dissipation of each BERT-JIT and DSO combination is about 20 Watts for a total of 80 watts for the 4 lane tester. This resulted in having to install a fan on the load board. We encountered initial repeatability issues, and traced it to power supply variation. We replaced the power supplies. We had few challenges supporting our customer remotely during the initial deployment and limited access to the tester to verify the code and to correlate. In the second phase of deployment we offered on-site support. We completed the integration, the calibration and optimized throughput to 800ms on all 4 channels in 8 days. Photo of V93K load board with 4x10G DSOs and 4x10-G BERTs with Jitter testing with details of close proximity of instruments and cabling to DUT.

Explore Efficient Test Approaches for PCIe at 16GT/s Kalev Sepp Principal Engineer Tektronix, Inc

Explore Efficient Test Approaches for PCIe at 16GT/s Kalev Sepp Principal Engineer Tektronix, Inc Explore Efficient Test Approaches for PCIe at 16GT/s Kalev Sepp Principal Engineer Tektronix, Inc Copyright 2015, PCI-SIG, All Rights Reserved 1 Disclaimer Presentation Disclaimer: All opinions, judgments,

More information

Successfully negotiating the PCI EXPRESS 2.0 Super Highway Towards Full Compliance

Successfully negotiating the PCI EXPRESS 2.0 Super Highway Towards Full Compliance Successfully negotiating the PCI EXPRESS 2.0 Super Highway Towards Full Compliance Page 1 Agenda Introduction PCIe 2.0 changes from 1.0a/1.1 Spec 5GT/s Challenges Error Correction Techniques Test tool

More information

Multi-Gigabit Interfaces for Communications/Datacomm

Multi-Gigabit Interfaces for Communications/Datacomm Multi-Gigabit Interfaces for Communications/Datacomm Richard Dugan, Drew Plant Hewlett-Packard Integrated Circuit Business Division email: richard_dugan@hp.com, drew_plant@hp.com 802.3 Meeting, Austin

More information

Keysight Technologies Characterizing and Verifying Compliance of 100Gb Ethernet Components and Systems. Application Brief

Keysight Technologies Characterizing and Verifying Compliance of 100Gb Ethernet Components and Systems. Application Brief Keysight Technologies Characterizing and Verifying Compliance of 100Gb Ethernet Components and Systems Application Brief Overview The expansion in Ethernet data bandwidth from 10Gb/s through 40G to 100G

More information

Selecting the Optimum PCI Express Clock Source

Selecting the Optimum PCI Express Clock Source Selecting the Optimum PCI Express Clock Source PCI Express () is a serial point-to-point interconnect standard developed by the Component Interconnect Special Interest Group (PCI-SIG). lthough originally

More information

Pericom PCI Express 1.0 & PCI Express 2.0 Advanced Clock Solutions

Pericom PCI Express 1.0 & PCI Express 2.0 Advanced Clock Solutions Pericom PCI Express 1.0 & PCI Express 2.0 Advanced Clock Solutions PCI Express Bus In Today s Market PCI Express, or PCIe, is a relatively new serial pointto-point bus in PCs. It was introduced as an AGP

More information

PCI-SIG ENGINEERING CHANGE NOTICE

PCI-SIG ENGINEERING CHANGE NOTICE PCI-SIG ENGINEERING CHANGE NOTICE TITLE: Separate Refclk Independent SSC Architecture (SRIS) DATE: Updated 10 January 013 AFFECTED DOCUMENT: PCI Express Base Spec. Rev. 3.0 SPONSOR: Intel, HP, AMD Part

More information

RF Measurements Using a Modular Digitizer

RF Measurements Using a Modular Digitizer RF Measurements Using a Modular Digitizer Modern modular digitizers, like the Spectrum M4i series PCIe digitizers, offer greater bandwidth and higher resolution at any given bandwidth than ever before.

More information

Eye Doctor II Advanced Signal Integrity Tools

Eye Doctor II Advanced Signal Integrity Tools Eye Doctor II Advanced Signal Integrity Tools EYE DOCTOR II ADVANCED SIGNAL INTEGRITY TOOLS Key Features Eye Doctor II provides the channel emulation and de-embedding tools Adds precision to signal integrity

More information

ISSCC 2003 / SESSION 4 / CLOCK RECOVERY AND BACKPLANE TRANSCEIVERS / PAPER 4.7

ISSCC 2003 / SESSION 4 / CLOCK RECOVERY AND BACKPLANE TRANSCEIVERS / PAPER 4.7 ISSCC 2003 / SESSION 4 / CLOCK RECOVERY AND BACKPLANE TRANSCEIVERS / PAPER 4.7 4.7 A 2.7 Gb/s CDMA-Interconnect Transceiver Chip Set with Multi-Level Signal Data Recovery for Re-configurable VLSI Systems

More information

LONGLINE QSFP+ SR4. Features. Applications. Description. Page 1 of 13

LONGLINE QSFP+ SR4. Features. Applications. Description. Page 1 of 13 LONGLINE QSFP+ SR4 Features 4 channels full-duplex transceiver modules Transmission data rate up to 10.5Gbps per channel 4 channels 850nm VCSEL array 4 channels PIN photo detector array Low power consumption

More information

PCI Express: The Evolution to 8.0 GT/s. Navraj Nandra, Director of Marketing Mixed-Signal and Analog IP, Synopsys

PCI Express: The Evolution to 8.0 GT/s. Navraj Nandra, Director of Marketing Mixed-Signal and Analog IP, Synopsys PCI Express: The Evolution to 8.0 GT/s Navraj Nandra, Director of Marketing Mixed-Signal and Analog IP, Synopsys PCIe Enterprise Computing Market Transition From Gen2 to Gen3 Total PCIe instances. 2009

More information

A Gigabit Transceiver for Data Transmission in Future HEP Experiments and An overview of optoelectronics in HEP

A Gigabit Transceiver for Data Transmission in Future HEP Experiments and An overview of optoelectronics in HEP A Gigabit Transceiver for Data Transmission in Future HEP Experiments and An overview of optoelectronics in HEP Ken Wyllie, CERN 1 Outline Optoelectronics What? Why? How? Experience in HEP (LHC) & future

More information

High-Speed Gigabit Data Transmission Across Various Cable Media at Various Lengths and Data Rate

High-Speed Gigabit Data Transmission Across Various Cable Media at Various Lengths and Data Rate Application Report SLLA091 - November 2000 High-Speed Gigabit Data Transmission Across Various Cable Media at Various Lengths and Data Rate Boyd Barrie, Huimin Xia ABSTRACT Wizard Branch, Bus Solution

More information

High-Definition Multimedia Interface (HDMI) Source/Sink Impedance Compliance Test Test Solution Overview Using the E5071C ENA Option TDR

High-Definition Multimedia Interface (HDMI) Source/Sink Impedance Compliance Test Test Solution Overview Using the E5071C ENA Option TDR High-Definition Multimedia Interface (HDMI) Source/Sink Impedance Compliance Test Using the E5071C ENA Option TDR Keysight Technologies Component Test Division Revision 01.10 2015/03/12 (YS) Reference

More information

The Boonton USB Peak Power Sensor, Wi-Fi ac Signals and the ETSI EN Standard

The Boonton USB Peak Power Sensor, Wi-Fi ac Signals and the ETSI EN Standard Application Note The Boonton 55006 USB Peak Power Sensor, Wi-Fi 802.11ac Signals and the ETSI EN 300 328 Standard Stephen Shaw Applications Engineer, Boonton Electronics Abstract This application note

More information

Using Pre-Emphasis and Equalization with Stratix GX

Using Pre-Emphasis and Equalization with Stratix GX Introduction White Paper Using Pre-Emphasis and Equalization with Stratix GX New high speed serial interfaces provide a major benefit to designers looking to provide greater data bandwidth across the backplanes

More information

Application Note. PCIEC-85 PCI Express Jumper. High Speed Designs in PCI Express Applications Generation 3-8.0 GT/s

Application Note. PCIEC-85 PCI Express Jumper. High Speed Designs in PCI Express Applications Generation 3-8.0 GT/s PCIEC-85 PCI Express Jumper High Speed Designs in PCI Express Applications Generation 3-8.0 GT/s Copyrights and Trademarks Copyright 2015, Inc. COPYRIGHTS, TRADEMARKS, and PATENTS Final Inch is a trademark

More information

Cloud-Based Apps Drive the Need for Frequency-Flexible Clock Generators in Converged Data Center Networks

Cloud-Based Apps Drive the Need for Frequency-Flexible Clock Generators in Converged Data Center Networks Cloud-Based Apps Drive the Need for Frequency-Flexible Generators in Converged Data Center Networks Introduction By Phil Callahan, Senior Marketing Manager, Timing Products, Silicon Labs Skyrocketing network

More information

Jitter in PCIe application on embedded boards with PLL Zero delay Clock buffer

Jitter in PCIe application on embedded boards with PLL Zero delay Clock buffer Jitter in PCIe application on embedded boards with PLL Zero delay Clock buffer Hermann Ruckerbauer EKH - EyeKnowHow 94469 Deggendorf, Germany Hermann.Ruckerbauer@EyeKnowHow.de Agenda 1) PCI-Express Clocking

More information

Transmission of High-Speed Serial Signals Over Common Cable Media

Transmission of High-Speed Serial Signals Over Common Cable Media Transmission of High-Speed Serial February 0 Introduction Technical Note TN066 Designers are often faced with moving serial data from one location to another, over moderate distances, and in the most efficient

More information

10Gb/s SFP+ LRM 1310nm FP with PIN Receiver 220meters transmission distance

10Gb/s SFP+ LRM 1310nm FP with PIN Receiver 220meters transmission distance Feature 10Gb/s serial optical interface compliant to 802.3aq 10GBASE-LRM Electrical interface compliant to SFF-8431 specifications for enhanced 8.5 and 10 Gigabit small form factor pluggable module SFP+

More information

Department of Electrical and Computer Engineering Ben-Gurion University of the Negev. LAB 1 - Introduction to USRP

Department of Electrical and Computer Engineering Ben-Gurion University of the Negev. LAB 1 - Introduction to USRP Department of Electrical and Computer Engineering Ben-Gurion University of the Negev LAB 1 - Introduction to USRP - 1-1 Introduction In this lab you will use software reconfigurable RF hardware from National

More information

The new frontier of the DATA acquisition using 1 and 10 Gb/s Ethernet links. Filippo Costa on behalf of the ALICE DAQ group

The new frontier of the DATA acquisition using 1 and 10 Gb/s Ethernet links. Filippo Costa on behalf of the ALICE DAQ group The new frontier of the DATA acquisition using 1 and 10 Gb/s Ethernet links Filippo Costa on behalf of the ALICE DAQ group DATE software 2 DATE (ALICE Data Acquisition and Test Environment) ALICE is a

More information

Module 13 : Measurements on Fiber Optic Systems

Module 13 : Measurements on Fiber Optic Systems Module 13 : Measurements on Fiber Optic Systems Lecture : Measurements on Fiber Optic Systems Objectives In this lecture you will learn the following Measurements on Fiber Optic Systems Attenuation (Loss)

More information

High-Speed SERDES Interfaces In High Value FPGAs

High-Speed SERDES Interfaces In High Value FPGAs High-Speed SERDES Interfaces In High Value FPGAs February 2009 Lattice Semiconductor 5555 Northeast Moore Ct. Hillsboro, Oregon 97124 USA Telephone: (503) 268-8000 www.latticesemi.com 1 High-Speed SERDES

More information

PCI Express* Ethernet Networking

PCI Express* Ethernet Networking White Paper Intel PRO Network Adapters Network Performance Network Connectivity Express* Ethernet Networking Express*, a new third-generation input/output (I/O) standard, allows enhanced Ethernet network

More information

PCI Express Transmitter PLL Testing A Comparison of Methods. Primer

PCI Express Transmitter PLL Testing A Comparison of Methods. Primer PCI Express Transmitter PLL Testing A Comparison of Methods Primer Primer Table of Contents Abstract...3 Spectrum Analyzer Method...4 Oscilloscope Method...6 Bit Error Rate Tester (BERT) Method...6 Clock

More information

Transmitter Characteristics (83D.3.1) Ryan Latchman, Mindspeed

Transmitter Characteristics (83D.3.1) Ryan Latchman, Mindspeed Transmitter haracteristics (83D.3.) Ryan Latchman, Mindspeed Transmit equalizer Transmitter equalizer range The AUI-4 chip-to-chip transmitter includes programmable equalization to compensate for the frequency-dependent

More information

Electrical Compliance Test Specification SuperSpeed Universal Serial Bus

Electrical Compliance Test Specification SuperSpeed Universal Serial Bus Electrical Compliance Test Specification SuperSpeed Universal Serial Bus Date: March 10, 2015 Revision: 1.0a SuperSpeed Electrical Compliance i Copyright 2015, USB Implementers Forum, Inc. All rights reserved.

More information

EMC countermeasures for High-Speed Differential Interfaces

EMC countermeasures for High-Speed Differential Interfaces TDK EMC Technology Practice Section EMC countermeasures for High-Speed Differential Interfaces How Do Common Mode Filters Suppress EMI in Differential Transmission Circuits? TDK Corporation Application

More information

AN1200.04. Application Note: FCC Regulations for ISM Band Devices: 902-928 MHz. FCC Regulations for ISM Band Devices: 902-928 MHz

AN1200.04. Application Note: FCC Regulations for ISM Band Devices: 902-928 MHz. FCC Regulations for ISM Band Devices: 902-928 MHz AN1200.04 Application Note: FCC Regulations for ISM Band Devices: Copyright Semtech 2006 1 of 15 www.semtech.com 1 Table of Contents 1 Table of Contents...2 1.1 Index of Figures...2 1.2 Index of Tables...2

More information

USB 3.0 CDR Model White Paper Revision 0.5

USB 3.0 CDR Model White Paper Revision 0.5 USB 3.0 CDR Model White Paper Revision 0.5 January 15, 2009 INTELLECTUAL PROPERTY DISCLAIMER THIS WHITE PAPER IS PROVIDED TO YOU AS IS WITH NO WARRANTIES WHATSOEVER, INCLUDING ANY WARRANTY OF MERCHANTABILITY,

More information

A+ Guide to Managing and Maintaining Your PC, 7e. Chapter 1 Introducing Hardware

A+ Guide to Managing and Maintaining Your PC, 7e. Chapter 1 Introducing Hardware A+ Guide to Managing and Maintaining Your PC, 7e Chapter 1 Introducing Hardware Objectives Learn that a computer requires both hardware and software to work Learn about the many different hardware components

More information

Equalization/Compensation of Transmission Media. Channel (copper or fiber)

Equalization/Compensation of Transmission Media. Channel (copper or fiber) Equalization/Compensation of Transmission Media Channel (copper or fiber) 1 Optical Receiver Block Diagram O E TIA LA EQ CDR DMUX -18 dbm 10 µa 10 mv p-p 400 mv p-p 2 Copper Cable Model Copper Cable 4-foot

More information

Jitter Transfer Functions in Minutes

Jitter Transfer Functions in Minutes Jitter Transfer Functions in Minutes In this paper, we use the SV1C Personalized SerDes Tester to rapidly develop and execute PLL Jitter transfer function measurements. We leverage the integrated nature

More information

Oscilloscope Bandwidth Requirements for Emerging Serial Data Interfaces

Oscilloscope Bandwidth Requirements for Emerging Serial Data Interfaces Oscilloscope Bandwidth Requirements for Emerging Serial Data Interfaces Page 1 What best determines bandwidth requirements? 5 th harmonic? Or spectral content of the signal, which is related to rise time?

More information

Electrical Compliance Test Specification SuperSpeed Universal Serial Bus

Electrical Compliance Test Specification SuperSpeed Universal Serial Bus Electrical Compliance Test Specification SuperSpeed Universal Serial Bus Date: September 14, 2009 Revision: 0.9 Preface 6/3/2009 Scope of this Revision The 0.7 revision of the specification describes the

More information

A 1.62/2.7/5.4 Gbps Clock and Data Recovery Circuit for DisplayPort 1.2 with a single VCO

A 1.62/2.7/5.4 Gbps Clock and Data Recovery Circuit for DisplayPort 1.2 with a single VCO JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.13, NO.3, JUNE, 2013 http://dx.doi.org/10.5573/jsts.2013.13.3.185 A 1.62/2.7/5.4 Clock and Data Recovery Circuit for DisplayPort 1.2 with a single VCO

More information

11. High-Speed Differential Interfaces in Cyclone II Devices

11. High-Speed Differential Interfaces in Cyclone II Devices 11. High-Speed Differential Interfaces in Cyclone II Devices CII51011-2.2 Introduction From high-speed backplane applications to high-end switch boxes, low-voltage differential signaling (LVDS) is the

More information

Keysight Technologies Forward Clocking - Receiver (RX) Jitter Tolerance Test with J-BERT N4903B High-Performance Serial BERT.

Keysight Technologies Forward Clocking - Receiver (RX) Jitter Tolerance Test with J-BERT N4903B High-Performance Serial BERT. Keysight Technologies Forward Clocking - Receiver (RX) Jitter Tolerance Test with J-BERT N4903B High-Performance Serial BERT Application Note Introduction J-BERT N4903B highperformance serial BERT with

More information

TC-3000C Bluetooth Tester

TC-3000C Bluetooth Tester TC-3000C Bluetooth Tester Product Overview TC-3000C Bluetooth Tester Data Sheet TC-3000C Bluetooth Tester is able to analyze the data of each packet that is transmitted to the upper application protocol

More information

Central Office Testing of Network Services

Central Office Testing of Network Services Central Office Testing of Network Services Rev 4 Application Note Ethernet is rapidly becoming the predominant method for deploying new commercial services and for expanding backhaul capacity. Carriers

More information

Dispersion penalty test 1550 Serial

Dispersion penalty test 1550 Serial Dispersion penalty test 1550 Serial Peter Öhlen & Krister Fröjdh Optillion Irvine, January 2001 Dispersion penalty test, 1550 serial Page 1 SMF Transmission at 1550 nm Different from multi-mode transmission

More information

Quick Reference Guide High Speed Input/Output Solutions

Quick Reference Guide High Speed Input/Output Solutions Quick Reference Guide The pluggable I/O interface offers significant advantages as a high speed I/O interconnect. With a standard equipment I/O interface and the flexibility of pluggable modules come the

More information

Clock Recovery Primer, Part 1. Primer

Clock Recovery Primer, Part 1. Primer Clock Recovery Primer, Part 1 Primer Primer Table of Contents Abstract...3 Why is Clock Recovery Used?...3 How Does Clock Recovery Work?...3 PLL-Based Clock Recovery...4 Generic Phased Lock Loop Block

More information

Low Speed Fiber Optic Link DO Engineering Note 3823.112-EN-397 Preliminary Jorge An1aral LAFEXlCBPF 05-02-94

Low Speed Fiber Optic Link DO Engineering Note 3823.112-EN-397 Preliminary Jorge An1aral LAFEXlCBPF 05-02-94 Low Speed Fiber Optic Link DO Engineering Note 3823.112-EN-397 Preliminary Jorge An1aral LAFEXlCBPF 05-02-94 This document describes the design of a low speed fiber opticallink.lt discusses the main issues

More information

8 Gbps CMOS interface for parallel fiber-optic interconnects

8 Gbps CMOS interface for parallel fiber-optic interconnects 8 Gbps CMOS interface for parallel fiberoptic interconnects Barton Sano, Bindu Madhavan and A. F. J. Levi Department of Electrical Engineering University of Southern California Los Angeles, California

More information

High Definition Oscilloscopes

High Definition Oscilloscopes PRELIMINARY High Definition Oscilloscopes HDO4000 and HDO6000 Key Features 12-bit ADC resolution, up to 15-bit with enhanced resolution 200 MHz, 350 MHz, 500 MHz, 1 GHz bandwidths Long Memory up to 250

More information

Large-Capacity Optical Transmission Technologies Supporting the Optical Submarine Cable System

Large-Capacity Optical Transmission Technologies Supporting the Optical Submarine Cable System Large-Capacity Optical Transmission Technologies Supporting the Optical Submarine Cable System INOUE Takanori Abstract As one of the foundations of the global network, the submarine cable system is required

More information

Timing Errors and Jitter

Timing Errors and Jitter Timing Errors and Jitter Background Mike Story In a sampled (digital) system, samples have to be accurate in level and time. The digital system uses the two bits of information the signal was this big

More information

Modular Instrumentation Technology Overview

Modular Instrumentation Technology Overview Modular Instrumentation Technology Overview Outline Overview of the PXI Platform PCI & PXI Express The Future of RF Leveraging Modular Instrumentation Mixed signal test Streaming RF Streaming Demo Summary

More information

NETWORK ENABLED EQUIPMENT MONITOR

NETWORK ENABLED EQUIPMENT MONITOR NETWORK ENABLED EQUIPMENT MONITOR Remotely Monitor Sensors over the Internet Connect Sensors to the Web to Remotely Monitor Equipment, Processes or Other Applications A Complete, Easy to Deploy, Stand-Alone

More information

Computer buses and interfaces

Computer buses and interfaces FYS3240 PC-based instrumentation and microcontrollers Computer buses and interfaces Spring 2011 Lecture #5 Bekkeng 15.1.2011 The most common data acquisition buses available today Internal computer buses

More information

Fibre Channel Disk Storage System Interface Speed Roadmap

Fibre Channel Disk Storage System Interface Speed Roadmap Fibre Channel Disk Storage System Interface Speed Roadmap 2003 EMC Corporation. All rights reserved. 1 Recommendations for future drive interfaces Needs to co-exist with 4G Arbitrated Loops Newer generation

More information

Agilent Technologies N5990A Test Automation Software Platform. Getting Started Guide

Agilent Technologies N5990A Test Automation Software Platform. Getting Started Guide Agilent Technologies N5990A Test Automation Software Platform Getting Started Guide Notices Agilent Technologies, Inc. 2008 No part of this manual may be reproduced in any form or by any means (including

More information

Transmission of fast signals via optical fibres

Transmission of fast signals via optical fibres Transmission of fast signals via optical fibres Michael Daniel for Richard White rw@ast.leeds.ac.uk 1 Digitizing the signal from an IACT camera: why fast signal transmission is needed. ns The Cherenkov

More information

Application Note. Line Card Redundancy Design With the XRT83SL38 T1/E1 SH/LH LIU ICs

Application Note. Line Card Redundancy Design With the XRT83SL38 T1/E1 SH/LH LIU ICs Application Note Design With the XRT83SL38 T1/E1 SH/LH LIU ICs Revision 1.3 1 REDUNDANCY APPLICATIONS INTRODUCTION Telecommunication system design requires signal integrity and reliability. When a T1/E1

More information

10Gbps XFP Bi-Directional Transceiver, 10km Reach 1270/1330nm TX / 1330/1270 nm RX

10Gbps XFP Bi-Directional Transceiver, 10km Reach 1270/1330nm TX / 1330/1270 nm RX Features 10Gbps XFP Bi-Directional Transceiver, 10km Reach 1270/1330nm TX / 1330/1270 nm RX Supports 9.95Gb/s to 10.5Gb/s bit rates Hot-pluggable XFP footprint Maximum link length of 10km with SMF 1270/1330nm

More information

Introduction to PCI Express Positioning Information

Introduction to PCI Express Positioning Information Introduction to PCI Express Positioning Information Main PCI Express is the latest development in PCI to support adapters and devices. The technology is aimed at multiple market segments, meaning that

More information

CX380X Advanced Spectrum and Burst QAM Analyzer

CX380X Advanced Spectrum and Burst QAM Analyzer Advanced Spectrum and Burst QAM Analyzer Preventative Network Monitoring With VeEX s VeSion system, the s advanced Spectrum Analyzer and Bursty Demodulator captures rogue cable modems and provides proactive

More information

Interfacing Intel 8255x Fast Ethernet Controllers without Magnetics. Application Note (AP-438)

Interfacing Intel 8255x Fast Ethernet Controllers without Magnetics. Application Note (AP-438) Interfacing Intel 8255x Fast Ethernet Controllers without Magnetics Application Note (AP-438) Revision 1.0 November 2005 Revision History Revision Revision Date Description 1.1 Nov 2005 Initial Release

More information

Fiber Optic Connectivity SECURITY SURVEILLANCE SOLUTIONS. ComNet Managed Ethernet Switches

Fiber Optic Connectivity SECURITY SURVEILLANCE SOLUTIONS. ComNet Managed Ethernet Switches ComNet Fiber Optic and Ethernet Transmission Equipment is setting the standard for value and performance. ComNet is a major provider of video, audio and data transmission, and network communication solutions

More information

81110A Pulse Pattern Generator Simulating Distorted Signals for Tolerance Testing

81110A Pulse Pattern Generator Simulating Distorted Signals for Tolerance Testing 81110A Pulse Pattern Generator Simulating Distorted Signals for Tolerance Testing Application Note Introduction Industry sectors including computer and components, aerospace defense and education all require

More information

DTSB35(53)12L-CD20 RoHS Compliant 1.25G 1310/1550nm(1550/1310nm) 20KM Transceiver

DTSB35(53)12L-CD20 RoHS Compliant 1.25G 1310/1550nm(1550/1310nm) 20KM Transceiver 产 品 规 格 书 Product Specification Sheet DTSB35(53)12L-CD20 RoHS Compliant 1.25G 1310/1550nm(1550/1310nm) 20KM Transceiver PRODUCT FEATURES Up to 1.25Gb/s data links FP laser transmitter for DTSB35(53)12L-CD20

More information

1+1 PROTECTION WITHOUT RELAYS USING IDT82V2044/48/48L & IDT82V2054/58/58L HITLESS PROTECTION SWITCHING

1+1 PROTECTION WITHOUT RELAYS USING IDT82V2044/48/48L & IDT82V2054/58/58L HITLESS PROTECTION SWITCHING 1+1 PROTECTION WITHOUT RELAYS USING IDT82V2044/48/48L & IDT82V2054/58/58L APPLICATION NOTE AN-357 1.0 INTRODUCTION In today's highly competitive market, high quality of service, QOS, and reliability is

More information

LLRF. Digital RF Stabilization System

LLRF. Digital RF Stabilization System LLRF Digital RF Stabilization System Many instruments. Many people. Working together. Stability means knowing your machine has innovative solutions. For users, stability means a machine achieving its full

More information

Digital Fundamentals

Digital Fundamentals Digital Fundamentals Tenth Edition Floyd Chapter 1 2009 Pearson Education, Upper 2008 Pearson Saddle River, Education NJ 07458. All Rights Reserved Analog Quantities Most natural quantities that we see

More information

Experiment 7: Familiarization with the Network Analyzer

Experiment 7: Familiarization with the Network Analyzer Experiment 7: Familiarization with the Network Analyzer Measurements to characterize networks at high frequencies (RF and microwave frequencies) are usually done in terms of scattering parameters (S parameters).

More information

Nutaq. PicoDigitizer 125-Series 16 or 32 Channels, 125 MSPS, FPGA-Based DAQ Solution PRODUCT SHEET. nutaq.com MONTREAL QUEBEC

Nutaq. PicoDigitizer 125-Series 16 or 32 Channels, 125 MSPS, FPGA-Based DAQ Solution PRODUCT SHEET. nutaq.com MONTREAL QUEBEC Nutaq PicoDigitizer 125-Series 16 or 32 Channels, 125 MSPS, FPGA-Based DAQ Solution PRODUCT SHEET QUEBEC I MONTREAL I N E W YO R K I nutaq.com Nutaq PicoDigitizer 125-Series The PicoDigitizer 125-Series

More information

AXIe: AdvancedTCA Extensions for Instrumentation and Test

AXIe: AdvancedTCA Extensions for Instrumentation and Test AXIe: AdvancedTCA Extensions for Instrumentation and Test November 2012 Copyright 2012 AXIe Consortium, Inc. * AdvancedTCA is a registered trademark of PICMG. AXIe is a registered trademark of the AXIe

More information

XFP Optical Receiver, 80km Reach

XFP Optical Receiver, 80km Reach Features Supports 9.95Gb/s to 11.1Gb/s bit rates Hot-pluggable XFP footprint Maximum link length of 80km with SMF APD ROSA receiver XFP MSA package with duplex LC connector No reference clock required

More information

Designing the NEWCARD Connector Interface to Extend PCI Express Serial Architecture to the PC Card Modular Form Factor

Designing the NEWCARD Connector Interface to Extend PCI Express Serial Architecture to the PC Card Modular Form Factor Designing the NEWCARD Connector Interface to Extend PCI Express Serial Architecture to the PC Card Modular Form Factor Abstract This paper provides information about the NEWCARD connector and board design

More information

Appendix A. by Gordon Getty, Agilent Technologies

Appendix A. by Gordon Getty, Agilent Technologies Appendix A Test, Debug and Verification of PCI Express Designs by Gordon Getty, Agilent Technologies Scope The need for greater I/O bandwidth in the computer industry has caused designers to shift from

More information

Advanced Modulation Formats in Data Centre Communications Michael J. Wale Director Active Products Research

Advanced Modulation Formats in Data Centre Communications Michael J. Wale Director Active Products Research Advanced Modulation Formats in Data Centre Communications Michael J. Wale Director Active Products Research 2 nd Symposium on Optical Interconnects in Data Centres ECOC, Cannes, 23rd September 2014 1 2014

More information

Using FPGAs to Design Gigabit Serial Backplanes. April 17, 2002

Using FPGAs to Design Gigabit Serial Backplanes. April 17, 2002 Using FPGAs to Design Gigabit Serial Backplanes April 17, 2002 Outline System Design Trends Serial Backplanes Architectures Building Serial Backplanes with FPGAs A1-2 Key System Design Trends Need for.

More information

Integrating PCI Express into the PXI Backplane

Integrating PCI Express into the PXI Backplane Integrating PCI Express into the PXI Backplane PCI Express Overview Serial interconnect at 2.5 Gbits/s PCI transactions are packetized and then serialized Low-voltage differential signaling, point-to-point,

More information

ChipScope Pro Tutorial

ChipScope Pro Tutorial ChipScope Pro Tutorial Using an IBERT Core with ChipScope Pro Analyzer Xilinx is disclosing this user guide, manual, release note, and/or specification (the Documentation ) to you solely for use in the

More information

The Effect of Network Cabling on Bit Error Rate Performance. By Paul Kish NORDX/CDT

The Effect of Network Cabling on Bit Error Rate Performance. By Paul Kish NORDX/CDT The Effect of Network Cabling on Bit Error Rate Performance By Paul Kish NORDX/CDT Table of Contents Introduction... 2 Probability of Causing Errors... 3 Noise Sources Contributing to Errors... 4 Bit Error

More information

IAT-1710E Integrated Access Tester

IAT-1710E Integrated Access Tester IAT-1710E Integrated Access Tester Features A number of ways to verify channel bandwidth, support for symmetric and asymmetric RFC2544 test Original high-speed PING test function, can be arbitrary set

More information

ACRS 2.0 User Manual 1

ACRS 2.0 User Manual 1 ACRS 2.0 User Manual 1 FCC Regulatory Information This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause harmful interference,

More information

SFP-SX with DOM 1.25Gb/s Multi-Mode SFP Transceiver 1000BASE-SX 1.0625Gb/s Fiber Channel

SFP-SX with DOM 1.25Gb/s Multi-Mode SFP Transceiver 1000BASE-SX 1.0625Gb/s Fiber Channel Product Features Compliant to IEEE Std 802.3-2005 Gigabit Ethernet 1000Base-SX, with DOM Specifications according to SFF-8074i and SFF-8472, revision 9.5 Digital Diagnostic Monitoring 850nm Vertical Cavity

More information

The Bus (PCI and PCI-Express)

The Bus (PCI and PCI-Express) 4 Jan, 2008 The Bus (PCI and PCI-Express) The CPU, memory, disks, and all the other devices in a computer have to be able to communicate and exchange data. The technology that connects them is called the

More information

Duobinary Modulation For Optical Systems

Duobinary Modulation For Optical Systems Introduction Duobinary Modulation For Optical Systems Hari Shanar Inphi Corporation Optical systems by and large use NRZ modulation. While NRZ modulation is suitable for long haul systems in which the

More information

Network Design. Yiannos Mylonas

Network Design. Yiannos Mylonas Network Design Yiannos Mylonas Physical Topologies There are two parts to the topology definition: the physical topology, which is the actual layout of the wire (media), and the logical topology, which

More information

Outlines. LECTURE 3: Wireless Transmission Technologies. Wireless Transmission on Unguided Media

Outlines. LECTURE 3: Wireless Transmission Technologies. Wireless Transmission on Unguided Media LECTURE 3: Wireless Transmission Technologies CIS 472 Wireless Communications and Networks Winter 2016 Instructor: Dr. Song Xing Outlines Wireless Data Transmission Modulation Spread Spectrum Department

More information

MODULATION Systems (part 1)

MODULATION Systems (part 1) Technologies and Services on Digital Broadcasting (8) MODULATION Systems (part ) "Technologies and Services of Digital Broadcasting" (in Japanese, ISBN4-339-62-2) is published by CORONA publishing co.,

More information

Clock Recovery in Serial-Data Systems Ransom Stephens, Ph.D.

Clock Recovery in Serial-Data Systems Ransom Stephens, Ph.D. Clock Recovery in Serial-Data Systems Ransom Stephens, Ph.D. Abstract: The definition of a bit period, or unit interval, is much more complicated than it looks. If it were just the reciprocal of the data

More information

TAN-030 Application Note Performance Characteristics of the XRT7300 Device for DS3 Applications Rev. 1.00

TAN-030 Application Note Performance Characteristics of the XRT7300 Device for DS3 Applications Rev. 1.00 APPLICATION NOTE PERFORMANCE CHARACTERISTICS OF THE XRT7300 DEVICE FOR DS3 APPLICATIONS 1 Table of Contents Table of Contents... 2 1.0 INTRODUCTION... 3 2.0 TRANSMIT OUTPUT PULSE TEMPLATE MEASUREMENTS

More information

Jitter Measurements in Serial Data Signals

Jitter Measurements in Serial Data Signals Jitter Measurements in Serial Data Signals Michael Schnecker, Product Manager LeCroy Corporation Introduction The increasing speed of serial data transmission systems places greater importance on measuring

More information

RGAINC Presents. Wireless Solutions for Closed Loop Systems and Other ITS Traffic Applications

RGAINC Presents. Wireless Solutions for Closed Loop Systems and Other ITS Traffic Applications RGAINC Presents Wireless Solutions for Closed Loop Systems and Other ITS Traffic Applications Presentation Outline The Basic Wireless Installation Radio Features for Traffic Applications The Wireless Site

More information

10-3. SYSTEM TESTING AND DOCUMENTATION

10-3. SYSTEM TESTING AND DOCUMENTATION 10-3. SYSTEM TESTING AND DOCUMENTATION System testing and documentation must cover pre-installation testing, sub-system testing, fiber optic cable testing, video link testing, data link testing, acceptance

More information

High speed pattern streaming system based on AXIe s PCIe connectivity and synchronization mechanism

High speed pattern streaming system based on AXIe s PCIe connectivity and synchronization mechanism High speed pattern streaming system based on AXIe s connectivity and synchronization mechanism By Hank Lin, Product Manager of ADLINK Technology, Inc. E-Beam (Electron Beam) lithography is a next-generation

More information

power rid B ge C o m p u t e r

power rid B ge C o m p u t e r power ridge B Computer powerbridge Computer Founded in 1993, Headquartered in Burgwedel / Hannover Distribution of computer boards and systems into telecom, industrial automation, traffic control, and

More information

ISSCC 2003 / SESSION 13 / 40Gb/s COMMUNICATION ICS / PAPER 13.7

ISSCC 2003 / SESSION 13 / 40Gb/s COMMUNICATION ICS / PAPER 13.7 ISSCC 2003 / SESSION 13 / 40Gb/s COMMUNICATION ICS / PAPER 13.7 13.7 A 40Gb/s Clock and Data Recovery Circuit in 0.18µm CMOS Technology Jri Lee, Behzad Razavi University of California, Los Angeles, CA

More information

DEVELOPMENT OF DEVICES AND METHODS FOR PHASE AND AC LINEARITY MEASUREMENTS IN DIGITIZERS

DEVELOPMENT OF DEVICES AND METHODS FOR PHASE AND AC LINEARITY MEASUREMENTS IN DIGITIZERS DEVELOPMENT OF DEVICES AND METHODS FOR PHASE AND AC LINEARITY MEASUREMENTS IN DIGITIZERS U. Pogliano, B. Trinchera, G.C. Bosco and D. Serazio INRIM Istituto Nazionale di Ricerca Metrologica Torino (Italia)

More information

LONGLINE 10Gbps 10km SFP+ Optical Transceiver

LONGLINE 10Gbps 10km SFP+ Optical Transceiver LONGLINE 10Gbps 10km SFP+ Optical Transceiver Features Optical interface compliant to IEEE 802.3ae 10GBASE-LR Electrical interface compliant to SFF-8431 Hot Pluggable 1310nm DFB transmitter, PIN photo-detector

More information

KVPX CONNECTOR SERIES HIGH SPEED SIGNAL INTEGRITY REPORT

KVPX CONNECTOR SERIES HIGH SPEED SIGNAL INTEGRITY REPORT KVPX CONNECTOR SERIES HIGH SPEED SIGNAL INTEGRITY REPORT CONTENTS 1 2 3 3 3 3 3 4 4 4 5 6 7 HIGH SPEED DATA TRANSFER Market Drivers for High Speed Signal Integrity Key Characteristics Impedance Matching

More information

An Overview of the Electrical Validation of 10BASE-T, 100BASE-TX, and 1000BASE-T Devices

An Overview of the Electrical Validation of 10BASE-T, 100BASE-TX, and 1000BASE-T Devices An Overview of the Electrical Validation of 10BASE-T, 100BASE-TX, and 1000BASE-T Devices Application Note The number of devices that come with a built-in network interface card has risen steadily and will

More information

AFG-100/200 series USB Modular Arbitrary Function Generator. Date: Oct, 2014

AFG-100/200 series USB Modular Arbitrary Function Generator. Date: Oct, 2014 AFG-100/200 series USB Modular Arbitrary Function Generator Date: Oct, 2014 Outline Product Overview Feature, Advantage and Benefit Comparison Chart Ordering Information 22 Product information AFG-125,

More information