Hybrid Platform Application in Software Debug

Transcription

1 Hybrid Platform Application in Software Debug Jiao Feng July

2 Software costs in SoC development 2

3 Early software adoption Previous Development Process IC Development RTL Design Physical Design SW Development Rev A0 Tape-out & Fab Rev A0 IC Bring-up Validation, Debug RTL Bug-fix & Feature Add Rev B0 Tape-out & Fab All-Layer Rev IC Validation Platform SW Development on SOC RTL Bug-fix Rev B1 Tape-out & Fab Metal Rev IC Validation Qual Tests Customer Validation & Network Integration IC Mass Production Ship SoC with poor Quality SW Customer SOC Launch New Development Process IC Development RTL Design Verification on Emulator/FPGA Physical Design Rev A0 Tape-out & Fab Rev A0 IC Bring-up Validation, Debug RTL Bug-fix Rev A1 Tape-out & Fab Metal Rev IC Validation Qual Tests IC Mass Production SW Development on Emulator/FPGA SW Development Platform SW Integration on SOC Customer Validation & Network Integration Customer SOC Launch High SW quality and cycle time reduction due to early SW adoption 3

4 Challenges for early software adoption SW teams have become the long pole in delivering SOC on time and with high quality Exploring Fixed Virtual Platforms for early SW Development Full Virtual Prototypes have a high cost of entry and lack accuracy Current Emulation solutions are too slow for the OS Based SW tasks Meeting SW teams needs with FPGA Prototypes becoming more difficult Earlier access can only occur with dirtier RTL, which is difficult with FPGA compile times and challenging debug Increased design complexity of multi-core/multi-cluster is exceeding the capacity of FPGA systems 4

5 Early, High-Performance SW Execution on Palladium Exclusive solution combines the best characteristics of emulation and virtual platforms 5

6 Improved HW/SW debug capability 6

7 The Palladium/VSP Hybrid Solution The Palladium/VSP Hybrid addresses the need for fast execution speed, to boot operating systems and execute applications. It does this by replacing the RTL CPU and memory with a virtual model that runs 50 times faster. Customer Design in Palladium VSP Virtual Models UART, emmc, USB Integration APIs Customer Virtual Models Virtualized CPU Sub-system CPU AVIP Bridges Smart Memory AMBA, interrupts, resets DDR Memory Controller GPU RTL Fabric IP IP IP SW Integrator VSP Execution Engines Palladium Architected for SW Performance Designed to integrate HW and SW flows High-speed virtual platform Does not require changes to HW or SW stacks Asynchronous HW/SW Execution with Interrupt driven sync Virtual connections into SW Engineer s environments High-Speed Multi-Domain Memory Coherency Seamless hybrid execution for both HW and SW users 7

8 Palladium Hybrid Focus: Kernel, Drivers, Android, Linux-based tests Compute Subsystem SOC Mode Config, Init Test Bench Assembly, Config A53 x 4 A57 x 2 CPU Coherent Sub-system FabricRTL I/F CPU Sub-system RTL I/F Memory Controller DDR MM CCI400 M4 SCP System Control Processor UART INTC Timer SCP RAM GPU Peripheral Fabric System Scratch RAM emmc SDIO USB2 USB3 SATA Boot Code System Control Processor Security GPU Micro- Code -Boot Code -BM Driver -BM Test Application Processor Kernel / OS, Android Application Processor OS Drivers Power Management Real- World Tests (i.e. OGL) Firmware OS-Based SW 8

9 Hybrid Components and Insertion Virtual Comps ARM Fast Model Smart Memory(systemc part) Re-configurable router model, etc. RTL Comps Rest RTLs(removed cpu core and replaced memory by smart memory model Bridge Comps TLM/RTL Bridge Reset and interrupts Manager Fast Processor Model TLM2 ACE Compute amba_pv Subsystem A15 x 4 A7 x 2 A7 x 4 Reconfigurable Interconnect TLM Smart Memory DDR TLM/RTL Bridge SW Integrator RTL I/F CPU Coherent Sub-system Fabric RTL I/F CPU Sub-system RTL I/F CCI400 Resets Enet Interrupt Manager GIC400 UARTs Timers UARTs Virtual Comps Bridge Comps Interrupt s GPX Peripheral Fabric SW Integrator Solution Loader Reset Manager CPU Wrapper Customer Design emmc SDIO emmc RTL Comps SWI packages makes it easier to do CPU and memory Hybrid integration Memory Controller Smart Memory Smart DDR3 DDR MM Scratch Ram M0 CSI DSI I2C Display USB2 USB3 etc 9

10 Hybrid at SPREADTRUM The following diagram shows all the components in Whale Hybrid environment: Usage: Boot kernel Boot OS Run real world applications Run benchmark VSP debugger Lauterbach/DS5 10

11 Performance Result Linux kernel boot Palladium only = 1 hour Hybrid = 60 secs Android Palladium only = Hours* Hybrid = 6 mins 11

12 Conclusion Enables high-performance execution of SOC SW with RTL and is suitable for bare mental SW, OS, device drivers, test applications on OS. Enable co-develop and co-verify pre-silicon HW designs. Run Linux kernel boot and android boot near FPGA speed. Has advanced debug tools to facilitate SW debug and HW debug. High quality SW on silicon arrival and contribute to smoother bring-up Cut down time from design to market. 12

13 THANK YOU!