Improved NAND Flash Memories Storage Reliablity Using Nonlinear Multi Error Correction Codes

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1 Improved NAND Flash Memories Storage Reliablity Using Nonlinear Multi Error Correction Codes R.Naresh Naik 1, P.Siva Nagendra Reddy 2, E. Ramakrishna Naik 3 1 M.Tech (VLSI System Design ),Dept.of ECE. 2 Asst.Professor, Dept. of ECE, KUPPAM ENGINEERING COLLEGE,KUPPAM 3 Asst.Professor, Dept. of ECE,S.K.D ENGINEERING COLLEGE,ANANTAPURAM ABSTRACT: Multi-level cell (MLC) NAND flash memories are popular storage media because of their power efficiency and large storage density. Conventional reliable MLC NAND flash memories based on BCH codes or Reed-Solomon (RS) codes have a large number of undetectable and miscorrected errors. Moreover, standard decoders for BCH and RS codes cannot be easily modified to correct errors beyond their error correcting capability t = [d-1/2], where d is the Hamming distance of the code. In this paper, we propose two general constructions of nonlinear multi-error correcting codes based on concatenations or generalized from Vasil ev codes. The proposed constructions can generate nonlinear bit-error correcting or digit-error correcting codes with very few or even no errors undetected or miscorrected for all code words. Moreover, codes generated by the generalized Vasil ev construction can correct some errors with multiplicities larger than t without any extra overhead in area, latency, and power consumption compared to schemes where only errors with multiplicity up to t are corrected. The design of reliable MLC NAND flash architectures can be based on the proposed nonlinear multi-error correcting codes. The reliability, area overhead and the penalty in latency and power consumption of the architectures based on the proposed codes are compared to architectures based on BCH codes and RS codes. The results show that using the proposed nonlinear error correcting codes for the protection of MLC NAND flash memories can reduce the number of errors undetected or miscorrected for all codewords to be almost 0 at the cost of less than 20% increase in power and area compared to architectures based on BCH codes and RS codes. the memory cell transistor until the multi-level cell (MLC) technology was developed and implemented in MLC technology is based on the ability to precisely control the amount of charge stored into the floating gate of the memory cell for he purpose of setting the threshold voltage to a number of different levels corresponding to different logic values, which enables the storage of multiple bits per cell. However, the increased number of programming threshold voltage levels has a negative impact on the reliability of the device due to the reduced operational margin. The raw bit error rate of the MLC NAND flash memory is around 10 and is at least two orders of magnitude worse than that of the single level cell (SLC) NAND flash memory. Moreover, the same reliability concerns as for SLC NAND flash memories, e.g., program/read disturb, data retention, programming/erasing endurance, and soft errors [may become more significant for MLC NAND flash memories. Hence a powerful error correcting code (ECC) that is able to correct at least 4-bit errors is required for the MLC NAND flash memories to achieve an acceptable application bit error rate, which is no larger than 10. Several works have investigated the use of linear block codes to improve the reliability of MLC NAND flash memories. In, the authors presented a highthroughput and low-power ECC Key words: Multi-error correcting codes, nonlinear codes, re-liable memory. I. INTRODUCTION The semiconductor industry has witnessed an explosive growth of the NAND flash memory market in the past several decades. Due to its high data transfer rate, low power consumption, large storage density and long mechanical durability, the NAND flash memories are widely used as storage media for devices such as portable media players, digital cameras, cell phones, and low-end netbooks. The increase of the storage density and the reduction of the cost per bit of flash memories were traditionally achieved by the aggressive scaling of NAND flash memory chip incorporating a 250 MHz BCH error correcting architecture was shown. The author of demonstrated that the use of strong BCH codes (e.g.,t= 12,15,67,102) can effectively increase the number of bits/cell thus further increasing the storage capacity of MLC NAND flash memories. In, an adaptive-rate ECC architecture based on BCH codes was proposed. The design had four operation modes with different error correcting capabilities. An ECC architecture based on Reed-Solomon (RS) codes of length 8 28 and 820 information digits constructed over was ISSN: Page 50

2 proposed in, which can correct all bit errors of maximizing the error detection and correction multiplicity less than or equal to four. The capabilities of the code. architecture achieves higher throughput, requires less area overhead for the encoder and the decoder 3.2 Algorithm and Properties but needs 32 more redundant bits than architectures based on BCH codes with the same error correcting capability. In, an architecture based on asymmetric limited-magnitude error correcting code was proposed, which can correct all asymmetric errors of multiplicitie s up to. II. MLC NAND FLASH MEMORIES Multi-level cell is able to store multiple bits by precisely controlling the threshold voltage level of the cell. In practice, the threshold voltage of the whole memory array satisfies a Gaussian distribution due t o random manufacturing variations. The data of the NAND flash memory is organized in blocks. Each b lock consists of a number of pages. Each p age stores data byte s and spare bytes. Cells in the spare area are physically the same as cells in the rest of the page and are typically used for overhead functions such as ECC and wear-leveling. The proportion of the spare bytes in the total number of bytes per page is usually 3%, e.g., 64 spare bytes for 2048 data bytes. More spare bytes may be required as the page size increases, e.g., 218 spare bytes for 4096 data bytes. Due to the existence of spare bytes, the number of redundant bits of the error correcting codes used for NAN D flash memories is not as crit- ical as for other types of memories such a s SRAM and DRAM where the area overhead is mostly determined by the number of redundant bits. This allows for a flexible design of more powerful error correcting codes for NAND flash memories. III. ERROR CORRECTING ALGORITHMS 3.1 Parameters of the Selected Code For the protection of MLC NAND flash memories, we propose to use a (8281, 8201, 11) nonlinear 5-errorcorrecting code with n1 = 8270, k1 = 8200, n2 = 11, k2 = 1. The detailed construction of the code is described below. All the algorithms and analysis in this section are also applicable to codes with other lengths and correcting capabilities. Denote by c = (x1, x2, x3) a codeword of the nonlinear t-error-correcting codes constructed as in Theorem 1. Let V be a (8270, 8200, 11) linear BCH code. To simplify the encoding and decoding procedures, we select {(u, Pu)} to be a repetition code with k2 = 1 and r2 = 10. f=gf( ) or GF(2 10 ) is chosen to be a quadratic perfect nonlinear function with Pf = 2 10 for the purpose of In this section we present the error correction algorithm for the case when {(u, Pu)} is a repetition code with k2 = 1 and r2 = d 2. We also assume that f is a perfect nonlinear function with Pf = 2 r2. The error will be corrected only if at least one of the information bits is distorted. If all errors are in the redundant bits, no correction will be attempted. In addition to errors that are miscorrected by all the code words, there are also errors which are conditionally miscorrected by the nonlinear t-error-correcting codes. However, these errors usually have high multiplicities. Moreover, most of the conditionally miscorrected errors are only miscorrected with a probability of 2 r2 = Thereby, the existence of conditionally miscorrected errors will not compromise the reliability of NAND flash memories protected by the nonlinear t error-correcting codes. There is only one error which is undetectable by the proposed nonlinear 5-errorcorrecting code. All the other errors will be detected with a probability of at least while most of them will always be detected. When error stays for several clock cycles, the probability that the error will be detected and successfully located will drastically increase. We note that the enhanced capability of the proposed nonlinear 5-errorcorrecting code to detect and correct repeating errors is very helpful for MLC NAND flash memories for the protection of hardware malfunctions such as data retention and programming/erasing endurance failure. Due to the decreased programming voltage margin, data retention is more likely to happen for MLC technology than for SLC technology. The problem of programming/erasing endurance also becomes more serious for MLC NAND flash memories, for which the typical number of supported program/ erase cycles is fewer than Errors introduced by these hardware failures will never disappear or will only disappear after the next erasing or programming operation. Hence, the proposed nonlinear t-error-correcting code with stronger error detection and correction capability for repeating errors can be used together with other protection schemes to efficiently detect these failures and protect the devices against them. Example :Algoritham1: Error Correcting Algorithm in non linear Multi Error correcting codes in Theorem is Input: C =(x1 -,x2 -,x3 - ) Output:e=(e1,e2,e3),ERR 1. begin 2. Decode V, Compute S; 3. If Ev =0,S=0 then ISSN: Page 51

3 4. No errors are detected ERR=0; During each clock cycle, the 10 most significant 5. else if Ev=0,S 0 then bits in the shift register are XORed with the new input 6. Uncorrectable multi errors are detected, ERR=1; and then multiplied by. The output of the multiplier is 7. else if Ev=-1,then XORed with the shifted data from the shift register to 8. Uncorrectable multi errors are detected,err=1; generate the input to the register. The top half of the 9. else architecture is for the computation of nonlinear redundant 10. Ev >0; bits. During the even-numbered clock cycles, the 10-bit 11. If e 1=0 input is buffered. During the odd-numbered clock cycles, 12. Error in the redundant digits are detected, the buffered data is multiplied by the new input in and 13. ERR=0 then added to the output registers. A 10-bit mask is 14. Else XORed with the data in the output register to generate the 15. Compute x1 = x1 e1, x2 = x2 e2 ; nonlinear redundant bits. For the (8281,8201,11) Compute ŝ=f(x1 x2 ); errorcorrecting code, 820 clock cycles are required to 17. If ŝ=0 then complete the encoding of the message. 18. e=(e1,e2,e3),err=0; The encoder for the (8280,8200,11) nonlinear else bit error correcting code based on Theorem 1 is similar to 20. Uncorrectable Multi errors are detected, the one shown 21. ERR=1 IV. HARDWARE DESIGN OF THE ENCODER AND THE DECODER FOR NONLINEAR MULTI-ERROR CORRECTING CODES In this section, we present the encoder and the decoder architectures for the proposed nonlinear multi error correcting codes. We estimate the area, the latency and the power consumption of the proposed architectures and compare the m to architectures based on BCH codes an d RS codes (see Section V). Fig. 2: Architecture of the encoder for the (8281,8201,11) nonlinear 5-errorcorrecting Code. in Fig. 2. The same structure (top half) is used to compute the 10-bit nonlinear redundant bits. The main 4.1. Encoder Architecture difference between the two encoders is as follows. First, the encoder for the (8280,8200,11) code does not The encoder for BCH codes and RS codes are require a separate port for msb.all information bits are conventionally implemented based on a linear feedback input via msg in 820 clock cycles, assuming a shift register (LFSR ) architecture. Both the serial and parallelism level of 10. Second, the encoding of the the parallel structures for LFSRs are well studied in the (8280,8200,11) code needs one more clock cycle to community. In general, the serial LFSR needs clock complete compared to the (8281,8201,11) code. At the cycles while the parallel LFSR needs only clock 821th clock cycle, the input to (Fig. 2) is switched to cycles to finish the computation of the redundant bits at the already-generated nonlinear check bits using a 10- the cost of higher hardware complexity, where is the bit 2:1 multiplexer. The former, however, requires that number of information bits and is the parallelism all operations are performed in GF(2 10 ). level of the LFSRs. Compared to the encoder for the BCH codes and RS codes, the encoder for the proposed 4.2. Decoder Architecture nonlinear multi error correcting codes requires one more finite field multiplier and correcting code The decoding of the proposed nonlinear multi - generated by Theorem 3 is shown in Fig. 2. The design error correcting Codes polynomial generation block is based on the parallel LFSR proposed in [26]. The and the Chien search block. Compared to the decoder parallelism level of the design is 10. During each clock for the BCH codes, the decoder for the R S codes cycle, 10 information bits are inputted to the encoder. requires one more block to compute the error The most significant bit of the message is input via a magnitude. We next briefly discuss the implementation separate port. The first information bit for the BCH c of the above four blocks and then present the decoder code is derived by XORing with the first bit of at the o architecture for the proposed nonlinear multi- error first clock cycle (when as shown in the figure). The d correcting codes. bottom half of the architecture is a parallel LFSR used Error Locator Polynomial Generation to generate the redundant bits for BCH codes. is a 10 x e 70 binary matrix. After the syndromes of are the computed, no nlinear the redu error ndant bits. s The ISSN: Page 52

4 locator polynomial Λ will be generated using Berlekamp-Massey(BM) algorithm. The hardware implementations of the BM algorithms have been well studied in the community. In our design a fully serial structure is used to minimize the area overhead. The design mainly requires three multipliers in GF (2 m ) and two FIFOs. The error locator polynomial Λ of degree t can be generated in t(t + 3)/2 clock cycles are required to generate the error locator polynomial Λ. When t = 5, the number of clock cycles needed is Chien Search Denote by the primitive element in GF(2 m ). The Chien search algorithm exhaustively tests whether i is a root of the error locator polynomial Λ. If Λ( i ) = 0, the error location is 2 m 1 i. Rewrite Λ( i ) as:λ( i ) = λ 0 +λ 1 i + λ 2 2i λ t ti = λ 0,i +λ 1,i + λ 2,i λ t,i t,i The computation complexity is reduced based on the fact that λ j,i+1 = λ j,i j 0 j t. The algorithm can also be paralleled to test multiple positions per clock cycle. A typical implementation of the algorithm with a parallelism level of q contains t m-bit multiplexers and registers, q t multipliers for multiplication by a constant and q adders in GF (2 m ). A strength-reduced parallel Chien search architecture is proposed. It can be showed that by a simple transformation of the error locator polynomial, most of the Galois field multiplications can be replaced by shift operations resulting in much lower hardware complexity (Figure 3.4). For the detail of the architecture, we implement the strength-reduced Chien search architecture with a parallelism level of ten, where 827 clock cycles are required to complete the error locating procedure. Figure.4: Chien Search Error Magnitude Computation for RS Codes Besides the error locator polynomial, the Berlekamp-Massey algorithm can also generate the error magnitude polynomial where is the syndrome polynomial. According to Forney s algorithm, the error magnitude at position can be computed Decoder Architecture for the Nonlinear Multi- Error Correcting Codes The decoder for the nonlinear multi-error correcting codes presented in Theorem 1 is similar to the decoders for BCH codes and RS codes. The main difference is as follows. First, the nonlinear multi-error correcting codes need to compute the nonlinear syndrome when receiving the possibly distorted code words and recomputed after correcting errors located. Second, after the decoding of the linear codes is completed and is recomputed, one more clock cycle is required for the decoder of the nonlinear code to verify the error correcting results. The decoder for the nonlinear multi-error correcting codes based on Theorem 2 is slightly more complicated than the decoder for codes based on Theorem 1. As an example, the detailed architecture of the decoder for the (8281, 8201, 11) nonlinear 5-bit error correcting code is shown in Figure 3.5. The whole decoding procedure requires 1675 clock cycles assuming a parallelism level of 10. During the first 827 cycles, and the syndrome of the BCH code are computed. If no errors are detected by the BCH code, the decoding procedure will be completed at the 828th clock cycle. Figure 5: Decoder Architecture for Nonlinear Error Correcting Codes. Depending on the value o f, either the first two information bits will be flipped or ERR will be pulled down by the ERR generating circuit which indicates that there are no errors occurring to the information bits of the code. The error locator polynomial generation and the Chien search will be incurred only when errors are detected by the BCH code, which can effectively reduce the average decoding latency. V. Area, Latency, and Power Consumption The area, latency, and the power consumption for architectures based on the six alternatives presented in Section V are shown in Table III. The designs are modeled in Verilog and synthesized in RTL Design Compiler using 45-nm NANDGATE library. In practice the logic circuits used in NAND flash memory could be different from those used in standard digital designs. The estimation presented here is only for the purpose of investigating the increase in area, ISSN: Page 53

5 power and latency of architectures based on the proposed nonlinear multi-error correcting codes compared to architectures based on the widely used BCH codes and R S codes. During the synthesis we fixed the clock rate for the encoder and the decoder and compared the area and the power consumption for architectures based on different codes. The encoders work at 1 GHz. The decoders work at a lower frequency 400MHz due to the long critical path in Berlekamp-Massey block [12]. The six alternatives require the similar latency in terms of the number of clock cycles for encoding and decoding. Due to the computation of the error magnitude and the pipeline for the inverter in the Galois field, digit-error VII. CONCLUSION correcting codes (RS, etc.) need eight more clock cycles to complete the decoding compared to bit-error In this paper, the constructions of two nonlinear correcting codes (BCH, etc.). The encoders for the multi-error correcting codes are proposed. Their error digit-error correcting codes require 40% 50% more area correcting algorithms are presented. The proposed overhead and power than the encoders for bit-error codes have much less undetectable and miscorrected correcting codes (see Figs. 6 and 7) due to the fact that errors than the conventional BCH codes and RS codes. all operations are in. The decoders for digit-error The designs of reliable MLC NAND flash memories correcting codes, however, require 20% 30% less based on the proposed nonlinear multi-error correcting overhead in area and power because of a much simpler codes are presented. We compare the area, the latency serial architecture. and the power consumption of the reliable MLC NAND Compared to BCH codes and RS codes, the flash architectures using the proposed nonlinear multierror correcting codes to architectures based on BCH proposed non-linear multi-error correcting codes need about 10% 20% more area and power in total for the codes and RS codes. The encoder and the decoder for encoder and the decoder and have the similar latency in all the alternatives are modeled in Verilog and terms of the number of clock cycles required to synthesized in RTL Design Compiler. The results show complete the encoding and decoding. that architectures based on nonlinear multi-error The(8281,8201,11) nonlinear 5-bit error correcting correcting codes can have close to zero undetectable codes based on Theorem 3, for example, requires and miscorrected errors while consuming less than 20% 17.5% more area and consumes 10.0% more power in more area and power consumption than architectures total for the encoder and the decoder compared to the based on the BCH codes and the RS codes. (8262,8192,11) BCH code. We note that the encoder and the decoder are only a very small portion in the VIII.ACKNOWLEDGMENT MLC NAND flash memory chip, where the major portion is the memory cell array. Thereby the increase We place our gratitude on record to the Department of in area overhead for the encoder and the decoder is not Electronics and Communication Engineering, Kuppam significant for the reliable memory design. Engineering College for the support rendered to us in carrying out this work. VI. Implementation and Results The proposed NAND Flash Memories Storage Reliablity Using Nonlinear Multi Error Correction Codes. The code is completely synthesized using Xilinx XST and implemented on device family Spatran 3E, device XC3S500E, package FG 320 with speed grade -4. IX. References. [1] G. Atwood, A. Fazio, D. Mills, and B. Reaves, Intel Strata memory technology overview, Intel Technol. J., vol. 1, 1997 [Online]. Avail-able: [2] J. Cooke, The inconvenient truths about NAND flash memory, pre-sented at the Micron MEMCON Presentation, Santa Clara, CA, [3] R. Dan and R. Singer, Implementing MLC NAND flash for costeffective,high capacity memory, M-Syst. White paper, 2003 [Online]. Available: ng_mlc_nand_flashwhite%20paper.pdf [4] R. Bez, E. Camerlenghi, A. Modelli, and A. Visconti, Introduction to flash memory, Proc. IEEE, vol. 91, no. 4, pp , Apr [5] G. Cellere, S. Gerardin, M. Bagatin, A. Paccagnella, A. Visconti, ISSN: Page 54

6 Bonanomi, S. Beltrami, R. Harboe-Sorensen, A. Virtanen, and [6] Roche, Can atmospheric neutrons induce soft errors in NAND floating gate memories?, IEEE Electron Device Lett., vol. 30, no. 2, pp , Feb [7] Impact of Voltage Scaled Repeaters on VLSI based CNT Interconects by Sandeep sani,karamjit singh sandha,ijett,vol- 4,ISSUE7,2013. [8] Proposed Multi Level cache Models Based on Inclusion & their Evaluation by Megha Soni,Rajendra Nath. IJETT,VOL- 4,ISSUE7,2013. [9] Modular delay Commutator for DHT Algorithm by Thamma Sai Sireesha,G.Malyadri, IJETT,VOL-18,ISSUE-12,2014. [10] A 6X6 Multiplier Based on MCM Method by Kolla Sruthi,K.Raju. IJETT,VOL-18,ISSUE-12,2014. About Authors: Author 1: R. NARESH NAIK, received his Bachelor of Technology in Electronics and Communication Engineering in N.B.K.R. Institute of Science&Technology,Vakadu, A.P., INDIA in He is doing his research on Advanced DSP architectures. His areas of interests are doing VERILOG based projects. Author 2: P.SIVA NAGENDRA REDDY, ASSISTANT PROFESSOR, DEPARTMENT OF ECE, KUPPAM ENGINEERING COLLEGE, KUPPAM, CHITTOOR. Author 3: E.RAMAKRISHNA NAIK, ASSISTANT PROFESSOR, DEPARTMENT OF ECE, S.K.D ENGINEERING COLLEGE, GOOTY, ANANTHAPURAMU. ISSN: Page 55