NAND Flash & Storage Media

Transcription

1 ENABLING MULTIMEDIA NAND Flash & Storage Media March 31, 2004 NAND Flash Presentation NAND Flash Presentation Version 1.6

2 NAND Flash Memories Technology Roadmap F70 1b/c F12 1b/c 1 bit/cell 0.12µm Eff. Cell = 0.07 µm² F90 1b/c 1 bit/cell 0.09µm Eff.Cell = µm² F90 2b/c 2 bit/cell 0.09µm Eff.Cell = µm² 1 bit/cell 0.070µ 070µm Eff.Cell = µm² F70 2b/c 2 bit/cell 0.070µ 070µm Eff.Cell = µm² March 31, 2004 page 2

3 NAND Flash Memories Packages Roadmap PB-Free Versions Supported TSOP48 WSOP48 12x20x1.2 mm 12x17x0.65 mm BGA63 BGA55 BGA55 8x10x1.0 mm BGA63 8.5x15x1.0 mm BGA63 9.5x12x1.0 mm 0.8mm pitch 0.45mm ball MCP / SIP Jedec BGA Multiple Stacked Side by Side MCP = Multi Chip Package; SIP = System In Package; March 31, 2004 page 3

4 NAND Flash Memories Product Roadmap SIP Solutions Removable Storage Media Embedded Storage Media NAND MCP with DRAM NAND General Purpose MCP = Multi Chip Package; SIP = System In Package March 31, 2004 page 4

5 ENABLING MULTIMEDIA NAND Flash & Storage Media NAND General Purpose Devices March 31, 2004 Version 1.6

6 Write Speed NAND Flash Memories Density & Performances Roadmap SLC - Large Page x4 512 Mbit 1 Gbit 2 Gbit 4 Gbit 8 Gbit MLC - Large Page x2 2 Gbit 4 Gbit 8 Gbit 16 Gbit SLC - Small Page x1 128 Mbit 256 Mbit 512 Mbit 1 Gbit Density March 31, 2004 page 6

7 NAND Flash Memories SLC Small Page Product Roadmap 528Bytes / 264Words Page Size Family Data Throughput (Max) Cache Read: 23 MB/s Cache Program: 2.5 MB/s Erase: 8 MB/s 128Mbit 3V TSOP/WSOP VFBGA 128Mbit 1.8V TSOP/WSOP VFBGA Contact Marketing for detailed Availability Schedule 256Mbit 3V TSOP/WSOP VFBGA 256Mbit 1.8V TSOP/WSOP VFBGA 512Mbit 3V TSOP/WSOP VFBGA 512Mbit 1.8V TSOP/WSOP VFBGA WSOP: Samples June 04 1Gbit 3V TSOP/TFBGA Dual 1Gbit 1.8V TSOP/TFBGA Samples NOW Apr/04 May/04 SOP NOW Jun/04 Jul/04 March 31, 2004 page 7

8 512Mbit 3V TSOP/WSOP VFBGA 512Mbit 1.8V TSOP/WSOP VFBGA NAND Flash Memories SLC Large Page Product Roadmap 2112Bytes / 1056Words Page Size Family Data Throughput (Max) Cache Read: 38 MB/s Cache Program: 7 MB/s Erase: 64 MB/s 1Gbit 3V TSOP/WSOP VFBGA 1Gbit 1.8V TSOP/WSOP VFBGA Contact Marketing for detailed Availability Schedule 2Gbit 3V TSOP/VFBGA Dual 2Gbit 1.8V TSOP/VFBGA 2Gbit 3V TSOP/WSOP VFBGA 2Gbit 1.8V TSOP/WSOP VFBGA WSOP: Samples July 04 4Gbit 3V TSOP/VFBGA Dual 4Gbit 1.8V TSOP/VFBGA Samples SOP Jun/04 Q3/04 Jul/04 Q3/04 Oct/04 Q4/04 Nov/04 Q1/05 March 31, 2004 page 8 8Gbit 3V TSOP/LFBGA Quad 8Gbit 1.8V TSOP/LFBGA

9 NAND Flash Memories MLC Large Page Product Roadmap 2112Bytes / 1056Words Page Size Family Multi Level Cell 2B/C Target Products 2Gbit 3V I/Os 1.8V/3V TSOP/WSOP VFBGA 4Gbit 3V I/Os 1.8V/3V TSOP/WSOP VFBGA 8Gbit 3V I/Os 1.8V/3V TSOP/VFBGA Dual 16Gbit 3V I/Os 1.8V/3V TSOP/LFBGA Quad Contact Marketing for detailed Availability Schedule Samples SOP Dec/04 Q1/05 Q1/05 Q2/05 March 31, 2004 page 9

10 Address Register & Counter Command Interface Logic Command Register PGM/Erase Controller & HV Generator NAND Flash Memories SLC Small Page Size Family X Decoder NAND Flash Memory Array Bytes Words Page Size Page Buffer Cache Register Y Decoder I/O Port Buffers & Latches Data Throughput (Max) 23 MB/s Read 2.5 MB/s Cache Program 8 MB/s Erase High Density: 128Mbit, 256Mbit, 512Mbit, 1Gbit Page Size: 528 Bytes (X8) or 264 Words (X16) Operating Voltages: V or V Configurations: X8 or X16 Multiplexed I/O Port for Command / Address / Data Pin-to-pin compatibility among All Densities Packages: TSOP48, WSOP48, VFBGA55/63, TFBGA55/63 Memory Organization Spare Area Page Size Block Size Pages # Blocks # Maximum throughput referred to NAND Family X16 w/o Host Overhead 128Mbit 256Mbit 512Mbit 1Gbit (16MB) (32MB) (64MB) (128MB) 4Mbit 8Mbit 16Mbit 32Mbit Bytes (X8) Words (X16) 16K Bytes (X8) 8K Words (X16) 32 Pages Copy Back Program Mode Cache Program Mode Chip Enable Don t Care Option Boot from Nand Power-on Auto Read Automatic Memory Download at Power-up Security Identifier and Serial Number OTP Area Hardware Data Protection Pin March 31, 2004 page 10

11 Address Register & Counter Command Interface Logic Command Register PGM/Erase Controller & HV Generator NAND Flash Memories SLC Large Page Size Family X Decoder NAND Flash Memory Array 2K+64 Bytes 1K+32 Words Page Size Page Buffer Cache Register Y Decoder I/O Port Buffers & Latches Data Throughput (Max) 38 MB/s Cache Read 7 MB/s Cache Program 64 MB/s Erase Maximum throughput referred to NAND Family X16 w/o Host Overhead High Density: 512Mbit, 1Gbit, 2Gbit, 4Gbit, 8Gbit Page Size: 2112Bytes (X8) or 1056Words (X16) Operating Voltages: V or V Configurations: X8 or X16 Multiplexed I/O Port for Command / Address / Data Pin-to-pin compatibility among All Densities Packages: TSOP48, WSOP48, VFBGA63, LFBGA63 Memory Organization Spare Area Page Size Block Size Pages # Blocks # 512Mbit 1Gbit 2Gbit 4Gbit 8Gbit (64MB) (128MB) (256MB) (512MB) (1GB) 16Mbit 32Mbit 64Mbit 128Mbit 256Mbit 2K + 64 Bytes (X8) 1K + 32 Words (X16) 128K + 4K Bytes (X8) 64K + 2K Words (X16) 64 Pages Copy Back Program Mode Cache Program ad Read Mode Chip Enable Don t Care Option Boot from Nand Power-on Auto Read Automatic Memory Download at Power-up Security Identifier and Serial Number OTP Area Lock/Unlock and Hw Data Protection Pin March 31, 2004 page 11

12 Random Access Serial Access Read TP NAND Flash Memories Product Features 128Mb 256Mb 512Mb D 512Mb 1Gb D 512Mb 1Gb 2Gb D 2Gb 4Gb D 8Gb Q (16MB) (32MB) (64MB) (64MB) (128MB) (64MB) (128MB) (256MB) (256MB) (512MB) (1GB) Technology 120nm SLC 90nm SLC Voltages 1.8V ( V) or 3V ( V) Configuration X8 or X16 Page Size Bytes (X8) Words (X16) 2K + 64 Bytes (X8) 1K + 32 Words (X16) Block Size 16K Bytes (X8) 8K Words (X16) 128K + 4K Bytes (X8) 64K + 2K Words (X16) Array 32 x x x x x x x x x x x us (3V) 15us (1.8V) 50ns (3V) 100ns(1.8V) 14.5MB/s (X8, 3V) 12.7MB/s (X8, 1.8V) 22.8MB/s (X16, 3V) 20.4MB/s (X16, 1.8V) 25us (3V) 30us (1.8V) 50ns (3V) 60ns (1.8V) 16.2MB/s (X8, 3V) 13.9MB/s (X8, 1.8V) 27.1MB/s (X16, 3V) 23.9MB/s (X16, 1.8V) Read (Cache) TP NA 38.1MB/s (X16, 3V) 19.1MB/s (X8, 3V) Page Program Time 200us (3V, 1.8V) 300us (3V, 1.8V) Program TP 2.3MB/s (X8, 3V) 2.2MB/s (X8, 1.8V) 2.4MB/s (X16, 3V) 2.4MB/s (X16, 1.8V) 5.1MB/s (X8, 3V) 4.8MB/s (X8, 1.8V) 5.8MB/s (X16, 3V) 5.7MB/s (X16, 1.8V)) Program (Cache) TP 2.6MB/s (X8, X16, 1.8V, 3V) 6.8MB/s (X8, X16, 1.8V, 3V) Block Erase 2ms 2ms Chip Erase 2.0s 4.1s 4.1s 8.2s 16.4s 1.0s 2.0s 4.1s 4.1s 8.2s 16.4s Special Features TSOP48 12x20x1.2 WSOP48 12x17x0.65 BGA55/BGA63 D = Dual Die; Q = Quad Die 10us (3V) 10us (1.8V) 50ns (3V) 60ns (1.8V) Cache Program - CE Don t Care - AutoRead Page0 Auto Download - Secure ID - Serial NBR Yes Yes 8x10x1.0 No No 8x10x1.2 Yes 8.5x15x1.0 Cache Program/Read - CE Don t Care - AutoRead Page0 Auto Download - Secure ID - Serial NBR - Lock/Unlock Maximum throughput referred to NAND w/o Host Overhead March 31, 2004 page 12 Yes No 8.5x15x1.2 Yes Yes 9.5x12x1.0 Yes No 9.5x12x1.0 Yes Yes Yes No Yes

13 NAND Flash Memories NAND General Purpose Part Number Operating Voltage R = 1.8V W = 3.0V Configuration 3 = x8 4 = x16 Packaging NAND 512 R 3 A 3 A ZA 6 E Blank = Standard Packing T = Tape & Reel E = Lead free Standard Packing F = Lead free Tape & Reel Density Temperature 128 = 128 Mbit 256 = 256 Mbit 512 = 512 Mbit 01G = 1 Gbit 02G = 2 Gbit 04G = 4 Gbit 08G = 8 Gbit 16G = 16 Gbit Family Identifier A = 528 bytes page SLC B = 2112 bytes page SLC C = 2112 bytes page MLC Device Options 0 = no options 1 = Read Page0 at power up 2 = CE don t care 3 = CE don t care & Read Page0 Product Version A, B, C, 6 = -40 / +85 Package N = TSOP V = WSOP ZA = VFBGA/TFBGA March 31, 2004 page 13

14 ENABLING MULTIMEDIA NAND Flash & Storage Media NAND MCP with LPSDRAM March 31, 2004 Version 1.6

15 NAND Flash Memories MCP NAND with LPSDRAM Roadmap Standard Family NAND 256Mb-512Mb 512Mb-1Gb 1Gb SDR 128Mb-256Mb 256Mb NAND Flash 528B Page Size x8/x16 + SDR LPSDRAM x16 BGA 8.5x15 mm de-populated ball-out High Performance Family NAND 512Mb-1Gb 1Gb-2Gb DDR/SDR 256Mb-512Mb 512Mb NAND Flash 2112B Page Size x8/x16 + DDR/SDR LPSDRAM x16/x32 BGA 11.5x13 mm populated ball-out H H March 31, 2004 page 15

16 NAND Flash Memories Nand+Dram Standard Family SCALABILITY Pin-to-Pin Compatible Along all Densities 256Mbit x8/x16 128Mbit x16 SDR 3.0V WTFBGA90 8.5x15x Mbit x8/x16 x16 128Mbit x16 SDR 1.8V WTFBGA90 8.5x15x Mbit x8/x16 256Mbit x16 SDR 3.0V WTFBGA90 8.5x15x Mbit x8/x16 256Mbit x16 SDR 1.8V WTFBGA90 8.5x15x Mbit x8/x16 256Mbit x16 SDR 3.0V WTFBGA90 8.5x15x Mbit x8/x16 256Mbit x16 SDR 1.8V WTFBGA90 8.5x15x1.2 1Gbit x8/x16 256Mbit x16 SDR 3.0V WLFBGA90 8.5x15x1.4 1Gbit x8/x16 256Mbit x16 SDR 1.8V Samples Apr/04 May/04 May/04 WLFBGA90 8.5x15x1.4 SOP Jun/04 Jul/04 Aug/04 March 31, 2004 page 16

17 512Mb x8/x16 x B Page 256Mb x16/x32 DDR/SDR 1.8V BGA 11.5x13 NAND Flash Memories Nand+Dram High Performance Family SCALABILITY Pin-to-Pin Compatible Along all Densities 1Gb x8/x B Page 256Mb x16/x32 DDR/SDR 1.8V BGA 11.5x13 2Gb x8/x B Page 256Mb x16/x32 DDR/SDR 1.8V BGA 11.5x13 1Gb x8/x B Page 512Mb x16/x32 DDR/SDR 1.8V BGA 11.5x13 BGA 11.5x13 March 31, 2004 page 17 2Gb x8/x B Page 512Mb x16/x32 DDR/SDR 1.8V Target Products Samples SOP Q3/04 Q4/04 Q4/04 Q1/05

18 NAND Flash Memories MCP Nand+Dram Part Number Operating Voltage R = 1.8V W = 3.0V Configuration 3 = x8 4 = x16 Packaging NAND 512 R 3 M 1 A ZA 7 E Blank = Standard Packing T = Tape & Reel E = Lead free Standard Packing F = Lead free Tape & Reel Density 256 = 256 Mbit 512 = 512 Mbit 01G = 1 Gbit 02G = 2 Gbit Device Options Family Identifier M = MCP DRAM Standard N = MCP DRAM High Performance 0 = LPSDRAM 128Mbit x16 105Mhz(@1.8V) 133Mhz(@3V) 1 = LPSDRAM 256Mbit X16 105Mhz(@1.8V) 133Mhz(@3V) Product Version A, B, C, D Temperature 7 = -25 / +85 Package ZA = FBGA March 31, 2004 page 18

19 ENABLING MULTIMEDIA NAND Flash & Storage Media MMC MultiMediaCard March 31, 2004 Version 1.6

20 MMC MultiMediaCard Application Drivers MP3 Player Music Storage Digital Camcorder Video Storage PDA File Storage Digital Camera Image Storage Mobile Phone Imaging Video Music Game Internet March 31, 2004 page 20

21 MMC MultiMediaCard Forms & Power Supply Roadmap High Speed Reduced Size X8 Data Bus 18 x 24 x 1.4 mm Normal Size 32 x 24 x 1.4 mm 3 Volts 2003 March 31, 2004 Dual Voltage 1.8V/3V page 21

22 MMC MultiMediaCard Flash Cards Product Roadmap 16 MB RS-MMC 1.8V/3V 16 MB Normal Size 1.8V/3V 32 MB RS-MMC 1.8V/3V 32 MB Normal Size 1.8V/3V 64 MB RS-MMC 1.8V/3V 64 MB Normal Size 1.8V/3V 128 MB RS-MMC 1.8V/3V 128 MB Normal Size 1.8V/3V 256 MB Normal Size 1.8V/3V Samples 512 MB Normal Size 1.8V/3V SOP Jun 04 Q3/04 Q3/04 Q4/04 1 GB Normal Size 1.8V/3V March 31, 2004 page 22

23 MMC MultiMediaCard Part Numbering Scheme Memory Type F = Flash M = Multiple Times Programmable R = Read only Card Version A, B, C, D Options blank = no options MMC 064 A F A 1 S xxxxx Density 002 = 2 MB 004 = 4 MB 008 = 8 MB 016 = 16 MB 032 = 32 MB 064 = 64 MB 128 = 128 MB 256 = 256 MB 512 = 512 MB 01G = 1 GB Options of Standard A = MMC 3V B = RS-MMC 3V C = MMC 1.8V/3V D = RS-MMC 1.8V/3V E = HS-MMC 1.8V/3V F = RS-HS-MMC 1.8V/3V 1 = 0 / +70 Packaging Temperature S = Standard Packing March 31, 2004 page 23

24 NAND Flash Memories Conclusions Reduce System Costs Increase System Performances Bring Innovation in Applications Reduce Development Time NAND Enabling Multimedia March 31, 2004 page 24

25 ENABLING MULTIMEDIA NAND Flash & Storage Media NAND Development Tools March 31, 2004 Version 1.6

26 FS OS FTL ECC LLD HW NAND Flash Memories Firmware Supports MMC Protocol MMC ASIC 8051 MMC IF YAFFS File System OS Less Flash Translation Layers LLD-8051 Nand IF ECC Error Correction Code Algorithm ATA Protocol CF ASIC 8051 ATA IF EMBEDDED OS Operative System NFFS File System OS Less TL-xxx Translation Layers OS Less LLD-ST7 Nand IF USB Protocol USB MCU ST7 USB IF BFN-ARM7 Boot Engine LLD-ARM7 Bus ARM7 Romless GP MCU File System OS Native TL-xxx Translation Layers OS Native WLGC Wear Leveling & Garbage Collection BBM Bad Blocks Management ECC VHDL & VERILOG Error Correction Hardware Model BFN-ARM9 Boot Engine LLD-ARM9 Nand IF ARM9 SOC (Nomadik) BFN-ST20 Boot Engine LLD-ST20 Nand IF ST20 SOC (Imaging) OS PC USB Win/Mac/Linux OS USB Remote File System TL-USB Translation Layers PC USB BFN-SH4 Boot Engine LLD-SH4 Bus SH4/ST40 Romless GP MCU March 31, 2004 page 26

27 NAND Flash Memories Reference Software Drivers Roadmap Low Level Drivers LLD & BFN-ARM7 LLD & Boot From NAND ARM7 GP Firmware LLD & BFN-ARM9 LLD & Boot From NAND ARM9 SOC Firmware LLD & BFN-ST20 LLD & Boot From NAND ST20 SOC Firmware LLD & BFN-SH4 LLD & Boot From NAND SH4 / ST40 Firmware Error Correction & Data Management WL Wear Leveling GC Garbage Collection BBM Bad Blocks Management ECC Error Correction Code Software Algorithm ECC Vhdl-Verilog Error Correction Code Hardware Models Modules are made available as free of charge Open Source Reference Software Turn Key Solutions are available upon specific conditions File Systems & Translation Layers NFFS-eCos Reference Nand Flash ecos OS Native FS + FTL NFFS Reference Nand Flash OS Less File System NFTL Reference Nand Flash Translation Layers YAFFS Reference Nand Flash OS Less FS + FTL Turn Key Solutions Pocket USB 1.1 Turn Key Solution ST7USB Firmware Camera USB 1.1 Turn Key Solution STV0674 Firmware Availability NOW Q2/04 March 31, 2004 page 27

28 NAND Flash Memories Data Management Operating System File System (Native) Flash Abstraction Layer Garbage Collection FTL Interface Wear Leveling Hardware Adaptation Layer LLD ECC BBM Nand Flash device FTL Approach Operating System Flash File System Hardware Adaptation Layer Nand Flash device FFS Approach Flash File System Exports to OS a File System interface (read/write files). It operates (through HAL) directly on NAND. Flash Abstraction Layer interface Exports a HDD-like interface, transform the NAND in a rewritable storage media. Garbage Collection Is a service module used by the FTL Interface. It implements the Erase operation for obsolete data. Wear Leveling It monitors and spreads the number of write cycle on the whole NAND. Bad Block Management Resolves the Bad Blocks problem through a reallocation technique. Error Correction Code Implements the ECC calculation and the Correction of the possible errors. Low Level Driver Abstracts the hardware functionality of the NAND flash. March 31, 2004 page 28

29 NAND Flash Memories Certification Efforts Compliance with Operative Systems and Standards is part of the validation and testing activity March 31, 2004 page 29