Engineer-to-Engineer Note EE-56 Technicl notes on using Anlog Devices DSPs, processors nd development tools Visit our Web resources http://www.nlog.com/ee-notes nd http://www.nlog.com/processors or e-mil processor.support@nlog.com or processor.tools.support@nlog.com for technicl support. Tips nd Tricks on SHARC EPROM nd Host Boot Loder Contributed by Stefn Hcker nd Jeynthi Jegdeesn Rev 3 Mrch 6, 27 Introduction After creting SHARC processor ppliction code nd verifying it in simultion or emultion, finl tsk is to crete boot imge for n EPROM or host processor. Though this is esy using the VisulDSP++ tools, some users wnt to dd specific functionlity to the boot loder or crete their own boot loder. This document discusses the output of the elfloder tool nd the rrngement of the dt in the boot imge. It shows where to dd chnges to modify boot loders to dpt to different host processor widths or types. Herefter, we will representtively refer to the ADSP-21367, ADSP-21368, nd ADSP-21369 processors s ADSP- 21368 processors. Similrly, we will refer to the ADSP-21362, ADSP-21363, ADSP-21364, ADSP-21365, nd ADSP- 21366 s ADSP-21362 processors Tble 1 shows the DMA chnnels nd corresponding interrupt sources used by different SHARC processors for EPROM/PROM boot loding. Processor DMA IVT loction ADSP-2106x DMA chnnel 6 0x40 Boot Loding After reset, SHARC processors re configured, by defult, to lod 256 words of 48-bit width (instruction size) by DMA. DMA is configured, bsed on the boot mode selected during reset. ADSP-2106x, ADSP-2116x, ADSP-21367, ADSP-21368, ADSP-21369, nd ADSP-2137x processors support booting through EPROM/flsh connected to the externl port of the processor. ADSP-2126x, ADSP-21362, ADSP-21363, ADSP-21364, ADSP-21365, nd ADSP-21366 processors do not hve n externl port. The prllel port on these processors supports booting from EPROM/flsh. ADSP-21065L DMA chnnel 8 0x40 ADSP-2116x DMA chnnel 10 0x50 ADSP-2126x Prllel port DMA 0x50 ADSP-21362 Prllel port DMA 0x50 ADSP-21368 ADSP-2137x Externl port DMA chnnel 0 0x50 Tble 1. DMA chnnels for EPROM/flsh booting Differences between externl port nd prllel port include: In prllel port, the ddress bus nd dt bus re multiplexed. In externl port, the dt bus nd ddress bus re seprte. The prllel port (unlike externl ports) cnnot hve direct core ccess. Dt must be red through DMA controller. Copyright 1999-27, Anlog Devices, Inc. All rights reserved. Anlog Devices ssumes no responsibility for customer product design or the use or ppliction of customers products or for ny infringements of ptents or rights of others which my result from Anlog Devices ssistnce. All trdemrks nd logos re property of their respective holders. Informtion furnished by Anlog Devices pplictions nd development tools engineers is believed to be ccurte nd relible, however no responsibility is ssumed by Anlog Devices regrding technicl ccurcy nd topiclity of the content provided in Anlog Devices Engineer-to-Engineer Notes.
Tble 2, Tble 3, Tble 4, nd Tble 5 show DMA settings for EPROM booting. Numbers printed in itlics re not initilized but re ssumed by the DMA engine. Since user ppliction code is fr lrger thn 256 words, boot kernel ensures tht the complete user ppliction code nd dt is loded into the internl memory spces of the SHARC processor. Additionlly, externl memories nd dt ports re initilized by the kernel. ADSP-21060/1/2 ADSP-21065L DMAC Register DMAC6=0x2A1 DMAC0=0x2A 1 II6 IIEP0 0x2 0x80 IM6 IMEP0 0x1 0x1 C6 CEP0 0x1 0x1 EI6* EIEP0* 0x40 0x80 EM6 EMEP0 0x1 0x1 EC6 ECEP0 0x6 0x6 IVT Loction 0x240 0x8040 Tble 2. EPROM boot setting with BSO bit set for ADSP-2106x processors DMAC Register ADSP-21160 DMAC10= 0x4A1 ADSP-21161 DMAC10= 0x4A1 II10 IIEP0 0x4 0x4 IM10 IMEP0 0x1 0x1 C10 CEP0 0x1 0x1 EI10* EIEP0* 0x80 0x80 EM10 EMEP0 0x1 0x1 EC10 ECEP0 0x6 0x6 IVT Loction 0x450 0x450 * BMS spce Tble 3. EPROM boot setting with BSO bit set for ADSP-2116x processors PPCTL Register IIPP ADSP-2126x PPCTL=0x16F 0x0 (offset from norml word strt ddress 0x8) IMPP 0x1 0x1 ICPP 0x180 0x180 EIPP 0x0 0x0 EMPP 0x1 0x1 ECPP 0x6 0x6 ADSP-21362 PPCTL=0x412F IVT Loction 0x850 0x950 0x0 (offset from norml word strt ddress 0x9) Tble 4. PROM boot setting for ADSP-2126x nd ADSP-21362 processors DMAC Register ADSP-21368 AMICTL0=0x5C1 ADSP-2137x IIEP0 0x9 0x9 IMEP0 0x1 0x1 ICEP0 0x180 0x180 AMICTL0=0x5C1 EIEP0 0x40 0 0x40 0 EMEP0 0x1 0x1 CPEP0 0x180 0x180 IVT Loction 0x950 0x950 Tble 5. EPROM boot setting for ADSP-21368 nd ADSP-2137x processors Boot Loder Nmes 060_prom.sm nd 065l_prom.sm re the source files for ADSP-2106x PROM-bsed loders. 16x_prom.sm, 26x_prom.sm, 36x_prom.sm, 369_prom.sm, nd 37x_prom.sm re the source files tht correspond to the ADSP-2116x, ADSP-2126x, ADSP-21362, ADSP-21368, nd ADSP-2137x processors, respectively. Tips nd Tricks on SHARC EPROM nd Host Boot Loder (EE-56) Pge 2 of 15
060_host.sm nd 065l_host.sm re the source files for the ADSP-2106x host-bsed boot loder. 160_host.sm nd 161_host.sm re the source files tht correspond to the ADSP-2116x processors. Depending on the selected processor nd the boot loding type, the corresponding boot kernel is loded into seg_ldr t reset. The corresponding Linker Description File is nmed with the processor nme, such s x6x_ldr.ldf. These source files re locted in the <instll_pth>\21k\ldr subdirectory within the VisulDSP++ tools. Boot Kernel Structure Ech kernel begins by defining mcros for the vrious IOP registers used in the code nd is followed by tble contining the interrupt vectors (up to nd including the DMA interrupt ligned to the externl port buffer 0 (EP0I) or prllel port interrupt). Most of these highpriority interrupts re not necessry for the opertion of the boot loder nd re filled with NOP or RTI instructions. The only interrupts used by the kernel re the reset interrupt nd the externl port or prllel port interrupt. The EP0I lib_rsti interrupt is vilble t the offset 0x04-0x07 for ll processors. The EP0I interrupt lib_ep0i is vilble t offset 0x40-0x43 for ADSP-2106x nd ADSP-2116x processors. The prllel port interrupt lib_ppi is vilble t offset 0x50-0x53 for ADSP-2126x nd ADSP- 21362 processors. For ADSP-21368 nd ADSP- 2137x processors, the externl port interrupt lib_ep0i is vilble t offset 0x50-0x53. ADSP-2106x nd ADSP-2116x Boot Kernel Structure Beginning from the strt_loder lbel, the kernel code cn be divided into four min sections: Strt_loder Initilizes some required registers. For EPROM booting, determines the processor ID of the processor in multiprocessor environment. Lod_memory Strts to prse the informtion from the boot source nd copies it into the required memory loction or clers not pre plced memory segments. finl_init Swps out the boot kernel nd replces it with the user ppliction code. red_prom_word Sets up the new DMA trnsfer to collect new 48-bit word The PROM nd host boot kernels for ADSP- 2106x nd ADSP-2116x processors include the four sections listed bove. For ADSP-21161N nd ADSP-21065L processors, the initiliztion of the SDRAM should be enbled when the user ppliction uses SDRAM to store code nd dt. ADSP-2126x nd ADSP-21362 Boot Kernel Structure Host booting is not supported on ADSP-2126x nd ADSP-21362 processors. The boot kernel begins by initilizing the control registers required for downloding the boot imge into the internl memory. The boot kernel strts by doing the following initiliztions: Enbles the globl interrupts. Initilizes the prllel port control nd SYSCTL registers. Initilize the DAG registers. Enble prllel port interrupt. The boot kernel vilble for the PROM boot on these processors hs the following sections. Tips nd Tricks on SHARC EPROM nd Host Boot Loder (EE-56) Pge 3 of 15
READ_BOOT_INFO The section reds three norml words using prllel port DMA. It checks the tg nd jumps to respective section to initilize the boot dt. USER_INIT The user cn initilize prllel port control nd other registers in this section. READ_THREEx32 This section reds three norml words nd stores them in scrtch loctions 0x803/0x983, 0x804/0x984, nd 0x805/0x985. READ_ONEx32 This section reds one norml word nd stores it t loction 0x803/0x983. finl_init After the ppliction hs been downloded completely, the boot kernel replces itself with interrupt vectors in this section. ADSP-21368 nd ADSP-2137x Processors The boot loder does the following: Clls the user_init section, in which the user initiliztion code exists. Clers ll interrupt registers, initilizes externl port0 interrupt, nd enbles globl interrupts. Initilizes DAG registers nd sves initil settings of the SYSCTL register. The boot kernel is divided into the following sections: READ_BOOT_INFO This section: Reds three or one norml words using externl port DMA nd plces them in scrtch loction strting t 0x983. This dt is lter used to initilize the boot dt t the required ddress. USER_INIT You cn initilize externl port control nd other registers in this section. You cn dd code in this section. Ensure tht the size of the boot kernel does not exceed 256 instructions. finl_init After the ppliction is downloded completely, the boot kernel replces itself with interrupt vectors in this section READ_THREEx32 This section reds three norml words nd stores them in scrtch loctions 0x983, 0x984, nd 0x985 READ_ONEx32 This section reds one norml word nd stores it t loction 0x983 x50_ep0i_isr Externl port interrupt vector MULTI_PROC This section reds the processor ID from SYSTAT nd chnges the offset ddress to the ppliction code, bsed on the processor ID. This section is useful in multiprocessor system where multiple pplictions cn be downloded from single flsh memory cross ll the processors in the multiprocessor system. This section pplies only to ADSP-21368 processors. If externl SDRAM is connected, uncomment #define SDRAM in the user_init section. Filure to do so my not copy correct vlues during boot to SDRAM. Also, if the SDRAM used is different from the SDRAM on the EZ- KIT Lite bord, the initiliztion vlues must be chnged ccordingly in the user_init section. Checks the tg nd jumps to the respective section to initilize the boot dt. Tips nd Tricks on SHARC EPROM nd Host Boot Loder (EE-56) Pge 4 of 15
EPROM Boot Kernel Opertion The following sections describe EPROM boot kernel opertion for vrious SHARC processors. ADSP-2106x, ADSP-21065L, nd ADSP-2116x Processors After reset, the core processor is held in n IDLE mode until the first 256 words (ech 48 bits wide), hve been loded by DMA into internl memory. The Externl Port DMA interrupt for EP0I is ctivted upon the completion of the DMA trnsfer. The core processor strts execution of the just-loded boot kernel by brnching to the vector interrupt loction for EP0I. In lib_ep0i, the DMA control register setting is stored in R2 for lter restortion, nd the DMA chnnel is disbled temporrily by clering the DMA enble bit in the control register. Hving completed the IRQ service, the core processor strts up the loder progrm. Beginning from the strt of execution, some required registers re initilized. This is good plce to strt up externl memories like SDRAM on ADSP-21065L processors or to set wit sttes nd wit modes. If there is user_init section in the boot kernel, the SDRAM nd synchronous memory interfce (AMI) control initiliztions cn be done in the user_init section. /BMS is dectivted, nd norml externl memory selects re ctivted by clering the BSO bit in the SYSCON register. Three copies of SYSCON re used in the progrm: one tht contins the originl vlue of SYSCON, one tht contins SYSCON with the BSO bit set so tht n ADSP-2106x processor cn gin ccess to the boot EPROM, nd third with the BSO bit clered. When BSO=1, the EPROM pcking mode bits in the DMACx control register re ignored nd 8-to-48-bit pcking is forced. For ADSP-21065L processors, 32-bitwide system bus is ssumed. Note tht 8-to-48-bit pcking is vilble only on ADSP-2106x processors during DMA reds from /BMS spce with the BSO bit set. When one of the externl port DMA chnnels is being used in conjunction with the BSO bit, none of the other three chnnels my be used. When BSO=1, /BMS is not sserted by core processor ccess, only during DMA trnsfer. This llows your bootstrp progrm (run by the ADSP-2106x core) to perform other externl ccesses to nonboot memory. The IMASK register is set finlly to llow the EP0I interrupt nd the MODE1 register is set to enble interrupts nd nesting. Hving completed the setup, the DMA engine on ADSP-2106x processors is used to collect 48-bit words from the EPROM. As n externl boot EPROM llows strting complete multiprocessor cluster, the proper section in the EPROM must be determined by checking the processor ID in the SYSTAT register. The code beginning from the get_ddr lbel will prse seven-entry 48-bit tble stored in the EPROM (hex offset 0x6 = 6*0x1 = 256 instruction words) to find the strt ddress of the boot section for this processor. Every entry of the tble is formtted s ddress (32-bit) nd processor ID (16-bit). For exmple, the redbck 0x82062A01 for n ADSP-21065L processor trnsltes into n EPROM offset of 0x82062A nd processor ID of 0x01. Hving determined the offset, the DMAC6/DMAC0 control register is set to 0x2A1, DMAC6 is set to 0x4A1 (ADSP-2116x processors), nd DMA prmeters re set up to red dt word-by-word beginning from the strting ddress of the boot section corresponding to the processor ID in the boot EPROM. Ech 48-bit word is trnsferred into ddress 0x204 (ADSP-2106x processors), 0x84 (ADSP-21065L processors), or 0x404 (ADSP-2116x processors) for disptching. Becuse the imge in the EPROM contins Tips nd Tricks on SHARC EPROM nd Host Boot Loder (EE-56) Pge 5 of 15
progrm memory code sections nd dt memory sections with different sizes, premble is stored before ech boot block. The premble with the ttched boot block is formtted s shown in Tble 6. 0x DDDD 0xAAAA AAAA LLLL 0xBOOT BOOT BOOT : : 0xBOOT BOOT BOOT Tble 6. Boot section heder D (dt type tg) A (ddress), L (length) Boot dt Boot dt Ech initiliztion block is identified by 16-bit tg (Tble 7) plced before the block. Ech type of initiliztion hs unique tg number. Tg Number Initiliztion Type 0 0x0 FINAL_INIT 1 0x1 ZERO_DM16 2 0x2 ZERO_DM32 3 0x3 ZERO_DM40 4 0x4 INIT_DM16 5 0x5 INIT_DM32 6 0x6 INIT_DM40 7 0x7 ZERO_PM16 8 0x8 ZERO_PM32 9 0x9 ZERO_PM40 10 0xA ZERO_PM48 11 0xB INIT_PM16 12 0xC INIT_PM32 13 0xD INIT_PM40 14 0xE INIT_PM48 Tble 7. Section heder types The boot kernel initilizes internl nd externl memories by reding the dt from EPROM using routine clled Red_Prom_Word nd writing it to specific loction of memory 0x204 (ADSP-2106x processors), 0x84 (ADSP-21065L processors), or 0x404 (ADSP- 2116x processors). For zero-vlued formt dt block whose tg is 1, 2, 3, 7, 8, 9, or 10, n initiliztion of 16- or 32-bit memory is done in loop, which writes zero vlue to memory, reducing the required spce in the EPROM. Any initiliztion of 40- or 48-bit PM memory uses write with the PX register set to zero. For non-zero formt dt block whose tg is 4, 5, 6, 11, 12, 13, or 14, the kernel enters loop which reds one 48-bit word from EPROM nd writes the pproprite width vlue to memory. This loop is repeted once for ech word being initilized. When the boot loder hs completed prsing boot block, it continues with the next tg nd executes the pproprite initiliztion routine until the kernel reches the FINAL_INIT (0x0) boot tg. In the finl initiliztion stge, the kernel lods the first 256 words of the trget executble file nd overwrites itself. When the loder detects the tg, it reds the next 48-bit word. This word indictes the instruction to be locted t 0x204 (ADSP-2106x processors), 0x84 (ADSP- 21065L processors), or 0x404 (ADSP-2116x processors) when the loding is close to being completed. This instruction is sved into the 48- bit PX register so tht the boot loder cn now finish initilizing internl memory. The kernel requires n RTI instruction t ddress 0x204 (ADSP-2106x processors), 0x84 (ADSP- 21065L processors), or 0x404 (ADSP-2116x processors), which is temporrily plced, becuse n EP0 interrupt is generted when the initiliztion is completed. The R9 register is loded with 0xBDB, which contins the encoded instruction PM(0,I8)=PX. This writes the desired customer instruction over the RTI used by the boot kernel with I8 pointing to 0x204 (ADSP-2106x processors), 0x84 (ADSP-21065 processors), or 0x404 (ADSP- 2116x processors). Tips nd Tricks on SHARC EPROM nd Host Boot Loder (EE-56) Pge 6 of 15
Before the DMA sequence is initited, the core processor is trpped in pseudo loop by issuing: DO lib_rsti UNTIL EQ; FLUSH CACHE; R0=0x204; /* 0x84 on 65l 0x404 on ADSP-2116x*/ PCSTK=R0; <DMA init> /* some code here */ IDLE; nd mnully dding the return ddress 0x204, 0x84, or 0x404 onto the stck. The loop termintes on n equl condition. Becuse the code will be overwritten by the DMA sequence, it is necessry to invlidte the cche with FLUSH CACHE instruction. The lst 256 48-bit words re loded into memory over the boot loder while the core processor is idling. Upon completion, the RTI is executed t ddress 0x240, 0x8040, or 0x440, returning the core processor to ddress (0x204, 0x84, or 0x404) so tht the next instruction to be crried out is filled with following instruction line: R0=R0-R0,DM(I4,M5)=R9,PM(I12,M13)=R11 which is red from the EPROM. This instruction clers the loop condition (r0=r0-r0), puts PM(0,I8)=PX (held in R9) into 0x204, 0x84, or 0x404, nd sets SYSCON bck to the originl vlue. At loop termintion of the loop, the progrm sequencer is set bck to 0x204, 0x84, or 0x404. The PX write exchnges the previously plced RTI t 0x204, 0x84, or 0x404 with the user instruction nd then proceeds to progrm loction 0x204, 0x84, or 0x404, which should be the beginning of user ppliction code. For more informtion bout dt plcement in the EPROM, its imge is prsed nd is included in this document. ADSP-2126x nd ADSP-21362 Processors ADSP-2126x nd ADSP-21362 processors do not hve n externl port. They boot through prllel port. In the prllel port, the ddress nd dt lines re multiplexed. After reset, the instruction t 0x804 or 0x904 is executed until the core downlods the first 256 instructions. The instruction t 0x804 or 0x904 must be vlid instruction s this instruction is executed by the core while downloding the first 256 instructions. The first 256 instructions downloded must be the boot kernel. The boot kernel hs n RTI instruction t the prllel port interrupt vector. After completing the downlod of the boot kernel, the RTI instruction t the prllel port vector is executed nd the core strts executing the just-loded boot kernel from reset vector 0x805 or 0x905. To strt, the boot kernel clls the user_init section. You cn dd code relted to configuring your system. Usully user configures prllel port registers in this section, bsed on the system design. The boot kernel follows by performing the following initiliztions: Clers ll the interrupt registers nd enbles the globl interrupt bit IRPTEN in the MODE1 register. The boot kernel uses only the prllel port interrupt prt from the reset interrupt. Disbles the prllel port. The prllel port is enbled by the boot kernel whenever dt from the boot imge must be downloded. Initilizes the DAG registers for use. Sves the current vlue of the SYSCTL registers for restortion in finl_init. Enbles the prllel port interrupt. After doing the necessry initiliztions, the boot kernel follows by reding the tg, count, nd Tips nd Tricks on SHARC EPROM nd Host Boot Loder (EE-56) Pge 7 of 15
destintion ddress using the READ_THREEx32 function. The READ_THREEx32 function sets up the prllel port DMA to red the tg, count nd destintion ddress into loctions strting from 0x803 or 0x983. The boot kernel reds the tg t loction 0x803 or 0x983 to determine the dt type of the boot imge to be copied. Ech initiliztion block is identified by 16-bit tg (Tble 8) plced before the block. Ech type of initiliztion hs unique tg number. Tg Number Initiliztion Type 0 0x0 FINAL_INIT 1 0x1 2 0x2 3 0x3 4 0x4 5 0x5 6 0x6 INIT_L64 7 0x7 8 0x8 9 0x9 10 0xA Tble 8. Section heder types ZERO_LDATA (initilize 16/32/64 DM dt to zero) ZERO_L48 (initilize 48/40 bit dt in internl memory to zero) INIT_L16 (initilize internl shortword (16-bit) memory) INIT_L32 (initilize 32-bit internl memory) INIT_L48 (initilize instructions nd 40-bit dt) ZERO_EXT8 (use core to initilize externl buffers to zero) ZERO_EXT16 (use core to initilize externl buffers to zero) INIT_EXT8 (initilize externl memory) INIT_EXT16 (initilize externl memory) The boot kernel initilizes internl nd externl memories by reding the dt from EPROM using routine clled READ_THREEx32 nd writing it to specific loction of memory (0x803 or 0x983). For zero-vlued formt dt block whose tg is 1, 2, 3, 7, 8, 9, or 10, n initiliztion of 16- or 32-bit memory is done in loop, which writes zero vlue to memory, reducing the required spce in the EPROM. Any initiliztion of 40- or 48-bit PM memory uses write with the PX register set to zero. Becuse the imge in the EPROM contins progrm memory code sections nd dt memory sections with different sizes, premble is stored before ech boot block. The premble with the ttched boot block is formtted s shown in Tble 9. 0x DDDD 0xAAAA AAAA LLLL 0xBOOT BOOT BOOT : : 0xBOOT BOOT BOOT Tble 9. Boot section heder D (dt type tg) A (ddress), L (length) Boot dt Boot dt To downlod 48-bit dt, the boot kernel uses three reds of 32 bits to fetch two 48 bits of dt. The READ_THREEx32 subroutine is used to fetch nd store three 32 bit dt t loctions strting t 0x803 or 0x983. PX registers re used to hndle initiliztion of dt greter then 32 bits. To initilize dt types of size 32 bits nd less, the READ_ONEx32 subroutine is used to fetch nd store one 32-bit dt t loction 0x803 or 0x983. The vlues t these loctions re copied into the destintion memory ddress in the internl memory. To initilize externl memory, the boot kernel uses the PP_DMA_WRITE subroutine. If initiliztion of externl SRAM is required, the boot initilizes the prllel port control nd DMA registers to perform writes to externl SRAM. The boot kernel wits until the externl writes re completed by testing the busy bit (PPBS) in the prllel port control register. When the boot loder hs completed prsing boot block, it continues with the next tg nd executes the pproprite initiliztion routine until the kernel reches the FINAL_INIT (0x0) boot tg. Tips nd Tricks on SHARC EPROM nd Host Boot Loder (EE-56) Pge 8 of 15
ADSP-21368 nd ADSP-2137x Processors ADSP-21368 nd ADSP-2137x processors use the externl port to boot from EEPROM/flsh. After reset, the instruction t 0x904 is executed until the core downlods the first 256 instructions. The instruction t 0x904 must be vlid instruction s this instruction is executed by the core while downloding the first 256 instructions. The first 256 instructions downloded must be the boot kernel. The boot kernel hs n RTI instruction t the externl port0 interrupt vector. After completing the downlod of the boot kernel, the RTI instruction t the externl port vector is executed nd the core strts executing the just-loded boot kernel from the reset vector (0x905). To strt, the boot kernel clls the user_init section. You cn dd code relted to configuring your system. Usully user configures the externl port, SDRAM, synchronous memory interfce (AMI), nd SYSCON registers in this section, bsed on system design. The boot kernel follows by performing the following initiliztions: Clers ll the interrupt registers nd enbles the globl interrupt bit (IRPTEN) in the MODE1 register. The boot kernel uses only the externl port 0 interrupt prt from the reset interrupt. Disbles the externl port DMA. The externl port is enbled when by the boot kernel whenever dt from the boot imge must be downloded. Initilizes the DAG registers for use. Sves the current vlue of the SYSCTL registers for restortion in finl_init. Enbles the externl port 0 interrupt. After doing the necessry initiliztions, the boot kernel follows by reding the tg, count, nd destintion ddress using the READ_THREEx32 function. The READ_THREEx32 function sets up the externl port DMA to red the tg, count, nd destintion ddress into loctions, strting from 0x983. The boot kernel reds the tg t loction 0x983 to decide the dt type of the boot imge to be copied. Ech initiliztion block is identified by 16-bit tg (Tble 10) plced before the block. Ech type of initiliztion hs unique tg number. Tg Number Initiliztion Type 0 0x0 FINAL_INIT 1 0x1 2 0x2 3 0x3 4 0x4 5 0x5 6 0x6 INIT_L64 7 0x7 8 0x8 9 0x9 10 0xA 11 0xB Tble 10. Section heder types ZERO_LDATA (initilize 16/32/64 DM dt to zero) ZERO_L48 (initilize 48/40 bit dt in internl memory to zero) INIT_L16 (initilize internl shortword (16-bit) memory) INIT_L32 (initilize 32-bit internl memory) INIT_L48 (initilize instructions nd 40-bit dt) ZERO_EXT8 (use core to initilize externl buffers to zero) ZERO_EXT16 (use core to initilize externl buffers to zero) INIT_EXT8 (initilize externl memory) INIT_EXT16 (initilize externl memory) MULTI_PROC (check the SYSTAT register to identify the processor ID nd downlod the pproprite ppliction) Hving completed the setup, the DMA engine on the ADSP-21368 or ADSP-2137x processor is used to collect 48-bit words from the EPROM. Tips nd Tricks on SHARC EPROM nd Host Boot Loder (EE-56) Pge 9 of 15
As n externl boot EPROM llows strting complete multiprocessor cluster, the proper section in the EPROM must be determined by checking the processor ID in the SYSTAT register. The code beginning from MULTI_PROC lbel will prse seven-entry 48-bit tble stored in the EPROM (hex offset 0x6 = 6*0x1 = 256 instruction words) to find strt ddress of boot section for this processor. Every entry of the tble is formtted s ddress (32-bit) nd processor ID (16-bit). For exmple, the redbck 0x42062A01 for n ADSP-2137x processor trnsltes into n EPROM offset of 0x42062A nd processor ID of 0x01. The boot kernel initilizes internl nd externl memories by reding the dt from EPROM using routine clled READ_THREEx32 nd writing it to specific loction of memory (0x983). For zero-vlued formt dt block whose tg is 1, 2, 3, 7, 8, 9, or 10, n initiliztion of 16- or 32-bit memory is done in loop, which writes zero vlue to memory, reducing the required spce in the EPROM. Any initiliztion of 40- or 48-bit PM memory uses write with the PX register set to zero. Becuse the imge in the EPROM contins progrm memory code sections nd dt memory sections with different sizes, premble is stored before ech boot block. The premble with the ttched boot block is formtted s shown in Tble 11. 0x DDDD 0xAAAA AAAA LLLL 0xBOOT BOOT BOOT : : 0xBOOT BOOT BOOT Tble 11. Boot section heder D (dt type tg) A (ddress), L (length) Boot dt Boot dt To downlod 48-bit dt, the boot kernel uses three reds of 32 bits to fetch two 48 bits of dt. The READ_THREEx32 subroutine is used to fetch nd store three 32 bits of dt t loctions strting t 0x983. PX registers re used to hndle initiliztion of dt greter thn 32 bits. To initilize dt types of size 32 bits nd less, the READ_ONEx32 subroutine is used to fetch nd store one 32-bit dt t loction 0x983. The vlues t these loctions re copied into the destintion memory ddress in the internl memory. To initilize externl memory, the boot kernel uses the subroutine tht ws used to initilize the internl memory. When the boot loder hs completed prsing boot block, it continues with the next tg nd executes the pproprite initiliztion routine The ADSP-21368 or ADSP-2137x boot kernel supports multiprocessor shred memory booting. It is possible to boot multiple processors using common EEPROM/flsh memory. The boot kernel identifies the processor ID by reding the SYSTAT register. Bsed on the processor ID, the boot kernel dds n offset nd modifies the externl ddress ppropritely to boot. VisulDSP++ provides n option to generte single loder file using multiple executbles. Refer to Mnging Multiple Applictions in Single EPROM for SHARC Processors (EE- 108) [9] for more detils. Host Boot Kernel Opertion The following sections describe host boot kernel opertion for vrious SHARC processors. ADSP-2106x nd ADSP-21065L Processors In mny wys, the host boot kernel works like the EPROM boot kernel. This section focuses on the differences between them. Unlike PROM booting, which uses mster DMA, host booting uses slve DMA. Tips nd Tricks on SHARC EPROM nd Host Boot Loder (EE-56) Pge 10 of 15
ADSP-21060/1/2 ADSP-21065L Host Timing Synchr./Asynchr. Asynchr. SYSCON 0x10 0x20 DMAC Register DMAC6=0xA1 DMAC0=0xA1 II6 IIEP0 0x2 0x80 IM6 IMEP0 0x1 0x1 C6 CEP0 0x1 0x1 IRQ Vector 0x240 0x8040 Tble 12. Host boot setting At first, it is importnt to verify tht the pcking HPM bits in SYSCON nd DMAC6 support the 16-48 pcking mode (HBW bits nd DMAC0 8-48 pcking for ADSP-21065L processors) s this is the defult mode. If this not selected, the first write of the host processor must chnge the settings of SYSCON; otherwise, the generic boot loder will not work. As soon s this first dpttion hs been mde or is verified, the host strts writing the first 256 instruction words s pcked dt to the externl port buffer 0 of the I/O processor t offset loction 0x4. This my be done in one host bus request cycle, where the /HBR pin (synchronous) or /HBR nd /CS pins (synchronous) of the selected processor must be driven low. The host interfce of the slve responds with /HBG nd ACK pins (synchronous) or /HBG nd REDY pins (synchronous) to recombine the dt words to instructions nd plces them beginning in 0x2 or 0x80 in internl memory. Hving written the first 256 instruction words, the slve s DMA internl Cx register elpses nd the processor wkes up nd strts executing the boot kernel beginning from lib_ep0i, (DMA interrupt vector), immeditely turning off the DMA chnnel by setting DEN=0 nd locking the externl bus with BUSLK bit in MODE2. If dt/code is to be plced externlly, the host processor must give up bus mstership or dedlock will occur. ADSP-2106x processors cnnot drive externl signls nd cnnot prse new dt presented by the host processor. Beginning from this point, timing of the host processor is essentil. ADSP-2106x processors now expect single-instruction word size slve DMA sequences in which the user is presenting three 16-bit-wide (six 8-bit-wide for ADSP- 21065L processors) dt chunks on EPB0 (0x04). These words form 48-bit-wide instruction word which is plced into 0x204 or 0x84 nd is then prsed. So the user just continues writing dt to EPB0. A chnge in the IOP destintion ddress is not necessry. If the host continues writing dt to buffer 0, the EPB0 FIFO nd slve write FIFO will fill up nd REDY (synchronous) will be de-sserted. This is the hndshke signl to the host processor to extend further ccesses. The structure of the boot imge is quite similr to the EPROM boot structure; the only difference is the missing multiprocessor boot tble fter the boot kernel. A host my boot multiprocessor system by selecting multiple /CS pins synchronously or directly in multiprocessor memory spce (MMS) synchronously. If lrge rrys must be initilized in externl memory, lot of time my be required until ADSP-2106x processor return bus control bck to the host processor. If such witing periods result in time-out on the host, you cn specify the time-out switch of the elfloder tool to brek these initiliztions into smller pieces, llowing the host processor to obtin bus control erlier. Hving downloded the initiliztion dt, the lst 256 instruction words my be written gin in single ccess to EPB0, s this only replces code which is plced internlly. The host boot loder swpping mechnism is identicl to the EPROM boot loding sequence. Tips nd Tricks on SHARC EPROM nd Host Boot Loder (EE-56) Pge 11 of 15
ADSP-2116x Processors Tble 13 shows host boot setting for ADSP- 2116x processors. Host Timing ADSP-21160 Synchr./Asynchr. SYSCON 0x10 0x20 ADSP-21161 Synchr./Asynchr. DMAC Register DMAC10=0x81 DMAC0=0x161 II10 IIEP0 0x4 0x4 IM10 IMEP0 0x1 0x1 C10 CEP0 0x1 0x1 IRQ Vector 0x450 0x450 Tble 13. Host boot setting At first, it is importnt to verify tht the pcking HPM bits in SYSCON nd DMAC10 support the 16-48 pcking mode (HBW bits nd DMAC0 8-48 pcking for ADSP-21161 processors) s this is the defult mode. If this not selected, the first write of the host processor must chnge the settings of SYSCON; otherwise, the generic boot loder will not work. ADSP-2116x processors host interfce differs from ADSP-2106x processors in tht this interfce cn tke dvntge of the 64-bit dt bus width. Though ADSP-2116x processors support the ADSP-2106x processor s synchronous host interfce protocols, ADSP- 2116x processors lso provide new synchronous interfce protocols for mximum throughput. The host/locl bus dedlock resolution function on ADSP-2116x processors is extended to the DMA controller. The function llows the host (or bridge) logic to force the locl bus to bck off nd llow the host to complete its opertion first. As soon s this first dpttion hs been mde or is verified, the host strts writing the first 256 instruction words s pcked dt to the externl port buffer 0 of the I/O processor t offset loction 0x4. This my be done in one host bus request cycle, where the /HBR pin (synchronous) or /HBR nd /CS pins (synchronous) of the selected processor must be driven low. The host interfce of the slve responds with /HBG nd ACK pins (synchronous) or /HBG nd REDY pins (synchronous) to recombine the dt words to instructions nd plces them beginning in 0x4 in internl memory. Hving written the first 256 instruction words, the slve s DMA internl Cx register elpses nd the processor wkes up nd strts executing the boot kernel beginning from lib_ep0i, (DMA interrupt vector), immeditely turning off the DMA chnnel by setting DEN=0 nd locking the externl bus with the BUSLK bit in MODE2. If dt or code is to be plced externlly, the host processor must give up bus mstership or dedlock will occur. ADSP-2116x processors cnnot drive externl signls nd cnnot prse new dt presented by the host processor. Beginning from this point, timing of the host processor is essentil. ADSP-2116x processors now expects single-instruction word size slve DMA sequences in which the user is presenting three 16-bit-wide (six 8-bit-wide for ADSP- 21161 processors) dt chunks on EPB0 (0x04). These words form 48-bit-wide instruction word which is plced into 0x404 nd is then prsed. So the user just continues writing dt to EPB0. A chnge in the IOP destintion ddress is not necessry. If the host continues writing dt to buffer 0, the EPB0 FIFO nd slve write FIFO will fill up nd REDY (synchronous) will be de-sserted. This is the hndshke signl to the host processor to extend further ccesses. The structure of the boot imge is quite similr to the EPROM boot structure; the only difference is the missing multiprocessor boot tble fter the boot kernel. A host my boot multiprocessor system by selecting multiple /CS pins synchronously or directly in multiprocessor memory spce (MMS) synchronously. Tips nd Tricks on SHARC EPROM nd Host Boot Loder (EE-56) Pge 12 of 15
If lrge rrys must be initilized in externl memory, lot of time my be required until ADSP-2116x processors return bus control bck to the host processor. If such witing periods result in time-out on the host, you cn specify the time-out switch of the elfloder tool to brek these initiliztions into smller pieces, llowing the host processor to obtin bus control erlier. Hving downloded the initiliztion dt, the lst 256 instruction words my be written gin in single ccess to EPB0, s this only replces code which is plced internlly. The host boot loder swpping mechnism is identicl to the EPROM boot loding sequence. Boot Kernel Cvets The kernel ssumes tht IMDW is 0 during the booting process before it is set to 1 in the finl boot stge of the kernel. Also remember tht when using ny of the power-up booting modes, loction 0x204 or 0x84 must not contin vlid instruction since it is not executble during the booting sequence. Plce NOP or IDLE instruction t this loction. If the kernel is going to initilize externl memory, ensure tht the pproprite vlues re set in SYSCON nd WAIT register nd tht they re correct; otherwise, the processor my hng. Note tht the SDRAM on ADSP-21065L, ADSP- 21161N, ADSP-21368, nd ADSP-2137x processors requires power-up routine before it is ccessible. This is reched by plcing the init code into the loder kernel. Be wre tht the vlue in DMACx is nonzero nd tht IMASK is set to llow DMACx interrupts. Becuse the EP0I interrupt remins enbled in IMASK, it must be clered before this DMA chnnel my be used gin; otherwise, unintended interrupts my occur. Additionlly, reset DMACx to 0x0 before reinitilizing or new DMA sequence my not strt. User Chnges to Boot Loder Sources For ADSP-2106x nd ADSP-2116x processors, the EPROM boot loder does not llow too mny chnges, s during the first 256 words instruction lod pcking mode of 8-to-48 is forced with the BSO bit. So, if user uses 16-bit-wide EPROM, the first 256 instructions must be spred cross the first 0x6 ddresses of the EPROM, showing only the lowest eight-bits populted. For these processors, chnging the DMA chnnel to higher number nd its initiliztion sequence llows the use of different pckging modes. The BSO bit is required; otherwise, no /BMS memory strobe is generted. With these modifictions, the user could boot from 16-bit-wide EPROM insted of n 8-bit-wide EPROM. The host boot loder offers more options: the pcking mode in SYSCON nd DMACx cn be chnged so tht different bus widths (16 or 32 bits) re possible. You must ensure proper ordering of the dt words to be written over EPB0, or the initiliztion of the processor will fil. Tips nd Tricks on SHARC EPROM nd Host Boot Loder (EE-56) Pge 13 of 15
Appendix EPROM Boot Imge Exmple EPROM boot imge decoded nd prtitioned, outlining importnt prts, broken into 48-bit words: :02 04 boot record strt FA :20 80 4480 +- strt of boot kernel 9C :2020 :2040 :25E0 043E06 3E0B 3E0B 3E0B 3E0B end of boot kernel -+ 78 7C FB :26 2A0680 01 02 03 04 05 +- 862A = offset of 0x862A in EPROM for processor ID=0 1B :0A0620 06 CA :262A 0E 0E81 790F 870A14!! +- strt of progrm code! +- strt ddress 0x81, length 0x0E = 14 dez +- section tg INIT_PM48 E6 :264A :266A :268A 382C14 4C14 1BB7DF0F 1BB7DE0F 2A14 10 0B14 1D14 80 0A813E06 604C14 3E0B 3E0B!! +- strt of user RTH! +- instruction to be plced t 0x8040 +- section tg FINAL_INIT EB C8 07 :26AA 20802D7339 813E06 3E0B 3E0B! +- jump 0x81 +- R0=R0-R0, DM(I4,M5)=R9, PM(I12,M13)=R11 60 :26CA :26EA :2C6A :0C0C8A 3E0B 3E0B 3E0B 3E0B 0C813E06 3E0B 3E0B +- end of user code 7E FB 6A 5E : 01 End of EPROM imge FF Tble 4. Boot imge for ADSP-21065L processors Tips nd Tricks on SHARC EPROM nd Host Boot Loder (EE-56) Pge 14 of 15
References [1] ADSP-2106x SHARC Processor User s Mnul. Rev 2.1, Mrch 24. Anlog Devices, Inc. [2] ADSP-21065L SHARC Processor User s Mnul. Rev 2.0, July 23. Anlog Devices, Inc. [3] ADSP-21160 SHARC Processor Hrdwre Reference. Rev 3.0, November 23. Anlog Devices, Inc. [4] ADSP-21161 SHARC Processor Hrdwre Reference. Rev 4.0, Februry 25. Anlog Devices, Inc. [5] ADSP-2126x SHARC Processor Peripherls Mnul. Rev 3.0, December 25. Anlog Devices, Inc. [6] ADSP-2136x SHARC Processor Hrdwre Reference for the ADSP-21362/3/4/5/6 Processors. Rev 1.0, October 25. Anlog Devices, Inc. [7] ADSP-21368 SHARC Processor Hrdwre Reference. Rev 1.0, September 26. Anlog Devices, Inc. [8] VisulDSP++ 4.5 Loder nd Utilities Mnul. Rev. 2.0, April 26. Anlog Devices, Inc. [9] Mnging Multiple Applictions in Single EPROM for SHARC Processors (EE-108). Rev 2, Mrch 27, Anlog Devices Inc. Document History Revision Rev 3 Mrch 6, 27 by P Mllikrjun Reddy nd Jeynthi Jegdeesn Rev 2 Mrch 24, 24 by Robert Hoffmnn Rev 1 July 20, 1999 by Stefn Hcker Description Updted the document for ADSP-2116x, ADSP-2126x, ADSP-2136x, nd ADSP- 2137x processors. Chnged title from Tips & Tricks on the ADSP-2106x SHARC EPROM nd Host Bootloder. Updted PROM nd host booting section, include boot tble for host booting. Initil relese. Tips nd Tricks on SHARC EPROM nd Host Boot Loder (EE-56) Pge 15 of 15