Febex Data Acquisition System (FPGA Hit Finder and Energy Filter for the FEBEX Pipelining ADC) Dr. Ivan Rusanov for CSEE, GSI - Darmstadt CSEE meeting, GSI 24.02.2014., Darmstadt The Febex Data AcquisitionSystem is developed in CS Experiment-Electronics Department of GSI. The main component of the system is a Febex board, which has 16 differential analog inputs, 16 differential LVDS I/Os (max. 8 outputs) and four serial multi-gigabit connections to backplane (2 Gbits per s.). The interface, implemented in the Febex broad, is designed to work with Multi Branch System (MBS) data acquisition system. Through the MBS system, via the optical interface, the user has full control over all components of Febex board: configuration, testing, start/stop of data acquisition, data readout and data logging. The MBS runs under the operating systems Linux and LynxOS and supports various hardware setups. Therefore, for each user defined hardware setup, the MBS data acquisition software requires user input data, describing the hardware setup and configuration parameters. Development: Dr. Ivan Rusanov CSEE; Jan Hoffmann - CSEE ; Dr. Nikolaus Kurz CSEE; Dr. Shizu Minami - CSEE ; Dr. Wolfgang Ott CSEE.
Febex Data Acquisition System: Features 1. Triggering: Yes. Acquisition (physics / Trigger Type 1) and Synchronization (Trigger Type 3) Triggers. 2. Self Triggering : Yes. For each channel are implemented two methods: # Programmable Fast Trapezoidal Filter for a leading edge selection with 12-bit threshold. # 3-Steps comparator for a leading edge selection. 3. Double Hit Detection: Yes. 4. Energy measurement: Yes. For each channel is implemented a Programmable Energy Trapezoidal Filter for a measurement of hits energy. 5. Trigger window (Traces Length): Programmable (up to 8000 ADC s samples/traces). Pre-Trigger Window: Programmable (up to 2000 ADC s samples/traces). Post-Trigger Window: [Trigger_Window] [Pre-Trigger_Window]. 6. Slow Control and Data Acquisition : via Optical Link. Access to Configuration Registers: Read/Write address mode (single access via Optical Link). # Configuration of Febex s DAC: via Optical Link and I2C bus. # Configuration of ADCs: via Optical Link and SPI bus I. # Configuration of FPGA s flash: via Optical Link and SPI bus II. Data Readout / Data Buffering: Block Transfer mode (via Optical Link) / Double Readout Buffer (one per channel + one for energy measurements). Data Readout is programmable: from each Febex board can be sent out: # summary data packet (Chanel Id, Number of hits, Hit s time and Energy data /2 words per channel //one per Febex) and ADCs traces with or without data from Energy Trapezoidal Filter, in case more than one hit is found in a single channel. # summary data packet and traces (up to 8000 ADC s samples/traces // one traces packet per channel). # summary data packet, traces and data from Energy Trapezoidal Filter (up to 2000 ADC s samples/traces). # only traces (up to 8000 ADC s samples/traces). # only traces and data from Energy Trapezoidal Filter (up to 2000 ADC s samples/traces). Readout Data Reduction: Yes and Programmable. The channels data is sent out only if hit is found (for summary and traces data packets). 7. Up to 1216 channels in 4 crates: 16 channels per Febex board // up to 19 Febex boards + one Interface card in one carte. 8. In the system can be used Febex boards with 12-bit/60 MHz (12-bit/50 MHz) or 14-bit/50 MHz ADCs (can be used mixed in one or different crates). 9. Each Febex Board can be programmed to operate with negative or positive input signals (can be used mixed in one crate or different crates).
Febex Data Acquisition System (one example for 1216 channels) PC Master Slave 1 TRIXOR ECL_OUT TRIXOR_Busy Trigger Module ANY_IN LVDS_OUT Trigg&Clock Bus 3 Trigger Module ANY_IN LVDS_OUT ECL_IN Coded Trigger ECL_OUT ECL_OUT Trigger 3 (external) LEMO_IN 3 LEMO_IN 3 LEMO_IN 1 LEMO_IN 1 Trigger 1 (external) Self Trigger (internal) LEMO_OUT 6 LEMO_IN 6 Self Trigger 1/2 LEMO_OUT 6 LEMO_IN 6 TRIGGER 1 TRIGGER 2 TRIGGER 1 TRIGGER 2 PEXOR 4 SFPs 4 SFPs / Slow Control and DATA Readout Trigg&Clock Bus 1 FEBEX Crate 1 Trigg&Clock Bus 2 FEBEX Crate 2 Trigg&Clock Bus 1 In one Febex Crate: Max 19 Febex Boards. 16 Diff. Inputs per Febex Board. FEBEX Crate 3 Trigg&Clock Bus 2 FEBEX Crate 4 Detector: Differential Analog Signals (up to 304 Channels per Crate)
Algorithms for Energy or Fast TF, implemented in FPGA history 2N+M N+M+1 N B_Window Gap (not used) ( N ADC samples ) ( M ADC samples ) current 1 A_Window ( N ADC samples ) ADC samples TF i=1 = N Σ i = 1 A i - 2N+M Σ B i i = N+M+1 Input Length of TF = A_Window + Gap + B_Window Delay Delay Delay A 1 A N+1 B N+M+1 B 2N+M+1 + - + - Σ Σ + + + + Σ Σ + - Σ Output TF 1 Filter's equation Implementation in FPGA (Delays = Block RAMs)
The testing in the Lab of the Febex Data Acquisition System (Energy TF) with Go4 FPGA: ADC Samples / Traces and Data from Energy Trapezoidal Filter. Go4: Calculated (inspected) reaction of the Energy Trapezoidal Filter (from received traces). Energy Filter Start point (Go4) Signal / Traces Energy Filter End point (Go4) Signal / Traces Energy Filter (Go4) FPGA Energy Filter Calc. Energy (FPGA) Energy Filter (FPGA) Energy Note: The calculated reaction of the ETF (in Go4) and the data of the ETF, implemented in FPGA, are the same!
The testing in the Lab of the Febex Data Acquisition System (Energy TF) with Go4 Data from Energy Trapezoidal Filter and Calculated (inspected) reaction of the Energy Trapezoidal Filter (from received traces). The positive input signal The negative input signal Note: The calculated reaction of the ETF (in Go4) and the data of the ETF, implemented in FPGA, are the same!
Testing of the Febex Data Acquisition System (Fast TF Hit finder) with Go4 Double Hits Detection The Summary Data Packet (Hit s time and energy) ADC Signal / Traces Fast Trapezoidal Filter (FPGA) 0xff050134 0x00000090 GOSIP Header // 2 words 0xaf1983b1 Summary Packet Header // 1 words 0x00000008 0x73a0f5d7 Epoch/Global Time Stamp // 2 words 0x00000000 0x00000000 Data for Channel Id 0 // 2 words (no input signal) 0x10000000 0x10000000 Data for Channel Id 1 // 2 words (no input signal) 0x20000000 0x20000000 Data for Channel Id 2 // 2 words (no input signal) 0x30000000 0x30000000 Data for Channel Id 3 // 2 words (no input signal) 0x40000000 0x40000000 Data for Channel Id 4 // 2 words (no input signal) 0x50000000 0x50000000 Data for Channel Id 5 // 2 words (no input signal) 0x60000000 0x60000000 Data for Channel Id 6 // 2 words (no input signal) 0x70000000 0x70000000 Data for Channel Id 7 // 2 words (no input signal)... 0x8a4081cf 0x8eeeeee2 Data for Channel Id 8 // 2 words The first word: 0x8 (bits [31:28]) Channel Id 0xa (bits [27:24]) Hit counter for the Channel 0x4 (bits [23:20]): Bit (23) = 0 always 0 Bit (22) = 1 Flag More than one Hit in the Trigger Window Bit (21) = 0 Flag Only one Hit in the Trigger Window, but not Full Filter Window Bit (20) = 0 Flag Only one Hit in the Trigger Window 0x0 (bits [19:16]) always 0x0 0x81cf (bits [15:0]) Relative Hit s Time (to Global Time Stamp)// MSB is a sign bit The second word Channel Id and Measured Energy... 0x9a4081cf 0x9eeeeee2 Data for Channel Id 9 // 2 words 0xaa4081cf 0xaeeeeee2 Data for Channel Id 10 // 2 words 0xba4081cf 0xbeeeeee2 Data for Channel Id 11 // 2 words 0xca4081cf 0xceeeeee2 Data for Channel Id 12 // 2 words 0xda4081cf 0xdeeeeee2 Data for Channel Id 13 // 2 words 0xea4081cf 0xeeeeeee2 Data for Channel Id 14 // 2 words 0xfa4081cf 0xeeeeeee2 Data for Channel Id 15 // 2 words... 0xbf1983b1 Summary Packet Trailer // 1 words Note: Due to the Data Reduction, the words, marked in red, are not sent out no found hits, no data for these channels in the summary packet!
Febex Data Acquisition System (test setup) Accepted Trigger Trigger&Clock Bus Febex Module Self Triggers Input Signal Fiber Optic Accepted Trigger Exploder Module Self Triggers Input Signal
The testing in the Lab of the Febex Data Acquisition System ( Low Signal with Noise ) with Go4 Febex 3a / 14-bit / 50 MHz (ADC s traces of Ch0... Ch15) Febex 3a / 14-bit / 50 MHz (FPGA s Energy Filter (ETF)) ADC ADC Febex 3a / 14-bit / 50 MHz (ADC s trace of Ch_Id0: U ~ 2 mv) Febex 3a / 14-bit / 50 MHz (FPGA s Hit s Energy)
60 The testing of the Febex Data Acquisition System with radioactive source Co Energy Resolution of 2.5... 2.7 kev
DC-DC convertor with a Murata Filter : Energy s RMS for different ETF s filter Lengths ETF Length 40-20-40 ETF Length 64-32-64 ETF Length 128-32-128 Febex 3a / 14-bit / 50 MHz (FPGA s Hit s Energy) Febex 3a / 14-bit / 50 MHz (FPGA s Hit s Energy) ETF Length 256-32-256 ETF Length 450-32-450 Febex 3a / 14-bit / 50 MHz (FPGA s Hit s Energy) Febex 3a / 14-bit / 50 MHz (FPGA s Hit s Energy) RMS of Measured Energy Febex 3a / 14-bit / 50 MHz (FPGA s Hit s Energy) ETF Filter Length (A or B Windows) Note: The "RMS" is growing up with the length of the Energy Trapezoidal Filter (ETF). Note: The problem - the low frequency "noise". This "noise" cannot be removed with a ETF.
The base line of the ETF for different ETF s filter Lengths ETF Length 64-32-64 The moving average filter and Signal s baseline instability ETF Energy Trapezoidal Filter ETF Febex 3a / 14-bit / 50 MHz (FPGA s Energy Filter (ETF)) ETF Length 256-32-256 Signal Frequency response of the moving average filter (Steven W. Smith. Digital Signal Processing) ETF Length 1 ETF Length 2 Febex 3a / 14-bit / 50 MHz (FPGA s Energy Filter (ETF)) Low Frequency signal: Baseline instability Note: For each length the responses of the ETF filter will be different. The longer ETF filter is more sensitive to the baseline instability! Note: When A_Window, B_Window = N, then the fluctuations of 1 LSB will produce differences from -N to +N! Note: Main problem Low Frequency noise! The low frequency components are dominating!
New Method: High Pas Filter with a Moving Accumulating Window (HPF & MAccW) Reconstruction of the Input Signal (MAccW = 32 ADC samples) Reconstruction of the Input Signal (MAccW = 256 ADC samples) Reconstruction of the Input Signal (MAccW = 1022 ADC samples) ADC ADC ADC ADC samples (Traces) ADC samples (Traces) ADC samples (Traces) Measured Amplitude of the Input Signal Measured Amplitude of the Input Signal Measured Amplitude of the Input Signal Amplitude in ADC counts Amplitude in ADC counts Amplitude in ADC counts
DC-DC convertor with a Murata Filter : Measurement of the Amplitudes of the Input Signals (using the new method: HPF & MAccW) Measured Amplitudes (ADC s ) ADC Amplitude, mv Amplitude of Input Signal, mv (Febex 3a / 14-bit / 50 MHz) Measured Amplitudes (50 mv... 400 mv) Note: The Febex s ADC sees about 50 % from the amplitude of the input signal!
That is all! Tank you!