Development. Igor Sheviakov Manfred Zimmer Peter Göttlicher Qingqing Xia. AGIPD Meeting April, 2014

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1 Textmasterformat AGIPD Firmware/Software bearbeiten Igor Sheviakov Manfred Zimmer Peter Göttlicher Qingqing Xia AGIPD Meeting April, 2014

2 Outline Textmasterformat bearbeiten Reminder: hardware set-up FPGA firmware/software development Reminder: concept of AGIPD FPGA firmware/software Standalone DAQ software development Status of FPGA firmware development Summary and Outlook

of AGIPD FPGA firmware/software Standalone DAQ software

3 Textmasterformat bearbeiten Reminder: Hardware Set-Up Vacuum board ASICs ceramic board Digital read out Backplane Analogue boards

4 AGIPD Textmasterformat FPGA Firmware/Software bearbeiten FPGA firmware/software development

5 Textmasterformat Reminder: concept bearbeiten of AGIPD FPGA Firmware/Software PC Cmd Editor Image Image (ADC) (ADC) Files Files DAQ Control Application Image Image (ADC) (ADC) Files Files FPGA Power PC Embedded System Initial Boot Ethernet 1GbE X ASIC Chip Select & Power Switch I2C Bus Master Control Firmware Registers BRAMs IMAGE Data Master Firmware Periphery Control Base Firmware Blocks Clk, Data, SoB ADC Clk ADC Data & Clks

Initial Boot Ethernet 1GbE X ASIC Chip Select & Power Switch I2C Bus.

6 Textmasterformat bearbeiten Standalone DAQ software DAQ monitor & control application Basic features available: Gigabit Ethernet(TCP/IP) client Triggering and debugging execution of user detector algorithms Receive images packets & assembling image Record image into hard disk (Binary & ASCIIs files) ASICs chip select & power switching Advance functions in debugging and test stage

detector algorithms Receive images packets & assembling image Record image into hard disk

7 Textmasterformat bearbeiten Standalone DAQ software User command editor Added: Sent to FPGA to update user algorithm

8 Status Textmasterformat of AGIPD FPGA bearbeiten Firmware Things are done and working! Power PC TCP/IP Server DAQ Monitor and Control software Command interpreter (3-Lines periphery interface) Command sequence 64 channels ADC readout (*fine tuning for every FPGA board?) Record images data into DDR2 memory (Power PC DMA Engine) Transmit image data via TCP/IP Gigabit Ethernet AGIPD 10G standalone module: Faked data emulating AGIPD image structure DDR2 Memory 10G Gigabit Ethernet I2C control for ASICs chip select and power switch

channels ADC readout (*fine tuning for every FPGA board?

9 Status Textmasterformat of AGIPD FPGA bearbeiten Firmware Talk to the ASIC periphery interface PC Cmd Editor Image Image (ADC) (ADC) Files Files Monitoring Control Application FPGA Power PC Embedded System Initial Boot Ethernet 1GbE Master Control Firmware Registers BRAMs Master Firmware Periphery Control Clk, Data, SoB

Control Application FPGA Power PC Embedded System Initial Boot Ethernet 1GbE.

10 Status Textmasterformat of AGIPD FPGA bearbeiten Firmware 64 Channels ADC image data readout PC Cmd Editor Image Image (ADC) (ADC) Files Files Monitoring Control Application FPGA Power PC Embedded System Initial Boot Ethernet 1GbE X Master Control Firmware Registers BRAMs IMAGE Data Master Firmware Periphery Control Base Firmware Blocks Clk, Data, SoB ADC Clk ADC Data & Clks

Embedded System Initial Boot Ethernet 1GbE X.

11 Status Textmasterformat of AGIPD FPGA bearbeiten Firmware Standalone 10G Channel AGIPD Image pattern generator DDR2 memory controller 10GE firmware BRAM for one Image Image data 32 bits 10GE Dual Port FIFO Central 128 bits Data Flow 128 bits Control Channel Dual Port BRAM 64 MHz Channel Data Flow Control 64 bits MAC + XAUI Cores 4x 3.125Gbps serial data Header Distributer Header BRAM

Dual Port FIFO Central 128 bits Data Flow 128 bits Control Channel Dual Port BRAM 64 bits @156.

12 Textmasterformat AGIPD Software/Firmware bearbeiten Summary & Outlook

13 Textmasterformat bearbeiten Status and Summary Standalone DAQ system development Basic features available: Gigabit Ethernet TCP/IP server Triggering and debugging execution of user detector algorithms Receive images packets & assembling image Record image into hard disk (Binary & ASCIIs files) ASICs chip select & power switching FPGA Firmware Power PC TCP/IP Ethernet Client PC DAQ System Command Interpreter (3-Lines ASIC periphery interface) Command Editor 64 channels ADC readout (image data) Record images data into DDR2 memory (Power PC DMA Engine) Transmit image data via TCP/IP Gigabit Ethernet I2C control for ASICs chip select and power switch AGIPD 10G standalone module: Faked data emulating AGIPD image structure DDR2 Memory 10G Gigabit Ethernet

DAQ System Command Interpreter (3-Lines ASIC periphery interface) Command Editor 64 channels ADC readout (image data) Record images data into DDR2 memory (Power PC DMA Engine) Transmit

14 Textmasterformat bearbeiten Things to do Preparation for beam test in APS in June Shipping list cross check with FS-DS Standalone DAQ system More user friendly and simplified GUI interface 10G UDP listener test FPGA Firmware Understanding the instability of ADC readout (hardware? Firmware?) Fine Tuning of ADC synchronization with ASIC command Pattern A,B,C tests (command editor templates) 10G module integration APS conditions (trigger, timing, ) adaption Hardware debugging

the instability of ADC readout (hardware? Firmware?

15 Textmasterformat AGIPD Software/Firmware bearbeiten Thank You!

16 Textmasterformat AGIPD Software/Firmware bearbeiten Spare Slides

AGIPD Interface Electronic Prototyping

AGIPD Interface Electronic Prototyping P.Goettlicher I. Sheviakov M. Zimmer - Hardware Setup, Measurements - ADC (AD9252 14bit x 8ch x 50msps ) readout - Custom 10G Ethernet performance - Conclusions Test