The muon L0 Off Detector Electronics (ODE) for the LHCb experiment

The muon L0 Off Detector Electronics (ODE) for the LHCb experiment A. Balla, M. Beretta, M. Carletti, P. Ciambrone, G. Corradi, G. Felici INFN Laboratori Nazionali di Frascati - Via E. Fermi 40, 044 Frascati (Rome), Italy giulietto.felici@lnf.infn.it M. Gatta INFN Roma2 - Via della Ricerca Scientifica 1, 133 Rome, Italy 1

Outline Apparatus main features The muon system detectors Readout system block diagram The muon trigger FEE requirements The muon off detector electronics ODE Overview Numbers Trigger data path Piggy Boards DAQ data path DAQ data frame L0 controller ODE ECS Clock distribution chain Jitter measurements BER estimation Radiation environment Conclusions 2

Apparatus main features reconstruct B-decay vertex with a good resolution provide identification for charged particles Q1 R4 R3 R1 R2 Muon detector Station 1 Muon detector Stations 2-5 3

The muon system detectors MWPC Number of MWPC: 1368 Readout: wires, pads, wires + pads Four gap chambers in Stations M2-M5. Two gap in M1 (R2-R4). Gas gap: 5 mm Wire: Gold-plated Tungsten, 30 mm dia. Wire spacing: 2 mm Wire length: 250 to 310 mm Gas mixture: Ar/CO2/CF4 (40:50:10) Gas gain: G 10 5 Charge/mip: 0.8 pc @ HV 2.7 kv Gap efficiency: 95% in 20 ns window ( σ t 3.9 ns) Rate/channel: max 2 MHz in M1, < 0.6 MHz M2-M5 4

Readout system block diagram FEE channels Logical channels Trigger Sectors Because of single channel occupancy and electrode capacitance the physical detector segmentation is smaller than segmentation required by trigger LHCb Muon Detector Granularity Number of FEE Channels 126832 Logical channels IB SYS Physical channels Number of Logical Channels (FE Boards) Number of Logical Channels (IB Boards) 19584 8640 LV PS Total Number of Logical Channels 28224 Number of Trigger Sectors 1248 ODE SYS Logical channels Trigger & DAQ 5

The muon trigger FEE requirements Muon Trigger FE Main Tasks Provide information for the L0 Muon Trigger Muon tracks identification P t measurement Merging (some of) the FEE channels to generate the logical ones Align them in time, minimizing inefficiencies due to time misalignment Bunch crossing alignment (BX identifier, 25 ns step) Fine time alignment (single channel t 0, 1.5 ns step) Deliver the logical channels together with the BX identifier to the trigger logic Moreover the system must: Include an interface to the DAQ Include monitor and diagnostic facilities of circuitry and detector functionalities 6

The muon off detector electronics Trigger Sector ½Chamber i Physical chs (1/2 chamber) 48x2 FE board LVDS outputs (1/2 chamber) 48 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 01 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 M2 R3 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 23 01 23 IB system Logical H chs (1 TS) 4 ½Chamber i+1 01 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 23 01 23 Logical V chs (1 TS) 24 Trigger Sector 1/4 Chamber i 0 03 1 2 3 0 5 0 4 0 4 0 4 11 03 4 5 6 7 2 6 1 5 1 5 1 5 M1 R1 0 1 2 3 3 7 2 6 2 6 2 6 Trigger & DAQ 4 5 6 7 4 8 3 7 3 7 3 7 11 ODE system 7

ODE overview Logical channels Bx alignment L0 buffer L0 derandomizer Input channel Sync LVDS Receiver Bunch cross synchr. Trig OUT TRIGGER DATA PATH Parallel Optical Transm. TRIGGER O.L. Send data to trigger via 12 parallel optical link @ 1.6Gbit/s L0 pipeline & L0 derand. Data OUT ELMB CAN BUS Format and send data to common L1 board via optical link @ 1.6Gbit/s L0 LINK TTCRX DEJITTER TTC DECODER L0 COUNTER TEST PATTERN GENERATOR ECS JTAG JTAG Test facilities for control and debug Clock de-jitter and distribution BC COUNTER CONTROL LOGIC CONFIG REGISTER DATA CHECK DATA FORMAT ERROR CODE GENERATOR M U X DAQ DATA PATH VCSEL DAQ O.L. ECS interface I2C JTAG L0 Controller ODE BOARD 8

ODE numbers 192 LVDS input signals 10 layers motherboard 6U Compact PCI card Mixed 5/3.3/2.5 V devices 1 TTCrx chip mounted on motherboard 1 de-jitter circuit QPLL 24 chips Mounted on piggy board 12 chips for trigger 1 parallel optical transmitter (12 channels) 1 Board controller FPGA 1 chip for DAQ 1 VCSEL laser 1 ELMB board for ECS interface 9

ODE trigger data path Unidirectional data transfer to trigger system Each every machine cycle (40,08 MHz) Receives and synchronizes 8 input signals Assign correct Bunch Crossing identifier (BX_Id) 10 bit data out (8 hits + 2 LSB of BC_Id) 2, 3 or 4 s per trigger sector (TS) Parallel Optical Transmitter TRIGGER DATA PATH LVDS Receiver 1 per TS Transmission (tx_en, tx_er) driven by one master Fast Ethernet mode (8B/10B) Bunch cross Synchronization TRIG DATA OUT TEST LINK CTRL TX_en TX_er 12 s drive a parallel optical link HFBR772B - 1.6 Gbit/s x 12 link Test link facilities Link check integrity BER test 31 BX_Id 1 st word 14 HIT DATA 0 1 14 HIT DATA 0 0 2 nd word 14 HIT DATA 0 1 14 HIT DATA 1 0 3 rd word 14 HIT DATA 1 1 14 HIT DATA 0 0 4 th word 14 HIT DATA 1 1 14 HIT DATA 1 0 10 16 Switch 0

ODE Piggy Boards Trigger sector type vs ODE configuration Station Region Logical Channel per TS per TS TS per ODE () Active ODE Channels M1 M2 or M3 R1 R2 R3 R4 R1 R2 R3 R4 24 28 16 28 28 3 4 2 4 4 8 6 12 6 6 192 168 192 168 168 Mother Board + Piggy Boards M4 or M5 R1 R2 R3 R4 24 14 10 10 3 2 2 2 8 12 12 12 192 168 120 120 Minimize number of PCB layouts Unique motherboard for all TS 12 piggy board slots 6 / 8 / 12 (active optical link) per ODE 3 different piggy boards 24 per ODE (2 / 3 / 4 per piggy board) 120 / 168 / 192 active input signals Piggy Board type 1 (2 s) 11

ODE DAQ data path Unidirectional data transfer to L1 DAQ Measure input signal phase vs LHCb clock period Put data in L0 buffer (40,08 MHz) Put data in L0 derandomizer after L0 trigger (1 MHz) TDC Bx cnt Hamming code L0 buffer EV cnt EDAC Hamming code ERR data format 32 bit for TDC data (data word) 32 bit for BX_Id, EV_Id, data error (info word) 32 bit output data bus 24 X 2 access X 25 ns = 12 ns > 9 ns BUS_UP L0 Controller L0 derandomizer EDAC OutMux 32 x 2 DATA TX_en ERR VCSEL Parallel readout mode 2 x 32 bit wide buses (BUS_UP, BUS_DW) 12 Sync for each bus L0 controller Read data/info words from de-randomizers Create L1 DAQ data frame Drive (tx_en, tx_er) o Ethernet mode o VCSEL diode BUS_DW TX_er DAQ DATA FLOW 12

ODE DAQ data frame Data frame is preceded by an idle character Data frame is 30 words long 1 32 Header 2 1 0 2 3 4 Data word Sync1 Data word Sync2 Data word Sync3 Hamming code (6 bit) BC_Id (12 bit) L0_id (12 bit) BC Check (1 bit) 5 Data word Sync4 6 Data word Sync5 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 24 Data word Sync23 CH15 CH14 CH13 CH12 CH11 CH10 CH9 CH8 25 26 Data word Sync24 data_check word TDC data (4 bit) 27 BC_check word 28 29 EV_check word Error Flag word 23..11 10..4 3..1 0 30 Check-sum n Check bit ch. n 13

L0 controller Receive and decode TTCrx data Control readout Format data for L1 DAQ Check data synchronization Drive transmission DATA UP DATA DW TTCRX DATA DATA SWITCH TTC DECODE Info_bus FIFO HEADER Hamming code FIFO 32x16 Error detect CHK FOOTER Test facilities Known pattern and PRBG for link integrity test Internal data frame dump fifo TTC control signal internal emulation Error condition monitor I 2 C interface FROM ECS I2C INTERFACE Error Register Serial to Parallel I 2 C_bus Data_bus FOOTER + CHKSUM Hamming code SCAN LOGIC CTRL CS CTRL TEST LOGIC FIFO dump PATTERN PRBG DATA CS Anti-fuse technology FPGA (ACTEL AX5) L0 CONTROLLER 14

ODE ECS ECS interface via ELMB card CANbus interface ELMB internal connection 2 I 2 C buses 24 13, TTCrx, L0 controller 1 bus JTAG Initialization time JTAG Controller ELMB CAN TRANSCEIVER JTAG TEST FACILITIES I 2 C EMULATION CAN BUS L0 Controller Byte x Device I 2 C Byte x Device Device x ODE Total Byte TTCrx L0 CONTROLLER TTCrx 3 7 9 28 1 1 9 28 JTAG BUS 4 16 13 208 6 18 24 432 24 13 Total Byte 677 Init Time 60 ms 15

Clock distribution Receive LHCb clock (40.08 MHz) Completely synchronous system TTCrx recovered clock jitter filter TTCrx jitter > 240 ps peak to peak (30 ps RMS) Maximum allowed jitter 1 ps peak to peak Narrow bandwidth PLL QPLL Low jitter clock distribution PECL standard (RMS jitter specs < 1 ps), and Board Controller FPGA 1 to 4 CLOCK DISTRIBUTOR (PECL) PIGGY BOARD TTCrx PLL 1 to 10 CLOCK DISTRIBUTOR (PECL) 1 to 4 CLOCK DISTRIBUTOR (PECL) VCXO 1 to 4 CLOCK DISTRIBUTOR 16

Jitter measurements eye diagram 0,7 UI 0,7 UI Trigger link DAQ link QPLL clock jitter 6,02 ps rms 17

BER estimation Trigger -16 DECADE DAQ -16 DECADE 18

Radiation environment Data from LHCb electronics website (simulation safety factor of 2) Total dose (rad) (10 years) 7.9 10 3 1 MeV Neutron eq. (10 years) 9.8 10 11 Hadrons > 20 MeV (10 years) 5.0 10 10 L0 controller FPGA State machines implemented with triple modular redundancy (TMR) technique Triple voted and auto-corrected registers Anti-fuse technology (Actel AX5) Qualified Tested To be tested (CERN) VCSEL Honeywell - (Rad( Rad-Tol technology) TTCrx (CERN) HFE439X-541 (CMS HCAL + - MC1EPT20, MC1EPT26, Honeywell) ELMB (ATLAS test) MC1LVEP1 MC1LVEP111 (CMS) QPLL (CERN) - Actel FPGA Parallel Optical link HFBR772B (Marseille) 19

Conclusions The Off Detector Electronics (ODE board) of the LHCb muon system has been presented. The ODE board receives the logical channels and generates the Trigger Sectors Three types of piggyback boards and a single ODE motherboard are used to fit every trigger sectors topologies The ODE board main features are: 192 inputs (LVDS standard) A parallel optical link with an overall bandwidth of ~ 20 Gbits/s as interface to the trigger system Circuitry for L0 functionality A 1.6 Gbit/s optical link as interface to L1 DAQ. A BER of about 10-16 can be inferred from preliminary measurements 20