Front-End Card Interface of the RCU

Transcription

1 Front-End Card Interface of the CU (Bernardo Mota & Carmen Gonzalez Gutierrez) ALTO Interface Board Controller Interface Block diagram Memories and Functionality Block diagram Table of egisters Macro Instructions Microcontroller Code Present Status FEC debugging capabilities

2 FEC Interface: Block Diagram DDL Design Focus Slow Control

3 ALTO Interface: Block Diagram cstb rcu_data 32 Decoder egister Table Counter Table writeb rcu_add ackb CU Master exec abort busy rcu_re Instruction MEM FSM Pattern MEM dstb trsfb 4 ALTO BUS rcu_valid esult MEM Data Data bd interrupt MEM 2 MEM 1 errorb L1, L2 data_valid xoff ASSEMBLE & DDL 4 data

4 ALTO Interface: Memories and Functionality Instruction Memory esult Memory Data Memory x 2 Pattern Memory DI DO DI DO DI DO DI DO AD AD AD AD 23 bit bit bit bit 124 WE WE WE WE INCLK INCLK INCLK INCLK OUTCLK

5 ALTO Interface: CU Macro Instructions JUMP 4 h 8 hxx Add. CHDO 4 h6 hxxxx S_STATUS S_L1CNT S_L2CNT 4 h1 4 h2 4 h3 hxxxx hxxxx hxxxx PMEAD PMWITE 4 h7 4 h8 4 hx hx channel add. bcast chann. add. END 4 h9 hxxxx LOOP 4 h4 8 hxx N cycles ETUN 4 h hxx Add. WAIT 4 ha 15 Nbr. Cycles CLK

6 ALTO Interface: Microcontroller code LOOP WITE N EG EAD N EG PMWITE PMEAD CONFIG *END* ETUN JUMP Testing egisters and Memories of the ALTOs & Configuration Testing Multi-Event Buffer & eadout SWTG (L1) WAIT WPINC (L2) CHDO (eadout) PINC *END* Normal Trigger sequence

7 ALTO Interface: Debugging Capabilities

8 BC Interface: Block Diagram CU ALTO BUS Master write,cstb BD 4 2 1ack scl I2C Master sda_ in sda_ out ALTO BUS INTEFACE we D AD mux I2C Slave AD 5 D we L1 ADC I2C Slave sda scl oti decoder I2C Master clr_cnt AD D we egister Block L1_cnt L2_cnt Trigger Dout L2 Board Controller counters

9 BC Interface: Table of egisters eg. Addr. Mnemonic eg. Name Width Acc. Mod e Allow Bcas t Meaning 1 T_TH Temperature Thr. 1 /W Maximum Temperature Threshold 2 3 AV_TH AC_TH AV threshold AC threshold 1 1 /W /W THESHOLDS Minimum Analog Voltage Threshold Maximum Analog Current Threshold 4 DV_TH DV threshold 1 /W Minimum Digital Voltage Threshold 5 DC_TH DC threshold 1 /W Maximum Digital Current Threshold 8 TEMP Temperature 1 N/A Temperature Value 9 A AV AC Analog Voltage Analog Current 1 1 N/A MEASUABLES N/A Analog Voltage Value Analog Current Value B DV Digital Voltage 1 N/A Digital Voltage Value C DC Digital Current 1 N/A Digital Current Value 1 11 L1CNT L2CNT L1 Counter L2 Counter N/A COUNTES N/A Number of L1 Trigger eceived Number of L2 Trigger eceived 12 SCLKCNT Sampling clk counter N/A Sampling Clock counter 13 DSTBCNT Data Strobe Counter 8 N/A Number of Data Strobe in the last eadout

10 BC Interface: Table of egisters 14 CS Configuration Status 14 /W Interrupt - Mask egister 15 CS1 Configuration Status 1 14 Error Status egister CS2 Configuration Status 2 /W Card Configuration Status egister 18 CNTLAT Counters Latch - W Latch L1, L2, SCLK counters CNTCL Counters Clear - W Clear L1, L2, SCLK counters 1A CS1CL Conf. St. eg 1 Clear - W Clear Error Status egister 1B ALST ALTO eset - W eset all the ALTOs 1C BCST BC eset - W eset Board Controller 1D STCNV Start Conversion madc - W Start Conversion / ead Out Monitor ADC

11 BC Interface: System level Architecture Each TPC Sector is served by 6 eadout Subsystems FEC 128 ch FEC 128 ch FEC 128 ch FEC 128 ch Overall TPC: I 2 C bus {SDA,SCL} INT CONF. & /O MON. & CTL DATA POC. DATA MEMO FEC CONTOLLE CU DAQ INT (DDL-SIU) DCS INT (POFIB, ETHE,...) TIGGE INT (TTC-X) UX 4356 Front End Card 2 eadout Control Unit The control network shares the same back-plane as the ALTO bus, using the same GTL transceivers. CX CONFIG. & EADOUT NETWOK (1 MB / s) DCS NETWOK The Electrical implementation of the I 2 C bus consists of 3 unidirectional lines instead of 2 bidirectional links.

12 THE FONT-END CAD (FEC) BC Interface: Physical Layout 5-channel 1bit ADC voltage regulators Current monitoring & supervision ALTOs Shaping Amplifiers (PASAs) power connector FPGA hosting Board Controller logic and register set control bus connector readout bus connectors mm GTL transceivers (back side) 155 mm

13 I 2 C Bus BC Interface: I2C Protocol

14 I 2 C Bus BC Interface: I2C Protocol Transmission rate up to 3.4Mbit/sec in High Speed mode Worldwide standard protocol developed by Philips Maximum allowed bus capacitance of 4pF FECs can be connected or disconnected without disturbing the network functioning Bi-directional 8-bit serial data transfer Multi-master protocol with Arbitration

15 Present Status ALTO Interface X IP design completed and simulated Testing in PLDA board: End of October Additional macro instructions and active channel list to be included Board Controller Interface BC ADC : Design completed, simulated and tested CU BC (I2C + ALTO bus): integration and test missing