Data Sheet PD No. reva Features Gate drive supply range from V to V Undervoltage lockout for V BS and V CC. V and V input logic compatible Tolerant to negative transient voltage Matched propagation delays for all channels RoHS compliant Description The IRS8 is a high voltage, high speed power MOSFET and IGBT single high-side driver with propagation delay matched output channels. Proprietary HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. The floating logic input is compatible with standard CMOS or LSTTL output, down to. V logic and can be operated up to V above the ground. The output driver features a high pulse current buffer stage designed for minimum driver cross-conduction. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high-side configuration, which operates up to V. ical Connection SINGLE HIGH SIDE DRIVER IC Product Summary Package V OFFSET I O +/- V OUT t on/off (typ.) V max. A / A V - V ns & ns 8-Lead SOIC IRS8 up to V V CC IN V CC IN V B HO COM V S TO LOAD (Refer to Lead Assignments for correct pin configuration). This diagram shows electrical connections only. Please refer to our Application Notes and DesignTips for proper circuit board layout. www.irf.com
Absolute imum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Symbol Definition Min.. Units V CC Low-side supply voltage -. (Note ) V IN Logic input voltage (HIN) COM -. V CC +. V B High-side floating well supply voltage -. (Note ) V S High-side floating well supply return voltage V B - V B +. V HO Floating gate drive output voltage V S -. V B +. dv s /dt Allowable V S offset supply transient relative to COM V/ns P D Package power dissipation @ T A + C. W Rth JA Thermal resistance, junction to ambient C/W T J Junction temperature - T S Storage temperature - T L Lead temperature (soldering, seconds) Note : All supplies are fully tested at V. An internal V clamp exists for each supply. V C Recommended Operating Conditions For proper operation, the device should be used within the recommended conditions. All voltage parameters are absolute voltages referenced to COM. The offset rating are tested with supplies of (V CC -COM)=(V B -V S )= V. Symbol Definition Min.. Units V CC Low-side supply voltage V IN HIN input voltage COM V CC V B High-side floating well supply voltage V S + V S + V S High-side floating well supply offset voltage Note V V HO Floating gate drive output voltage V S V B T A Ambient temperature - C Note : Logic operational for V S of - V to V. Logic state held for V S of - V to -V BS. (Please refer to the Design Tip DT97- for more details). www.irf.com
Dynamic Electrical Characteristics (V CC -COM)=(V B -V S )= V, T A = o C. C L = pf unless otherwise specified. All parameters are referenced to COM. Symbol Definition Min... Units Test Conditions t on Turn-on propagation delay (V S -COM) = V t off Turn-off propagation delay (V S -COM) = V ns t r Turn-on rise time t f Turn-off fall time Static Electrical Characteristics (V CC -COM)=(V B -V S )= V. The V IN, V TH, and I IN parameters are referenced to COM. The V O and I O parameters are referenced respective V S and are applicale to the respective output leads HO. The V CC parameters are referenced to COM. The V BSUV parameters are referenced to V S. Symbol Definition Min... Units Test Conditions V CCUV+ V CC supply undervoltage positive going threshold 8. 8.9 9.8 V CCUV- V CC supply undervoltage negative going threshold 7. 8. 9. V BSUV+ V BS supply undervoltage positive going threshold 8. 8.9 9.8 V BSUV- V BS supply undervoltage negative going threshold 7. 8. 9. I LK High-side floating well offset supply leakage current V B = V S = V I QBS Quiescent V BS supply current 8 I QCC Quiescent V CC supply current V IH Logic input voltage. V IL Logic input voltage.8 V OH, HO HO high level output voltage, V BIAS - V O V OL, HO HO low level output voltage, V O I IN+ Logic input bias current V HIN = V µa I IN- Logic input bias current V HIN = V I O+, HO Output high short circuit pulsed current HO I O-, HO Output low short circuit pulsed current HO V µa V mv A HIN = V or V I O = ma V O = V, V IN = V PW µs V O = V, V IN = V PW µs www.irf.com
Functional Block Diagram VCC COM V VREG VCCUV DETECT HIGHSIDE CHANNLE VB HIN PULSE GEN LEVEL SHIFT UP FILTER, LATCH UV DETECT DRIVER HO VS Lead Definitions Symbol V CC COM V B HO V S HIN Description Low-side supply voltage Ground High-side drive floating supply High-side driver outputs High voltage floating supply return Logic inputs for high-side gate driver output (in phase) Lead Assignments VCC VB 8 HIN IRS8S HO 7 VS COM 8-Lead SOIC www.irf.com
IRS8PbF IN % % t on t r t off tf OUT % 9% 9% % Figure. Switching Time Waveforms HIN HO Figure. Input/Output Timing Diagram www.irf.com
T u r n - O n P r o p a g a t i o n D e l a y ( n s ) - - 7 Figure A. Turn-On Propagation Delay vs. T u r n - O n P r o p a g a t i o n D e l a y ( n s ) 8 Figure B. Turn-On Propagation Delay vs. Supply Voltage Turn- Off Propagation Delay (ns) - - 7 Figure A. Turn-Off Propagation Delay vs. T u r n - O f f P r o p a g a t i o n D e l a y ( n s ) 8 Figure B. Turn-Off Propagation Delay vs. Supply Voltage www.irf.com
T u r n - O n R i s e T i m e ( n s ) T u r n - O n R i s e T i m e ( n s ) - - 7 8 Figure A. Turn-On Rise Time vs. Figure B. Turn-On Rise Time vs. Supply Voltage Turn- Off Fall Time ( ns) - - 7 Figure A. Turn-Off Fall Time vs. Turn- Off Fall Time ( ns) 8 Figure B. Turn-Off Fall Time vs. Supply Voltage www.irf.com 7
Logic "" Input Voltag e (V)... Logic "" Input Voltage (V)... - - 7 Figure 7A. Logic "" Input Voltage vs. 8 Figure 7B. Logic "" Input Voltage vs. Supply Voltage.9.9 Logic "" Input Voltage (V).8.7...... Min Logic "" Input Voltage (V).8.7...... Min - - 7 8 Figure 8A. Logic "" Input Voltage vs. Figure 8B. Logic "" Input Voltage vs. Supply Voltage www.irf.com 8
High Level Output (mv) 9 8 7 - - 7 Figure 9A. High Level Output vs. (Io = ma) H i g h L e v e l O u t p u t ( m V ) 7 8 Figure 9B. High Level Output vs. Supply Voltage (Io = ma) Low L evel Output (m V) Low Level Output (mv) - - 7 Figure A. Low Level Output vs. (Io= ma) 8 Figure B. Low Level Output vs. Supply Voltage (Io= ma) www.irf.com 9
Offset Supply Leakage Current (µa) - - 7 O f f s e t S u p p l y L e a k a g e C u r r e n t ( µ A ) 8 Figure A. Offset Supply Leakage Current vs. Figure B. Offset Supply Leakage Current vs. Supply Voltage 8 V B S Supp ly Current (µa) 8 V BS Supply Current (µa) - - 7 8 Figure A. V BS Supply Current vs. Figure B. V BS Supply Current vs. Supply Voltage www.irf.com
V CC Supp ly Current (µa ) V CC Supply Current (µa ) - - 7 8 Figure A. V CC Supply Current vs. Figure B. V CC Supply Current vs. Supply Voltage Logic "" Input Bias Current (µa) - - 7 L o g i c " " I n p u t B i a s C u r r e n t ( µ A ) 8 Figure A. Logic "" Input Bias Current vs. Figure B. Logic "" Input Bias Current vs. Supply Voltage www.irf.com
Logic "" Input Bias Current (µa) - - 7 Figure A. Logic "" Input Bias Current vs. Logic "" Input Bias Current (µa) 8 Figure B. Logic "" Input Bias Current vs. Voltage V CC UVL O Threshold (+) (V) 9 8 7 Min V CC UVLO Threshold (-) (V) 9 8 7 Min - - 7 - - 7 Figure. V CC Undervoltage Threshold (+) vs. Figure 7. V CC Undervoltage Threshold (-) vs. www.irf.com
V B S UVL O Threshold (+) (V) 9 8 Min 7 - - 7 V B S UVLO Threshold (-) (V) 9 8 7 Min - - 7 Figure 8. V BS Undervoltage Threshold (+) vs. Figure 9. V BS Undervoltage Threshold (-) vs. Outp ut Source Current (A)..... - - 7 Figure A. Output Source Current vs. O u t p u t S o u r c e C u r r e n t ( A ) 8 Figure B. Output Source Current vs. Supply Voltage www.irf.com
Output Sink Current (A)..... - - 7 Figure A. Output Sink Current vs. O utp ut Sink Cur r ent ( A) 8 Figure B. Output Sink Current vs. Supply Voltage Case outline A E X D 8 7 e B H. [.] A. [.] X.7 [.] FOOTPRINT 8X.7 [.8] 8X.78 [.7] DIM INCHES MILLIMETERS MIN MAX MIN MAX A A...88.98...7. b.... c.7.98.9. D E.89.97.98.7.8.8.. e. BASIC.7 BASIC e. BASIC. BASIC H K L y.8.99...9. 8.8.....7 8 e A C y K x 8X b. [.] C A B NOTES: A. DIMENSIONING & TOLERANCING PER ASME Y.M-99.. CONTROLLING DIMENSION: MILLIMETER. [.]. DIMENSIONS ARE SHOWN IN MILLIMETERS [INCHES].. OUTLINE CONFORMS TO JEDEC OUTLINE MS-AA. 8-Lead SOIC 8X L 7 8X c. OUTLINE CONFORMS TO JEDEC OUTLINE MS-AA. DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS. MOLD PROTRUSIONS NOT TO EXCEED. [.]. DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS. MOLD PROTRUSIONS NOT TO EXCEED. [.]. 7 DIMENSION IS THE LENGTH OF LEAD FOR SOLDERING TO A SUBSTRATE. -7 www.irf.com
Tape & Reel 8-lead SOIC LOADED TAPE FEED DIRECTION B A H D F C NOTE : CONTROLLING DIMENSION IN MM E G CARRIER TAPE DIM ENSION FOR 8SOICN Metric Im perial Code Min Min A 7.9 8...8 B.9... C.7...8 D....8 E...8. F....8 G. n/a.9 n/a H...9. F D E C B A G H REEL DIM ENSIONS FOR 8SOIC N Metric Im perial Code Min Min A 9...97. B.9..8.8 C.8...9 D.9..77.9 E 98...88. F n/a 8. n/a.7 G. 7..7.7 H...88. www.irf.com
LEADFREE PART MARKING INFORMATION Part number Date code IRxxxxxx S YWW? IR logo Pin Identifier? MARKING CODE P Lead Free Released Non-Lead Free Released?XXXX Lot Code (Prod mode - digit SPN code) Assembly site code Per SCOP - ORDER INFORMATION 8-Lead SOIC order 8-Lead SOIC Tape & Reel IRS8STRPbF Rev. Date Page # Description of Change A //8 Not Recommended for new design: Please use IRS8D ton/toff values should read ns not 7ns The SOIC-8 is MSL qualified. This product has been designed and qualified for the industrial level. Qualification standards can be found at www.irf.com IR WORLD HEADQUARTERS: Kansas St., El Segundo, California 9 Tel: () -7 Data and specifications subject to change without notice. //8 www.irf.com