DDR3 SDRAM UDIMM MT8JSF567AZ GB MT8JSF57AZ 4GB GB, 4GB (x7, ECC, DR) 40-Pin DDR3 UDIMM Features Features DDR3 functionality and operations supported as defined in the component data sheet 40-pin, unbuffered dual in-line memory module (UDIMM) Fast data transfer rates: PC3-800, PC3-0600, PC3-8500, or PC3-6400 GB (56 Meg x 7), 4GB (5 Meg x 7) V DD =.5V ±0.075V V DDSPD = 3.0 3.6V Supports ECC error detection and correction Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals Dual rank On-board I C temperature sensor with integrated serial presence-detect (SPD) EEPROM 8 internal device banks Fixed burst chop (BC) of 4 and burst length (BL) of 8 via the mode register set (MRS) Selectable BC4 or BL8 on-the-fly (OTF) Gold edge contacts Halogen-free Fly-by topology Terminated control, command, and address bus Figure : 40-Pin UDIMM (MO-69 R/C E) Module height: 30mm (.8in) Options Marking Operating temperature Commercial (0 C T A +70 C) None Industrial ( 40 C T A +85 C) I Package 40-pin DIMM (halogen-free) Z Frequency/CAS latency.5ns @ CL = (DDR3-600) -G6.5ns @ CL = 9 (DDR3-333) -G4.87ns @ CL = 7 (DDR3-066) -G.87ns @ CL = 8 (DDR3-066) -G0.5ns @ CL = 5 (DDR3-800) -80C.5ns @ CL = 6 (DDR3-800) -80B Notes:. Contact Micron for industrial temperature module offerings.. Not recommended for new designs. Table : Key Timing Parameters Speed Grade Industry Nomenclature Data Rate (MT/s) CL = CL = 0 CL = 9 CL = 8 CL = 7 CL = 6 CL = 5 -G6 PC3-800 600 333 333 066 066 800 667 3.5 3.5 48.5 -G4 PC3-0600 333 333 066 066 800 667 3.5 3.5 49.5 -G PC3-8500 066 066 800 667 3.5 3.5 50.65 -G0 PC3-8500 066 800 667 5 5 5.5-80B PC3-6400 800 667 5 5 5.5 t RCD (ns) t RP (ns) t RC (ns) jsf8c56_5x7az.pdf Rev. C 3/ EN 009 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice.
GB, 4GB (x7, ECC, DR) 40-Pin DDR3 UDIMM Features Table : Addressing Parameter GB 4GB Refresh count 8K 8K Row address 6K A[3:0] 3K A[4:0] Device bank address 8 BA[:0] 8 BA[:0] Device configuration Gb (8 Meg x 8) Gb (56 Meg x 8) Column address K A[9:0] K A[9:0] Module rank address S#[:0] S#[:0] Table 3: Part Numbers and Timing Parameters GB Modules Base device: MT4J8M8, Gb DDR3 SDRAM Part Number Module Density Configuration Module Bandwidth Memory Clock/ Data Rate Clock Cycles (CL- t RCD- t RP) MT8JSF567A(I)Z-G6 GB 56 Meg x 7.8 GB/s.5ns/600 MT/s -- MT8JSF567A(I)Z-G4 GB 56 Meg x 7 0.6 GB/s.5ns/333 MT/s 9-9-9 MT8JSF567A(I)Z-G GB 56 Meg x 7 8.5 GB/s.87ns/066 MT/s 7-7-7 MT8JSF567A(I)Z-G0 GB 56 Meg x 7 8.5 GB/s.87ns/066 MT/s 8-8-8 MT8JSF567A(I)Z-80C GB 56 Meg x 7 6.4 GB/s.5ns/800 MT/s 5-5-5 MT8JSF567A(I)Z-80B GB 56 Meg x 7 6.4 GB/s.5ns/800 MT/s 6-6-6 Table 4: Part Numbers and Timing Parameters 4GB Modules Base device: MT4J56M8, Gb DDR3 SDRAM Part Number Module Density Configuration Module Bandwidth Memory Clock/ Data Rate Clock Cycles (CL- t RCD- t RP) MT8JSF57A(I)Z-G6 4GB 5 Meg x 7.8 GB/s.5ns/600 MT/s -- MT8JSF57A(I)Z-G4 4GB 5 Meg x 7 0.6 GB/s.5ns/333 MT/s 9-9-9 MT8JSF57A(I)Z-G 4GB 5 Meg x 7 8.5 GB/s.87ns/066 MT/s 7-7-7 MT8JSF57A(I)Z-G0 4GB 5 Meg x 7 8.5 GB/s.87ns/066 MT/s 8-8-8 MT8JSF57A(I)Z-80C 4GB 5 Meg x 7 6.4 GB/s.5ns/800 MT/s 5-5-5 MT8JSF57A(I)Z-80B 4GB 5 Meg x 7 6.4 GB/s.5ns/800 MT/s 6-6-6 Notes:. The data sheet for the base device can be found on Micron s Web site.. All part numbers end with a two-place code (not shown) that designates component and PCB revisions. Consult factory for current revision codes. Example: MT8JSF567AZ-GD. jsf8c56_5x7az.pdf Rev. C 3/ EN 009 Micron Technology, Inc. All rights reserved.
GB, 4GB (x7, ECC, DR) 40-Pin DDR3 UDIMM Pin Assignments Pin Assignments Table 5: Pin Assignments 40-Pin DDR3 UDIMM Front 40-Pin DDR3 UDIMM Back Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol V REF 3 5 6 A 9 4 5 8 A 3 6 V DD 9 4 5 DM3 8 V DD DM5 3 0 33 S3# 63 CK 93 S5# 3 5 53 NC 83 V DD 3 NC 4 34 S3 64 CK# 94.6 4 54 84 CK0 4 5 35 65 V DD 95 5 DM0 55 30 85 CK0# 5 46 6 S0# 36 6 66 V DD 96 4 6 NC 56 3 86 V DD 6 47 7 S0 37 7 67 V REFCA 97 43 7 57 87 EVENT# 7 8 38 68 NC 98 8 6 58 CB4 88 A0 8 5 9 39 CB0 69 V DD 99 48 9 7 59 CB5 89 V DD 9 53 0 3 40 CB 70 A0 00 49 30 60 90 BA 0 4 7 BA0 0 3 6 DM8 9 V DD DM6 8 4 S8# 7 V DD 0 S6# 3 3 6 NC 9 RAS# NC 3 9 43 S8 73 WE# 03 S6 33 63 93 S0# 3 4 44 74 CAS# 04 34 DM 64 CB6 94 V DD 4 54 5 S# 45 CB 75 V DD 05 50 35 NC 65 CB7 95 ODT0 5 55 6 S 46 CB3 76 S# 06 5 36 66 96 A3 6 7 47 77 ODT 07 37 4 67 NU 97 V DD 7 60 8 0 48 NC 78 V DD 08 56 38 5 68 RESET# 98 NC 8 6 9 49 NC 79 NC 09 57 39 69 CKE 99 9 0 50 CKE0 80 0 40 0 70 V DD 00 36 30 DM7 6 5 V DD 8 3 S7# 4 7 NF 0 37 3 NC 7 5 BA 8 33 S7 4 7 NF/A4 0 3 3 53 NC 83 3 43 DM 73 V DD 03 DM4 33 6 4 S# 54 V DD 84 S4# 4 58 44 NC 74 A 04 NC 34 63 5 S 55 A 85 S4 5 59 45 75 A9 05 35 6 56 A7 86 6 46 76 V DD 06 38 36 V DDSPD 7 8 57 V DD 87 34 7 SA0 47 3 77 A8 07 39 37 SA 8 9 58 A5 88 35 8 SCL 48 78 A6 08 38 SDA 9 59 A4 89 9 SA 49 8 79 V DD 09 44 39 30 4 60 V DD 90 40 0 V TT 50 9 80 A3 0 45 40 V TT jsf8c56_5x7az.pdf Rev. C 3/ EN 3 009 Micron Technology, Inc. All rights reserved.
Pin Descriptions Table 6: Pin Descriptions Symbol Type Description The pin description table below is a comprehensive list of all possible pins for all DDR3 modules. All pins listed may not be supported on this module. See Pin Assignments for information specific to this module. Ax Input Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A0) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A0 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A0 LOW, bank selected by BAx) or all banks (A0 HIGH). The address inputs also provide the op-code during a LOAD MODE command. See the Pin Assignments Table for density-specific addressing information. BAx Input Bank address inputs: Define the device bank to which an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. BA define which mode register (MR0, MR, MR, or MR3) is loaded during the LOAD MODE command. CKx, CKx# Input Clock: Differential clock inputs. All control, command, and address input signals are sampled on the crossing of the positive edge of CK and the negative edge of CK#. CKEx Input Clock enable: Enables (registered HIGH) and disables (registered LOW) internal circuitry and clocks on the DRAM. DMx Input Data mask (x8 devices only): DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH, along with that input data, during a write access. Although DM pins are input-only, DM loading is designed to match that of the and S pins. ODTx Input On-die termination: Enables (registered HIGH) and disables (registered LOW) termination resistance internal to the DDR3 SDRAM. When enabled in normal operation, ODT is only applied to the following pins:, S, S#, DM, and CB. The ODT input will be ignored if disabled via the LOAD MODE command. Par_In Input Parity input: Parity bit for Ax, RAS#, CAS#, and WE#. RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being entered. RESET# Input (LVCMOS) Reset: RESET# is an active LOW asychronous input that is connected to each DRAM and the registering clock driver. After RESET# goes HIGH, the DRAM must be reinitialized as though a normal power-up was executed. Sx# Input Chip select: Enables (registered LOW) and disables (registered HIGH) the command decoder. SAx Input Serial address inputs: Used to configure the temperature sensor/spd EEPROM address range on the I C bus. SCL Input Serial clock for temperature sensor/spd EEPROM: Used to synchronize communication to and from the temperature sensor/spd EEPROM on the I C bus. CBx I/O Check bits: Used for system error detection and correction. x I/O Data input/output: Bidirectional data bus. Sx, Sx# I/O GB, 4GB (x7, ECC, DR) 40-Pin DDR3 UDIMM Pin Descriptions Data strobe: Differential data strobes. Output with read data; edge-aligned with read data; input with write data; center-aligned with write data. jsf8c56_5x7az.pdf Rev. C 3/ EN 4 009 Micron Technology, Inc. All rights reserved.
GB, 4GB (x7, ECC, DR) 40-Pin DDR3 UDIMM Pin Descriptions Table 6: Pin Descriptions (Continued) Symbol Type Description SDA I/O Serial data: Used to transfer addresses and data into and out of the temperature sensor/ SPD EEPROM on the I C bus. TSx, TSx# Err_Out# EVENT# Output Output (open drain) Output (open drain) Redundant data strobe (x8 devices only): TS is enabled/disabled via the LOAD MODE command to the extended mode register (EMR). When TS is enabled, DM is disabled and TS and TS# provide termination resistance; otherwise, TS# are no function. Parity error output: Parity error found on the command and address bus. Temperature event:the EVENT# pin is asserted by the temperature sensor when critical temperature thresholds have been exceeded. V DD Supply Power supply:.5v ±0.075V. The component V DD and V D are connected to the module V DD. V DDSPD Supply Temperature sensor/spd EEPROM power supply: 3.0 3.6V. V REFCA Supply Reference voltage: Control, command, and address V DD /. V REF Supply Reference voltage:, DM V DD /. Supply Ground. V TT Supply Termination voltage: Used for control, command, and address V DD /. NC No connect: These pins are not connected on the module. NF No function: These pins are connected within the module, but provide no functionality. jsf8c56_5x7az.pdf Rev. C 3/ EN 5 009 Micron Technology, Inc. All rights reserved.
GB, 4GB (x7, ECC, DR) 40-Pin DDR3 UDIMM Map Map Table 7: Component-to-Module Map Component Reference Number Component Module Module Pin Number Component Reference Number Component Module Module Pin Number U 0 9 U 0 0 8 5 3 3 3 7 9 5 38 3 0 3 3 8 4 6 8 4 4 37 5 4 5 3 6 3 0 6 9 7 4 7 9 3 U3 0 8 7 U4 0 6 36 4 9 50 3 47 3 56 3 6 3 4 30 4 46 4 30 55 5 0 40 5 8 49 6 9 8 6 7 37 7 7 7 5 3 U5 0 CB 45 U6 0 34 87 CB5 59 37 0 CB7 65 39 07 3 CB0 39 3 33 8 4 CB6 64 4 38 06 5 CB4 58 5 36 00 6 CB3 46 6 35 88 7 CB 40 7 3 8 U7 0 4 96 U8 0 50 05 45 0 53 9 47 6 55 5 3 4 9 3 49 00 4 46 5 4 54 4 5 44 09 5 5 8 6 43 97 6 5 06 7 40 90 7 48 99 U9 0 58 4 U 0 6 8 6 8 58 4 63 34 57 09 3 57 09 3 63 34 4 6 33 4 56 08 5 60 7 5 59 5 6 59 5 6 60 7 7 56 08 7 6 33 jsf8c56_5x7az.pdf Rev. C 3/ EN 6 009 Micron Technology, Inc. All rights reserved.
GB, 4GB (x7, ECC, DR) 40-Pin DDR3 UDIMM Map Table 7: Component-to-Module Map (Continued) Component Reference Number Component Module Module Pin Number Component Reference Number Component Module Module Pin Number U 0 53 9 U3 0 45 0 50 05 4 96 49 00 4 9 3 55 5 3 47 6 4 48 99 4 40 90 5 5 06 5 43 97 6 5 8 6 44 09 7 54 4 7 46 5 U4 0 37 0 U5 0 CB5 59 34 87 CB 45 33 8 CB0 39 3 39 07 3 CB7 65 4 3 8 4 CB 40 5 35 88 5 CB3 46 6 36 00 6 CB4 58 7 38 06 7 CB6 64 U6 0 9 50 U7 0 4 6 36 8 7 4 30 6 3 3 56 3 3 47 4 5 3 4 7 5 7 37 5 9 8 6 8 49 6 0 40 7 30 55 7 46 U8 0 3 3 U9 0 5 3 0 8 9 8 0 3 3 5 38 3 7 9 4 9 3 4 4 5 9 5 3 0 6 3 6 4 7 4 37 7 6 8 jsf8c56_5x7az.pdf Rev. C 3/ EN 7 009 Micron Technology, Inc. All rights reserved.
GB, 4GB (x7, ECC, DR) 40-Pin DDR3 UDIMM Functional Block Diagram Functional Block Diagram Figure : Functional Block Diagram S# S0# S0 S0# DM0 S4 S4# DM4 DM CS# S S# DM CS# S S# DM CS# S S# DM CS# S S# 0 3 4 5 6 7 U U9 3 33 34 35 36 37 38 39 U6 U4 S S# DM S5 S5# DM5 8 9 0 3 4 5 S S# DM DM CS# S S# DM CS# S S# DM CS# S S# DM CS# S S# U U8 40 4 4 43 44 45 46 47 S6 S6# DM6 U7 U3 6 7 8 9 0 3 S3 S3# DM3 DM CS# S S# DM CS# S S# DM CS# S S# DM CS# S S# U3 U7 48 49 50 5 5 53 54 55 S7 S7# DM7 U8 U 4 5 6 7 8 9 30 3 DM CS# S S# DM CS# S S# DM CS# S S# DM CS# S S# 56 57 58 U4 U6 59 U9 U 60 6 6 63 BA[:0] A[4:0] RAS# CAS# WE# CKE0 CKE ODT0 ODT RESET# S8 S8# DM8 CB0 CB CB CB3 CB4 CB5 CB6 CB7 DM CS# S S# U5 BA[:0]: DDR3 SDRAM V DDSPD A[4:0]: DDR3 SDRAM RAS#: DDR3 SDRAM V DD CAS#: DDR3 SDRAM V TT WE#: DDR3 SDRAM CKE0: Rank 0 V REFCA CKE: Rank ODT0: Rank 0 V REF ODT: Rank RESET#: DDR3 SDRAM DM CS# S S# U5 Temperature sensor/spd EEPROM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM SCL Rank 0: U U9 Rank : U U9 U0 Temperature sensor/ SPD EEPROM EVT A0 A A SA0 SA EVENT# SA Control, command, and address termination SDA CK0 CK0# CK CK# Rank 0 Clock, control, command, and address line terminations: CKE[:0], A[4/3:0], RAS#, CAS#, WE#, ODT[:0], BA[:0], S#[:0] DDR3 SDRAM DDR3 SDRAM V TT Rank CK CK# V DD Note:. The ball on each DDR3 component is connected to an external 40Ω ±% resistor that is tied to ground. It is used for the calibration of the component s ODT and output driver. jsf8c56_5x7az.pdf Rev. C 3/ EN 8 009 Micron Technology, Inc. All rights reserved.
General Description GB, 4GB (x7, ECC, DR) 40-Pin DDR3 UDIMM General Description DDR3 SDRAM modules are high-speed, CMOS dynamic random access memory modules that use internally configured 8-bank DDR3 SDRAM devices. DDR3 SDRAM modules use DDR architecture to achieve high-speed operation. DDR3 architecture is essentially a 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the DDR3 SDRAM module effectively consists of a single 8n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins. DDR3 modules use two sets of differential signals: S, S# to capture data and CK and CK# to capture commands, addresses, and control signals. Differential clocks and data strobes ensure exceptional noise immunity for these signals and provide precise crossing points to capture input signals. Fly-By Topology DDR3 modules use faster clock speeds than earlier DDR technologies, making signal quality more important than ever. For improved signal quality, the clock, control, command, and address buses have been routed in a fly-by topology, where each clock, control, command, and address pin on each DRAM is connected to a single trace and terminated (rather than a tree structure, where the termination is off the module near the connector). Inherent to fly-by topology, the timing skew between the clock and S signals can be easily accounted for by using the write-leveling feature of DDR3. Temperature Sensor with Serial Presence-Detect EEPROM Thermal Sensor Operations The temperature from the integrated thermal sensor is monitored and converts into a digital word via the I C bus. System designers can use the user-programmable registers to create a custom temperature-sensing solution based on system requirements. Programming and configuration details comply with JEDEC standard No. -C page 4.7-, "Definition of the TSE00av, Serial Presence Detect with Temperature Sensor." Serial Presence-Detect EEPROM Operation DDR3 SDRAM modules incorporate serial presence-detect. The SPD data is stored in a 56-byte EEPROM. The first 8 bytes are programmed by Micron to comply with JE- DEC standard JC-45, "Appendix X: Serial Presence Detect (SPD) for DDR3 SDRAM Modules." These bytes identify module-specific timing parameters, configuration information, and physical attributes. The remaining 8 bytes of storage are available for use by the customer. System READ/WRITE operations between the master (system logic) and the slave EEPROM device occur via a standard I C bus using the DIMM s SCL (clock) SDA (data), and SA (address) pins. Write protect (WP) is connected to, permanently disabling hardware write protection. For further information refer to Micron technical note TN-04-4, "Memory Module Serial Presence-Detect." jsf8c56_5x7az.pdf Rev. C 3/ EN 9 009 Micron Technology, Inc. All rights reserved.
Electrical Specifications Table 8: Absolute Maximum Ratings GB, 4GB (x7, ECC, DR) 40-Pin DDR3 UDIMM Electrical Specifications Stresses greater than those listed may cause permanent damage to the module. This is a stress rating only, and functional operation of the module at these or any other conditions outside those indicated in each device's data sheet is not implied. Exposure to absolute maximum rating conditions for extended periods may adversely affect reliability. Symbol Parameter Min Max Units V DD V DD supply voltage relative to 0.4.975 V V IN, V OUT Voltage on any pin relative to 0.4.975 V Table 9: Operating Conditions Symbol Parameter Min Nom Max Units Notes V DD V DD supply voltage.45.5.575 V I VTT Termination reference current from V TT 600 600 ma V TT I I I OZ Termination reference voltage (DC) command/address bus Input leakage current; Any input 0V V IN V DD ; V REF input 0V V IN 0.95V (All other pins not under test = 0V) Output leakage current; 0V V OUT V D ; and ODT are disabled; ODT is HIGH Address inputs, RAS#, CAS#, WE#, BA S#, CKE, ODT, CK, CK# 0.49 V DD - 0mV 0.5 V DD 0.5 V DD + 0mV V 36 0 36 µa 8 0 8 DM 4 0 4, S, S# I VREF V REF supply leakage current; V REF = V DD / or V REFCA = V DD / (All other pins not under test = 0V) T A T C Module ambient operating temperature 0 0 0 µa 8 0 8 µa Commercial 0 70 C, 3 Industrial 40 85 C DDR3 SDRAM component Commercial 0 95 C, 3, 4 case operating temperature Industrial 40 95 C Notes:. V TT termination voltage in excess of the stated limit will adversely affect the command and address signals voltage margin and will reduce timing margins.. T A and T C are simultaneous requirements. 3. For further information, refer to technical note TN-00-08: Thermal Applications, available on Micron s Web site. 4. The refresh rate is required to double when 85 C < T C 95 C. jsf8c56_5x7az.pdf Rev. C 3/ EN 0 009 Micron Technology, Inc. All rights reserved.
GB, 4GB (x7, ECC, DR) 40-Pin DDR3 UDIMM DRAM Operating Conditions DRAM Operating Conditions Recommended AC operating conditions are given in the DDR3 component data sheets. Component specifications are available on Micron s Web site. Module speed grades correlate with component speed grades, as shown below. Table 0: Module and Component Speed Grades DDR3 components may exceed the listed module speed grades; module may not be available in all listed speed grades Module Speed Grade Component Speed Grade -G9-07 -G6-5 -G4-5E -G -87E -G0-87 -80C -5E -80B -5 Design Considerations Simulations Micron memory modules are designed to optimize signal integrity through carefully designed terminations, controlled board impedances, routing topologies, trace length matching, and decoupling. However, good signal integrity starts at the system level. Micron encourages designers to simulate the signal characteristics of the system's memory bus to ensure adequate signal integrity of the entire memory system. Power Operating voltages are specified at the DRAM, not at the edge connector of the module. Designers must account for any system voltage drops at anticipated power levels to ensure the required supply voltage is maintained. jsf8c56_5x7az.pdf Rev. C 3/ EN 009 Micron Technology, Inc. All rights reserved.
GB, 4GB (x7, ECC, DR) 40-Pin DDR3 UDIMM I DD Specifications I DD Specifications Table : DDR3 I DD Specifications and Conditions GB Values are for the MT4J8M8 DDR3 SDRAM only and are computed from values specified in the Gb (8 Meg x 8) component data sheet Parameter Symbol 600 333 066 Units Operating current 0: One bank ACTIVATE-to-PRECHARGE I DD0 88 098 008 ma Operating current : One bank ACTIVATE-to-READ-to-PRECHARGE I DD 368 78 88 ma Precharge power-down current: Slow exit I DDP0 6 6 6 ma Precharge power-down current: Fast exit I DDP 80 70 630 ma Precharge quiet standby current I DDQ 06 080 954 ma Precharge standby current I DDN 60 70 990 ma Precharge standby ODT current I DDNT 963 873 783 ma Active power-down current I DD3P 80 70 630 ma Active standby current I DD3N 06 6 06 ma Burst read operating current I DD4R 358 908 548 ma Burst write operating current I DD4W 358 088 88 ma Refresh current I DD5B 4680 430 3960 ma Self refresh temperature current: MAX T C = 85 C I DD6 08 08 08 ma Self refresh temperature current (SRT-enabled): MAX T C = 95 C I DD6ET 6 6 6 ma All banks interleaved read current I DD7 5508 458 368 ma Reset current I DD8 5 5 5 ma Notes:. One module rank in the active I DD ; the other rank in I DDP0 (slow exit).. All ranks in this I DD condition. jsf8c56_5x7az.pdf Rev. C 3/ EN 009 Micron Technology, Inc. All rights reserved.
GB, 4GB (x7, ECC, DR) 40-Pin DDR3 UDIMM I DD Specifications Table : DDR3 I DD Specifications and Conditions 4GB Values are for the MT4J56M8 DDR3 SDRAM only and are computed from values specified in the Gb (56 Meg x 8) component data sheet Parameter Symbol 333 066 Units Operating current 0: One bank ACTIVATE-to-PRECHARGE I DD0 98 88 ma Operating current : One bank ACTIVATE-to-READ-to-PRECHARGE I DD 43 008 ma Precharge power-down current: Slow exit I DDP0 6 6 ma Precharge power-down current: Fast exit I DDP 630 540 ma Precharge quiet standby current I DDQ 70 990 ma Precharge standby current I DDN 70 990 ma Precharge standby ODT current I DDNT 873 783 ma Active power-down current I DD3P 80 70 ma Active standby current I DD3N 350 080 ma Burst read operating current I DD4R 908 548 ma Burst write operating current I DD4W 68 908 ma Refresh current I DD5B 4590 440 ma Self refresh temperature current: MAX T C = 85 C I DD6 6 6 ma Self refresh temperature current (SRT-enabled): MAX T C = 95 C I DD6ET 6 6 ma All banks interleaved read current I DD7 3393 988 ma Reset current I DD8 5 5 ma Notes:. One module rank in the active I DD ; the other rank in I DDP0 (slow exit).. All ranks in this I DD condition. jsf8c56_5x7az.pdf Rev. C 3/ EN 3 009 Micron Technology, Inc. All rights reserved.
Temperature Sensor with Serial Presence-Detect EEPROM Serial Presence-Detect GB, 4GB (x7, ECC, DR) 40-Pin DDR3 UDIMM Temperature Sensor with Serial Presence-Detect EEPROM The temperature sensor continuously monitors the module's temperature and can be read back at any time over the I C bus shared with the SPD EEPROM. For the latest SPD data, refer to Micron's SPD page: www.micron.com/spd. Table 3: Temperature Sensor with SPD EEPROM Operating Conditions Parameter/Condition Symbol Min Max Units Supply voltage V DDSPD 3.0 3.6 V Supply current: V DD = 3.3V I DD.0 ma Input high voltage: Logic ; SCL, SDA V IH.45 V DDSPD + V Input low voltage: Logic 0; SCL, SDA V IL 0.55 V Output low voltage: I OUT =.ma V OL 0.4 V Input current I IN 5.0 5.0 µa Temperature sensing range 40 5 C Temperature sensor accuracy (class B).0.0 C Table 4: Temperature Sensor and EEPROM Serial Interface Timing Parameter/Condition Symbol Min Max Units Time bus must be free before a new transition can start t BUF 4.7 µs SDA fall time t F 0 300 ns SDA rise time t R 000 ns Data hold time t HD:DAT 00 900 ns Start condition hold time t H:STA 4.0 µs Clock HIGH period t HIGH 4.0 50 µs Clock LOW period t LOW 4.7 µs SCL clock frequency t SCL 0 00 khz Data setup time t SU:DAT 50 ns Start condition setup time t SU:STA 4.7 µs Stop condition setup time t SU:STO 4.0 µs jsf8c56_5x7az.pdf Rev. C 3/ EN 4 009 Micron Technology, Inc. All rights reserved.
GB, 4GB (x7, ECC, DR) 40-Pin DDR3 UDIMM Temperature Sensor with Serial Presence-Detect EEPROM EVENT# Pin The temperature sensor also adds the EVENT# pin (open-drain). Not used by the SPD EEPROM, EVENT# is a temperature sensor output used to flag critical events that can be set up in the sensor s configuration register. EVENT# has three defined modes of operation: interrupt mode, compare mode, and critical temperature mode. Event thresholds are programmed in the 0x0 register using a hysteresis. The alarm window provides a comparison window, with upper and lower limits set in the alarm upper boundary register and the alarm lower boundary register, respectively. When the alarm window is enabled, EVENT# will trigger whenever the temperature is outside the MIN or MAX values set by the user. The interrupt mode enables software to reset EVENT# after a critical temperature threshold has been detected. Threshold points are set in the configuration register by the user. This mode triggers the critical temperature limit and both the MIN and MAX of the temperature window. The compare mode is similar to the interrupt mode, except EVENT# cannot be reset by the user and returns to the logic HIGH state only when the temperature falls below the programmed thresholds. Critical temperature mode triggers EVENT# only when the temperature has exceeded the programmed critical trip point. When the critical trip point has been reached, the temperature sensor goes into comparator mode, and the critical EVENT# cannot be cleared through software. jsf8c56_5x7az.pdf Rev. C 3/ EN 5 009 Micron Technology, Inc. All rights reserved.
GB, 4GB (x7, ECC, DR) 40-Pin DDR3 UDIMM Module Dimensions Module Dimensions Figure 3: 40-Pin DDR3 UDIMM Front view 33.50 (5.56) 33.0 (5.44) 4.0 (0.57) MAX 0.9 (0.035) 0.50 (0.0) R (4X) 0.75 (0.03) R (8X).50 (0.098) D (X) U U U3 U4 U5 U0 U6 U7 U8 U9 7.3 (0.68) 3.3 (0.9) 30.50 (.0) 9.85 (.75).30 (0.09).0 (0.087).45 (0.057) Pin 54.68 (.5) 0.76 (0.030) R.0 (0.039) 0.80 (0.03) 9.5 (0.374) Pin 0.37 (0.054).7 (0.046) 5.0 (0.59) (4X) 3.0 (4.84) Back view.0 (0.039) R (8X) 5. (0.) 3. (0.) X U U U3 U4 U5 U6 U7 U8 U9 3.0 (0.8) 4X 3.05 (0.) Pin 40 Pin 5.0 (0.97) 7.0 (.79) 47.0 (.85) Notes:. All dimensions are in millimeters (inches); MAX/MIN or typical () where noted.. The dimensional diagram is for reference only. 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 08-368-3900 www.micron.com/productsupport Customer Comment Line: 800-93-499 Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. jsf8c56_5x7az.pdf Rev. C 3/ EN 6 009 Micron Technology, Inc. All rights reserved.