SMART TECHNOLOGY CHOICES AND LEADERSHIP I.MX APPLICATIONS PROCESSORS RONALD MARTINO FD SOI FORUM 13 APRIL 2016
Smart World Secure, Connected, Low-Power, Scalable Internet of Things Smart Hospitals Smart Homes Smart Energy Smart Highways Software Ease-of-use Open-source Security Device Management Professional Services Smart Industrial Connected Cars Solutions Embedded Processing Connectivity Protocols Multi-Sensing Applications Video Image Graphics Voice Connected World Smart Homes Smart Cities Technology Innovations Advanced NVM, RF, Mixed Signal Analog, and Sensors integration Powerful, Secure, Low-Power MCUs & Application Processors System Miniaturization & Advanced Packaging 1
Driving Explosive Growth in Smart Vehicles & Smart Devices 2010 My Ford Touch Introduction Powered by 2012 ereader Inventory Correction Over 200M SOCs shipped to date Over 35M vehicles enabled with since 2007 Leader in ereaders and Auto Infotainment MPU 2007 2008 2009 2010 2011 2012 2013 2014 2015 Auto 2
6 Series: Supreme Scalability and Flexibility Leverage One Design into Diverse Product Portfolio Scalable series of NINE ARM-based SoC Families 6UltraLite 6UltraLite 6SoloLite 6SoloLite 6SoloX 6SoloX 6Solo 6DualLite 6Dual 6DualPlus 6Quad 6Solo 6DualLite 6Dual 6DualPlus 6Quad 6QuadPlus 6QuadPlus 6UltraLite 6SoloLite 6SoloX 6Solo 6DualLite 6Dual 6DualPlus 6Quad 6QuadPlus Family Family Family Family Family Family Family Family Family Pin-to-pin Compatible Software Compatible Expanded series for performance, power efficiency and lower BOM 3
Recently Announced 7D & 7S Advantages Advanced Heterogeneous Architecture Single and Dual Cortex-A7 Core up to 1GHz Cortex-M4 up to 266MHz Offload Tasks Optimize Power Increase Security Cortex-A7 Cortex-A7 Bus Fabric Cortex- M4 Unmatched Power Efficiency 3x improvement in Power Efficiency vs 6 100 uw/mhz for Cortex-A7 70 uw/mhz for Cortex-M4 One third the power consumed in the Low Power suspend mode (250uW) vs 6 Enabling Flexible High Speed Connectivity PCI-e v2.1 Dual Gbit Ethernet with AVB DDR QuadSPI support emmc 5.0 Complete Security Infrastructure Secure Boot Crypto H/W Acceleration Internal and External Tamper Detection Secure RAM DPA attack Resistance Secure JTAG 4
Active Power ( mw/mhz ) Processing Power Efficiency 2 Core-only 1.6 1.2 0.8 0.4 28nm for MPU & MCU 0 2010 2012 2014 2016 2017 2018 ARM Cortex -M0+ ARM Cortex-M4 ARM Cortex-A9/Ax 5
Processor Roadmap Two New Platforms Based on 28nm FD SOI Technology 6QuadPlus 6Quad 6DualPlus 6Dual 6DualLite 6Solo 6SoloX 6SoloLite 8 series Advanced Graphics & Performance ARM v8-a 7 series Power Efficiency ARM v7-a 6UltraLite ARM v7-a 6
Miniaturization Increasing Integration of Diverse Components Diversification Precision Analog RF HV NVM Sensors Biochips 180nm 130nm 90nm 65nm Sense, Acquisition & Connectivity Functionality 40nm 28nm 14nm... Computational & Graphics Functionality Leading-edge process nodes (45, 32 14FF) driven mainly by digital SoC Longer-lasting shrink nodes (40, 28??) offer mixed-signal integration opportunity 7
End Nodes of TOMORROW Low-power Core Analog NVM High- Performance Core Wide-band RF Sensors (MEMS) Narrow-band RF Analog Optics (Camera) Antennas Energy Sources Power Management (PMIC/PMU) Complete Integration Scaled and all-in-one small, thin form factor package 8
Moore s Law No Exponential is Forever but Forever can be Delayed 10 mm Recent scaling and performance improvements driven by unprecedented technical innovation on silicon 1 mm Cu Metallization (220nm) Immersion Lithography (45/40nm) High k / Metal Gate (32/28nm) 100 nm FinFET (22/16/14nm) 10 nm Low-k ILD (130/90nm) Strained Si (90/65nm) 1 nm 1970 1980 1990 2000 2010 2020 FD-SOI (28/22nm) (from STMicroelectronics) (from TSMC) 9
Analog Feature / Performance Differentiation NXP Process Development Strategy SmartMOS Power & Analog e-non Volatile Memory CMOS Platform-Based Technologies: Leverage foundry standard technology Adapt for targeted applications Sensors Packaging High Performance SOI RF CMOS Degree of Partnering CMOS Differentiating Technologies: Focus on performance/features High re-use >80% of the technology platform Wholly-owned intellectual property envm CMOS Platform UHV RF 10
Smart Technology Choices 1 Which node? 2 Which process architecture? 11
28nm Last Simple Node? 11 50% INCREASE in COST Wafer Cost normalized to 0.25um cost 6.0 1.0.18um.13um 90nm 65nm 40nm 28nm (High-K Metal Gate) 14/16nm (FinFET) 40nm to 28nm will be significant % of worldwide capacity in 2020 12
Die Cost 16FF/28FD Cost Vs. Performance 160% 150% 140% Die Cost Comparison: 16FF vs 28FD Relative Wafer Price 150% 175% 200% 130% 120% 110% 100% 90% 80% 0.00 25.00 50.00 75.00 100.00 125.00 150.00 Die Size Processors Large range of die size Larger amount of analog Pads and overhead not scaling Future RF integration 13
Soft Error Rate (FITs/Mb) Soft Error Rate (FITs/Mb) NXP History Leveraging SOI 4500 4000 3500 Alpha SER Neutron SER 4500 4000 3500 Alpha SER Neutron SER 3000 3000 2500 2500 2000 2000 1500 1500 1000 1000 500 500 0 0 130nm (B) 90nm 65nm 130nmSOI 90nmSOI 45nmSOI NXP has developed 20+ processors over 3 generations of SOI technology Soft Error Rate (SER) is becoming an increasingly significant factor as SoC memory arrays continue to increase in size & density Bulk technology performs successively worse with each technology node SOI provides 5 ~ 10x better SER reliability and the gap is widening as geometries shrink 28 FD SOI benefits extend to 10-100X better immunity 14
SER Comparison Technology Intrinsic (Technology) SER Product-Level SER 28nm Bulk Si Moderate Design techniques / protection 28nm FD-SOI Low Protection techniques depend on amount of memory and logic content 14/16nm FinFET Low Protection techniques depend on amount of memory and logic content 15
FD SOI Advantages 1 2 3 Power-Performance Benefits Low Vdd with Performance Improved Electrostatics Scalable Platform Analog & RF Characteristics Better Gain, Matching, Noise Gate 1st Integration Lower Risk Manufacturing Simple Integration / Fast TAT Extends 28nm install base Low complexity planar device 16
Leakage FOM 28nm FD-SOI Platform Logic Gate Leakage/Performance Metric T=25C Vdd=0.8V, 1.1V Back-bias enables large dynamic operating range Forward Back Bias Good power-performance at low voltages, temperatures (IOT standby mode) Reverse Back Bias Frequency FOM Each point represents simulated average over three X1 library cells from a unique Vt-L combination. Ignores interconnect impact, which is highly implementation dependent 17
Process Technology Implications 28nm & Beyond High-K Metal Gate FD-SOI FinFET Energy Efficiency Cost Competitiveness Ease of Design Ease of Diversification Multi-Cores Power Management Performance Security / ARM TrustZone Memory Secure Java / OS support Connectivity S/W stack Non-volatile Memory Program Complexity Data Collection RF Connectivity Wireless Everywhere 18
FD SOI Gaps Addressed by NXP 1 2 3 Utilizing Full Range of Back-Gate Biasing Extended Bias Range BEOL TDDB Rules Enhanced Voltage Management Expanding Richness of Design Collateral DDK Enhancements RAM Compiler Enhancements IO Enhancements Enabling Auto Quality and Analog IP Unique Design Rules & Verification Supporting Multiple IP Vendors Auto Aging Use Case 19
Single A53 @ >1.2 GHz Lower Power & Smaller Area Leveraging Bias Range Scalable Performance Subsystem Attributes 28 FD SOI Alternative 28nm Leakage (Typical / WC) 70 / 175mA 125 / 315mA Normalized dynamic power 0.75 1.0 Area 1.3 sqmm 1.7 sqmm 20
8 Coming Soon Leveraging superset design ARM V8-A 64 bit architecture 10+ core complex Cortex-A72, Cortex-A53 Enhanced graphics Leadership 4k video Integrated vision Low power 4k multi-display Mixed signal Rich connectivity Compelling auto features Mixed Signal Logic DDR Display Ctrl Connectivity Multimedia ss_imaging 28nm Technology Positioning FD SOI for leadership in broad market application processors MIPI_CSI SCU DB Imagin Digital Logic Audio g Core Complex (A53/A72) Mixed Signal Logic MIPI_CSI Display Ctrl DDR Mixed Signal Logic 21
Summary The evolving smart world requires a broad range of application processors I/O counts, integrated PHYs and interface speeds are increasing Integration of functions in a cost effective technology is required for success 28 FD SOI offers advantages that allows scaling from small power efficient processors to high performance safety critical processors NXP s broad product portfolio and technology adoption strategy enables cost-effective ground-breaking solutions Future roadmap for will leverage 14nm class devices in order to scale power-performance when market demand justifies higher cost and expense of development 22