ELEN 468 Advanced Logic Design (Spring 2001) Lab #8 Timing Analysis using PrimeTime Introduction: PrimeTime is the Synopsys stand-alone full chip, gate-level static timing analyzer. It analyzes the timing of large, synchronous, digital ASIC s. PrimeTime works with designs at the gate level, providing a tight integration with other Synopsys tools. PrimeTime has features that make it suitable for analyzing large, system-on-a-chip (SOC) designs. Primetime is synthesis-compatible, and you can use it throughout your design process. Basic Features: The following timing checks can be performed on a design Setup and hold checks Recovery and removal checks Clock pulse width checks Clock gating checks The following design checks can be preformed with the help of PrimeTime Unclocked registers Unconstrained timing endpoints Master-Slave clock separation Multiple clocked registers Level-sensitive clocking Combinational feedback loops Design rule checks on maximum capacitance, transition time and fanout. Timing Analysis Flow and Methodology 1. setup the design environment - set the search path and the link path - read the design and the libraries - link the top design - set up the operating conditions, wireload models, port load, drive and transition time
2. Specify the timing assertions - define the clock period, waveform, uncertainty and latency - specify the input and output port delays 3. Specify the timing exceptions - set multicycle paths - set false paths - specify minimum and maximum delays, path segmentation and disabled arcs 4. Perform the analysis and create reports - Check timing - Generate constraint reports - Generate path timing reports Setup Information PrimeTime is capable of reading industry standard file formats including vhdl, verilog, EDIF and SDF. PrimeTime requires.synopsys_pt.setup file to be able to run. Make a new directory under tutorial, and create a.synopsys_pt.setup file in it. The file should contain the following:. synopsys_pt.setup set search_path ". /jumbo/synopsys/2000.5/libraries/syn" set link_path "* class.db" set sh_enable_page_mode true The variable search_path defines a list of directories to look into while searching for libraries and designs. The variable link_path defines a list of libraries containing cells to be used for linking the design. These libraries are searched in the directories specified in the search_path. By setting the sh_enable_page_mode as true, the output is paged each time you use Primetime. PrimeTime handles the following input files... Design files - in vhdl, db, verilog or in any industry standard file formats Technology library - in db format Timing model scripts -.pt formats Stamp data and models -.data and.mod files
Starting PrimeTime: Change to the new directory created above and type Primetime &. This opens the PrimeTime tool. At the bottom of the window, there is a small box (called the pt_shell) where you type all the commands. Getting Help: To get a basic summary of all the PrimeTime commands, enter Primetime> help Use the help verbose command to get command syntax information. Enter Primetime> help verbose <command > Use the man pages for detailed help for each command and variable. To access the man pages, enter man followed by the name of the command or variable. Reading the design: PrimeTime works on gate-level netlist files in any of the following formats: - Synopsys database files (.db) - Verilog netlist files - Electronic Data Interchange Format (EDIF) netlist files - VHDL netlist files So the verilog code has to be synthesized to gate-level netlist before using PrimeTime on the design. To generate the gate-level netlist file: 1. Open the design_analyzer & window. 2. Analyze & Elaborate the design. 3. The design has to be optimized using the tools->design optimization menu. 4. At the end of optimization, select the top module (in the hierarchy) and save the file. For reading the design, enter Primetime> read_verilog flip_flop. This command will read in the module flip_flop.
Linking the Design: The link process resolves the design references and connects the designs and components from the library. Primetime> link_design flip_flop This command will link all the libraries and designs linked to the design flip_flop. Performing Timing Analysis: 1. Setting up Operating conditions, wire models and drive and transition time Primetime> set_operating_conditions -library pt_lib -min BCCOM -max WCCOM Primetime> set_wire_load_mode top Primetime> set_wire_load_model -library pt_lib -name 05x05 -min Primetime> set_wire_load_model -library pt_lib -name 20x20 -max The above set of commands set up the operating conditions and wire models by linking to already existing models. PrimeTime uses - Maximum operating conditions and wire load model when it generates setup timing reports. - Minimum operating conditions and wire load model when it generates hold timing reports. 2. Setting Up the Basic Timing Assertions The following set of commands define the clock period, skew and latency (insertion delay) Primetime> create_clock -period 30 [get_ports CLOCK] Primetime> set clock [get_clock CLOCK] Primetime> set_clock_uncertainty 0.5 $clock Primetime> set_clock_latency -min 3.5 $clock Primetime> set_clock_latency -max 5.5 $clock for setting transition times Primetime> set_clock_transition -min 0.25 $clock Primetime> set_clock_transition -max 0.3 $clock The clock gating setup and hold values and a minimum pulse width are defined Primetime> set_clock_gating_check -setup 0.5 -hold 0.1 $clock Primetime> set_min_pulse_width 2.0 $clock
You can do all of the above-mentioned tasks by writing them all in a single script file. The file contains commands to read & link the design, setting up the various conditions. The file should have an extension.st, which is a TCL file. The file can be executed by typing Primetime> source flip_flop.st Where flip_flop.st is the file containing the various commands. After the execution, Primetime tells you if the file has been properly read and linked. The things to keep in mind when writing this script file is: - read_design: contains the design s gate-level netlist file - current_design: contains the design module name - link_design: contains the design module name. Running Basic Analysis: Constraint and timing reports are generated with the help of - report_constraint - report_timing commands. The report_constraint command reports the timing violations and constraints violations, whereas the report_timing command provides path-based timing reports. Reports: The following commands are used to generate basic reports - Primetime> report_design The report_design command shows the min-max operating condition and wire load models. - Primetime> report_reference The report_reference command shows each block and its area. More important, it identifies the extracted, Stamp, and quick timing models.
Example: The following example shows how to generate the timing analysis for a D-flipflop. 1) Write the Behavioral or structural code for D-flipflop (flipflop.v): module flip_flop(q,data_in,clk,rst); input data_in,clk,rst; output q; reg q; always @(posedge clk) begin if(rst==1) q=0; else q = data_in; end endmodule 2) Analyze and Elaborate the design using design_analyzer. 3) Optimize the design. Save the top model (in the hierarchy) as a verilog file. 4) Write a script file (flipflop_st.v) which contains the commands to read & link the design and setting the various conditions like operating environment, wire load, input drive strength etc.
#************************************************** #Define top design read_verilog "flipflop.v" current_design flip_flop link_design flip_flop #************************************************** #Design environment set_operating_conditions -library {class} -analysis_type single WCCOM set _wire_load_mode top set_driving_cell -lib_cell IBUF1 -library class [ all_inputs ] #************************************************** #************************************************* #Clock specification and design constraints create_clock -period 1.00000 -waveform {0.000000 0.50000} {clk} #set_propagated_clock [get_clocks clk] #set_clock_uncertainty 0.5 -setup [get_clocks clk] #************************************************ #Timing analysis commands #report_constraint -all_violators #report_timing -to [all_registers -data_pins] #report_timing -delay_type min_max -to comp1/u10/a #report_timing -delay_type min_max -to comp1/u10/b - Define top design defines the file to be read and linked. - Design Environment sets the operating conditions, wire load etc.. - Clock specification defines the clock period. - # indicate comments.
5) Execute the file by typing: Primetime> source flipflop_st.v 6) Write another script file (test.st), which does the timing analysis. set slack 0 foreach_selection cell [all_registers] { set cellname [get_attribute $cell full_name] } foreach_selection spin [get_pins "$cellname/*"] { set pinname [get_attribute $spin full_name -quiet] set curpath [get_timing_paths -delay_type max -to $pinname] set slack [get_attribute $curpath slack] if {$slack < 0} { report_timing -delay_type max -to $spin } } This file identifies the various pins where the timing is not met. Run this script by typing Primetime> source test.st Primetime identifies the pins where the timing conditions are not met. It prints out the pins where the slack (difference between the data required and arrival time) is negative and timing condition is violated. 7) Go back to the flipflop_st.v file and change the clock period to 3, also changing the waveform as {0.00000 1.50000}. 8) Execute the script and you will notice that all the conditions are met. 9) The basic idea is to identify the minimum clock period, which satisfies the timing conditions. 10) Get constraint report and evaluate the violations. Enter Primetime> report_constraint all_violations
Lab assignment: 1. Try the example given above and get an idea of using Primetime. 2. Use the verilog code for MIPS processor and generate the timing results for the design. You will identify the clock period, which satisfies the timing conditions. The clock period is in ns, and so finding the inverse of the clock period will give the frequency you processor operates. Generate waveforms using signalscan in Synopsys: Include these lines in.cshrc file: setenv CDS_INST_DIR /jumbo/cadence/ic443/tools/ldv source /usr/local/bin/setup.signalscan And in the stimulus file of your design, include these statements initial begin $shm_open(); $shm_probe("ac"); end