High Speed Communication Circuits and Systems Lecture 9 Low Noise Amplifiers

Narrowband LNA Design for Wireless Systems From Antenna and Bandpass Filter PC board trace Z o Package Interface Z in LNA To Mixer Design Issues - Noise Figure impacts receiver sensitivity - Linearity (IIP3) impacts receiver blocking performance - Gain high gain reduces impact of noise from components that follow the LNA (such as the mixer) - Power match want Z in = Z o (usually = 50 Ohms) - Power want low power dissipation - Bandwidth need to pass the entire RF band for the intended radio application (i.e., all of the relevant channels) - Sensitivity to process/temp variations need to make it manufacturable in high volume 2

Our Focus in This Lecture From Antenna and Bandpass Filter PC board trace Z o Package Interface Z in LNA To Mixer Designing for low Noise Figure Achieving a good power match Hints at getting good IIP3 Impact of power dissipation on design Tradeoff in gain versus bandwidth 3

Our Focus: Inductor Degenerated Amp Source i nout e ns L g Z gs v gs C gs g m v gs i ndg Source I out L deg L g M 1 v in L deg V bias Same as amp in Lecture 7 except for inductor degeneration - Note that noise analysis in Tom Lee s book does not include inductor degeneration (i.e., Table 11.1) 4

Recall Small Signal Model for Noise Calculations G I out D S Z g G Z gs v gs C gs i out g m v gs D i ndg Z g Z deg S Z deg 5

Key Assumption: Design for Power Match Z in L g I out M 1 v in L deg V bias Input impedance (from Lec 6) Real! Set to achieve pure resistance = at frequency w o 6

Process and Topology Parameters for Noise Calculation Source i nout e ns L g Z gs v gs C gs g m v gs i ndg L deg Process parameters - For 0.18 CMOS, we will assume the following Circuit topology parameters Z g and Z deg 7

Calculation of Z gs Source i nout e ns L g Z gs v gs C gs g m v gs i ndg L deg 8

Calculation of Source i nout e ns L g Z gs v gs C gs g m v gs i ndg L deg = 9

Calculation of Z gsw By definition Calculation 10

Calculation of Output Current Noise Step 3: Plug in values to noise expression for i ndg 11

Compare Noise With and Without Inductor Degeneration Source i nout e ns L g Z gs v gs C gs g m v gs i ndg L deg From Lecture 7, we derived for L deg = 0, w o2 = 1/(L g C gs ) We now have for (g m /C gs )L deg =, w o2 = 1/((L g + L deg )C gs ) 12

Derive Noise Factor for Inductor Degenerated Amp Source i nout e ns L g Z gs v gs C gs g m v gs i ndg L deg Recall the alternate expression for Noise Factor derived in Lecture 8 We now know the output noise due to the transistor noise - We need to determine the output noise due to the source resistance 13

Output Noise Due to Source Resistance Source i nout e ns L g Z in Z gs v gs C gs g m v gs i ndg L deg 14

Noise Factor for Inductor Degenerated Amplifier Noise Factor scaling coefficient 15

Noise Factor Scaling Coefficient Versus Q Noise Factor Scaling Coefficient Noise Factor Scaling Coefficient Versus Q for 0.18 μ NMOS Device 7 6.5 6 5.5 5 4.5 4 3.5 3 c = -j0 c = -j0.55 c = -j1 Achievable values as a function of Q under the constraints that 1 = w o (L g +L deg )C gs g m C gs L deg = 2.5 1 1.5 2 2.5 3 3.5 4 4.5 5 Q Note: 1 Q = 2 w o C gs 16

Achievable Noise Figure in 0.18 with Power Match Suppose we desire to build a narrowband LNA with center frequency of 1.8 GHz in 0.18 CMOS (c=-j0.55) - From Hspice at V gs = 1 V with NMOS (W=1.8, L=0.18 ) measured g m =871 S, C gs = 2.9 ff - Looking at previous curve, with Q 2 we achieve a Noise Factor scaling coefficient 3.5 17

Component Values for Minimum NF with Power Match Assume = 50 Ohms, Q = 2, f o = 1.8 GHz, f t = 47.8 GHz - C gs calculated as - L deg calculated as - L g calculated as 18

Have We Chosen the Correct Bias Point? (V gs = 1V) 4.5 V gs, g m, and g do versus Current Density for 0.18μ NMOS V gs I d M 1 W L = 1.8μ 0.18μ g m and g do (milliamps/volts) and V gs (Volts) 4 3.5 3 2.5 2 1.5 1 0.5 Chosen bias point is V gs = 1 V Lower power Lower f t Lower IIP3 g do Lower g m Higher power Higher f t Higher IIP3 g do Higher g m g do V gs g m Note: IIP3 is also a function of Q 0 0 100 200 300 400 500 600 700 Current Density (microamps/micron) 19

Calculation of Bias Current for Example Design Calculate current density from previous plot Calculate W from Hspice simulation (assume L=0.18 m) - Could also compute this based on C ox value Calculate bias current - Problem: this is not low power!! 20

We Have Two Handles to Lower Power Dissipation Key formulas Lower current density, I den - Benefits - Negatives Lower W - Benefit: lower power - Negatives 21

First Step in Redesign Lower Current Density, I den 4.5 V gs, g m, and g do versus Current Density for 0.18μ NMOS V gs I d M 1 W L = 1.8μ 0.18μ g m and g do (milliamps/volts) and V gs (Volts) 4 3.5 3 2.5 2 1.5 1 0.5 New bias point is V gs = 0.8 V g do V gs g m 0 0 100 200 300 400 500 600 700 Current Density (microamps/micron) Need to verify that IIP3 still OK (once we know Q) 22

Recalculate Process Parameters Assume that the only thing that changes is g m /g do and f t - From previous graph (I den = 100 A/ m) We now need to replot the Noise Factor scaling coefficient - Also plot over a wider range of Q Noise Factor scaling coefficient 23

Update Plot of Noise Factor Scaling Coefficient Noise Factor Scaling Coefficient Versus Q for 0.18 μ NMOS Device 18 Noise Factor Scaling Coefficient 16 14 12 10 8 6 4 Achievable values as a function of Q under the constraints that 1 = w o (L g +L deg )C gs c = -j0.55 c = -j0 c = -j1 g m C gs L deg = 2 1 2 3 4 5 6 7 8 9 10 Q Note: 1 Q = 2 w o C gs 24

Second Step in Redesign Lower W Recall I bias can be related to Q as We previously chose Q = 2, let s now choose Q = 6 - Cuts power dissipation by a factor of 3! - New value of W is one third the old one 25

Power Dissipation and Noise Figure of New Design Power dissipation - At 1.8 V supply Noise Figure - f t previously calculated, get scaling coeff. from plot 26

Updated Component Values Assume = 50 Ohms, Q = 6, f o = 1.8 GHz, f t = 42.8 GHz - C gs calculated as - L deg calculated as - L g calculated as 27

Inclusion of Load (Resonant Tank) Add output load to achieve voltage gain - Note: in practice, use cascode device We re ignoring C gd in this analysis i nout R e ns L s g L L R L C L i out v out v in Z in Z gs v gs C gs g m v gs i ndg L L R L C L L deg L g I out V out M 1 v in L deg V bias 28

Calculation of Gain Assume load tank resonates at frequency w o L L R L C L v out i nout R e ns L s g i out v in Z in Z gs v gs C gs g m v gs i ndg Assume Z in = L deg 29

Setting of Gain Parameters g m and Q were set by Noise Figure and IIP3 considerations - Note that Q is of the input matching network, not the amplifier load R L is the free parameter use it to set the desired gain - Note that higher R L for a given resonant frequency and capacitive load will increase Q L (i.e., Q of the amplifier load) There is a tradeoff between amplifier bandwidth and gain - Generally set R L according to overall receiver noise and IIP3 requirements (higher gain is better for noise) Very large gain (i.e., high Q L ) is generally avoided to minimize sensitivity to process/temp variations that will shift the center frequency 30

The Issue of Package Parasitics Noise Voltage L bondwire2 Equivalent Source L ext L bondwire3 L L R L C L V out Noise Current Mixer and Other Circuits M 1 v in V bias L deg Noise Current Noise Voltage L bondwire1 Bondwire (and package) inductance causes two issues - Value of degeneration inductor is altered - Noise from other circuits couples into LNA 31

Differential LNA L L R L C L C L R L L L L g V out V out L g M 1 M 2 v in 2 L deg L deg -v in 2 V bias I bias Advantages - Value of L deg is now much better controlled - Much less sensitivity to noise from other circuits Disadvantages - Twice the power as the single-ended version - Requires differential input at the chip 32

Note: Be Generous with Substrate Contact Placement To L deg To L g To amplifer load GND Substrate Contact G S D N + N + GND Substrate Contact e nrsub e nrsub Hot electrons and other noise Having an abundance of nearby substrate contacts helps in three ways - Reduces possibility of latch up issues - Lowers ub and its associated noise Impacts LNA through backgate effect (g mb ) - Absorbs stray electrons from other circuits that will otherwise inject noise into the LNA Negative: takes up a bit extra area ub P - ub Hot electrons and other noise 33

Another CMOS LNA Topology Consider increasing g m for a given current by using both PMOS and NMOS devices - Key idea: re-use of current g m I d g m1 +g m2 I d /2 I d I d /2 (1/2)W/L M 2 g m1 +g m2 I d /2 W/L M 1 Issues M 1 (1/2)W/L - PMOS device has poorer transconductance than NMOS for a given amount of current, and f t is lower - Not completely clear there is an advantage to using this technique, but published results are good See A. Karanicolas, A 2.7 V 900-MHz CMOS LNA and Mixer, JSSC, Dec 1996 M 2 (1/2)W/L (1/2)W/L M 1 I d /2 34

Biasing for LNA Employing Current Re-Use Stage 1 Stage 2 R big1 M 4 M 2 V out1 V out2 I bias V rf Matching Network C big1 M 1 R big2 C big3 C big2 M 3 opamp V ref PMOS is biased using a current mirror NMOS current adjusted to match the PMOS current Note: not clear how the matching network is achieving a 50 Ohm match - Perhaps parasitic bondwire inductance is degenerating the PMOS or NMOS transistors? 35

Another Recent Approach Feedback from output to base of transistor provides another degree of freedom L L R L C L V out v in C bypass Q 1 L deg α α < 1 For details, check out: - Rossi, P. et. Al., A 2.5 db NF Direct-Conversion Receiver Front-End for HiperLan2/IEEE802.11a, ISSCC 2004, pp. 102-103 36

Broadband LNA Design High Speed Broadband Signal PC board trace Z o Package Interface Z in LNA Most broadband systems are not as stringent on their noise requirements as wireless counterparts Equivalent input voltage is often specified rather than a Noise Figure Typically use a resistor to achieve a broadband match to input source - We know from Lecture 8 that this will limit the noise figure to be higher than 3 db For those cases where low Noise Figure is important, are there alternative ways to achieve a broadband match? 37

Recall Noise Factor Calculation for Resistor Load Source Source e nrs e nrl v in R L v out v nout R L Total output noise Total output noise due to source Noise Factor 38

Noise Figure For Amp with Resistor in Feedback Source R f Source e nrs R f e nrf V in V ref A V out incremental ground A V nout Total output noise (assume A is large) Total output noise due to source (assume A is large) Noise Factor 39

Input Impedance For Amp with Resistor in Feedback Source R f e nrf e nrs A V nout Recall from Miller effect discussion that Z in If we choose Z in to match, then Therefore, Noise Figure lowered by being able to choose a large value for R f since 40

Example Series-Shunt Amplifier R in R out R f R L v in V bias v x M 1 R 1 v out Recall that the above amplifier was analyzed in Lecture 5 Tom Lee points out that this amplifier topology is actually used in noise figure measurement systems such as the Hewlett-Packard 8970A - It is likely to be a much higher performance transistor than a CMOS device, though 41

Recent Broadband LNA Approaches Can create broadband matching networks using LC-ladder filter design techniques CMOS example: R L L L M 3 V bias2 M 2 V out L 1 C 1 L g M 1 C p I bias v in L 2 C 2 V bias L deg See Bevilacqua et. al, An Ultra-Wideband CMOS LNA for 3.1 to 10.6 GHz Wireless Receivers, ISSC 2004, pp. 382-383 42

Recent Broadband LNA Approaches (Continued) Bipolar example: R L L L C 3 M 3 V bias2 Q 2 R 1 V out C 2 V bias3 C4 Q 1 L deg2 C 1 L 1 v in L deg V bias See Ismail et. al., A 3 to 10 GHz LNA Using a Wideband LC-ladder Matching Network, ISSCC 2004, pp. 384-385 43