CMOS Logic Circuit Design http://www.rcns.hiroshima-u.ac.jp Link( リンク ): センター教官講義ノートの下 CMOS 論理回路設計 Static and Dynamic CMOS Design Basic Considerations Important Technical Concepts Transfer (DC) Characteristic and Switching Point Transient (AC) Characteristic as well as Rise-Time, Fall-Time and Delay Time Fan-In and Fan-Out Static CMOS-Logic Conventional Complementary MOS Logic Pseudo n-mos Logic Pass-Transistor Logic Dynamic CMOS-Logic Precharge-Evaluate (PE) Logic NP Domino Logic CMOS Domino Logic Mattausch, CMOS Design, H20/4/25 1
Basic Considerations Mattausch, CMOS Design, H20/4/25 2
Meaning of Static and Dynamic CMOS Logic Logic Output (1) Noise Noise Noise Static Logic VSS (0) Dynamic Logic Time Static CMOS logic actively restores the logic output values, while dynamic CMOS logic does not. Mattausch, CMOS Design, H20/4/25 3
Advantages of Static and Dynamic CMOS Design static design - high functional reliability - easy circuit design - unlimited validity of logic outputs dynamic design - high switching speed - small area consumption - low power dissipation The most important design goals determine, whether a static or a dynamic design technology is chosen. Mattausch, CMOS Design, H20/4/25 4
Important Technical Concepts - Transfer (DC) Characteristic and Switching Point Mattausch, CMOS Design, H20/4/25 5
Transfer (DC) Characteristic (Example Inverter) Inverter Circuit Inverter Transfer Characteristic V OH = high output voltage V OL = low output voltage V IL = max. low input voltage V IH = min. high input voltage V IL -VSS = low noise margin - V IH = high noise margin The transfer characteristic of CMOS logic is analog. The region between points A and B (slope = 1) is logically invalid. Mattausch, CMOS Design, H20/4/25 6
Switching Point V SP (Example Inverter) Switching-Point Definition Switching-Point Condition I D, n MOS = I D, p MOS β n ( 2 V SP V TH, n ) 2 = β p ( 2 V SP V TH,p ) 2 V SP = β n β p V TH, n + ( V TH, p ) 1+ β n β p β p β n ; V TH, p V TH, n V SP 2 At the switching point both transistors M1 and M2 are in the saturation region and have equal conductance. Mattausch, CMOS Design, H20/4/25 7
Transfer Characteristic and Transistor-Size (Example Inverter) p- and n-mos transistor design influences the transfer characteristic Correlation between β and MOS-transistor parameters SP 2 SP 1 <<1 β = µ ε W t ox L µ n 3µ p µ = carrier mobility ε = gate-insulator permittivity t ox = gate-insulator thickness W = MOS transistor width L = MOS transistor length SP 3 >>1 β p β n W p 3W n The choice of MOS-transistor length L and width W is a major design freedom in CMOS circuit design. Mattausch, CMOS Design, H20/4/25 8
Transfer Characteristic of NAND Gates N-input NAND Gate Switching-point N-input NAND Gate SP inv,inv SP N-NAND N, N-NAND <<1 V SP = β n N m β p V TH,n + ( V TH, p ) 1+ ; m = 1~2 β n N m β p To keep the switching point of the N-input NAND gate at about /2, it is necessary to choose W n ~NW p /3. Mattausch, CMOS Design, H20/4/25 9
Transfer Characteristic of NOR Gates N-input NOR Gate Switching-point N-input NOR Gate,inv, N-OR N >>1 SP inv SP N-OR V SP = N m β n β p V TH, n + ( V TH, p ) 1+ N m β n β p ; m = 1~2 To keep the switching point of the N-input NOR gate at about /2, it is necessary to choose W p ~3NW n. Mattausch, CMOS Design, H20/4/25 10
Important Technical Concepts - Transient (AC) Characteristic as well as Rise-Time, Fall-Time and Delay Time Mattausch, CMOS Design, H20/4/25 11
Rise-, Fall- and Delay-Time of Logic Circuits Logic Gate Transient Input and Output Rise-, Fall- and Delay-Time 50% (/2) Rise-Time t r Time for a transient waveform to rise from 10% to 90% of its steady state values. Fall-Time t f Time for a transient waveform to fall from 90% to 10% of its steady state values. Delay-Time t d Time difference from the 50% transition level of the input waveform to the 50% transition level of the output waveform. Rise-, fall and delay time are the main quantities for characterizing the performance of a logic CMOS circuit. Mattausch, CMOS Design, H20/4/25 12
Simple AC Model/Equations for CMOS Logic fall time: pull-down network rise time: pull-up network VSS VSS t f = k f C L β pd,eff ; t df 1 2 t f t r = k r β pu, eff CL ; t dr 1 2 t r t d,av t dr + t df 2 ; k f and k r depend on fabrication technology (~2-4) Pull-down, pull-up network and the load capacitance C L determine the AC-performance of the CMOS logic circuit. Mattausch, CMOS Design, H20/4/25 13
Important Technical Concepts - Fan-In and Fan-Out Mattausch, CMOS Design, H20/4/25 14
Definition of Fan-In and Fan-Out for Logic Gates fan-in = m fan-out = k 1 2 3 m-1 m 1 2 3 k The fan-in of a logic gate is the number of its inputs. The fan-out of a logic gate is the number of its output connections to other gates. Mattausch, CMOS Design, H20/4/25 15
Delay-Time Effect of Fan-In (m) and Fan-Out (k) (Constant n-mos and p-mos transistor W/L-ratios, respectively) NAND-Gate NOR-Gate t df,nand = m (m t fin + k t fex ) t df,nor = m t + k t fin fex t dr,nand = m t + k t rin rex t dr,nor = m (m t rin + k t rex ) t fin and t rin are internal fall- and rise-time of a minimum sized inverter, due to its own gate and drain capacitances, respectively. t fex and t rex are external fall- and rise-time of a minimum sized inverter, due the external load of a minimum sized inverter with typical routing capacitance, respectively. The fan-in has a quadratic impact on NAND-Gate fall times as well as NOR-Gate rise times. Mattausch, CMOS Design, H20/4/25 16
Static CMOS-Logic - Conventional Complementary MOS (CMOS) Logic - Pseudo n-mos Logic - Pass-Transistor Logic Mattausch, CMOS Design, H20/4/25 17
Conventional Static CMOS Logic Conventional CMOS principle Example with fan-in equal 5 A Pull-Up Pull-Up Z = A (E + D) + (B C) (E + D) B F u (A, B,, N ) F d (A,B,,N) Pull-Down = F u (A, B,, N ) Pull-Down Z = A (B+ C) + (D E) N F d (A,B,,N) Conventional CMOS logic is static because 1 and 0 are restored by pull-up and pull-down network, respectively. Mattausch, CMOS Design, H20/4/25 18
Pseudo n-mos Logic Principle: Use only the pull-down network. Chose pull-up strength of p-mos smaller than pull-down strength of network. A Example with fan-in equal 5 B VSS F d (A,B,,N) Pull-Down Z = A (B+ C) + (D E) Pull-Down N F d (A,B,,N) VSS Advantage: Less transistors and lower input capacitance. Disadvantage: High power dissipation and low pull-up speed. Mattausch, CMOS Design, H20/4/25 19
Pass-Transistor Logic V 1 V 2 V k P 1 P 2 F P = P 1 (V 1 ) + P 2 (V 2 ) + +P k (V k ) P k Pass-Transistor Logic Gate Any logic function F P can be constructed by controlling a set of pass signals P i by another set of control signals V i. Mattausch, CMOS Design, H20/4/25 20
2-Input Pass-Transistor Gate Example Realization Table of 2-Input Gates Operation P 1 P 2 P 3 P 4 NOR(A,B) 0 0 0 1 XOR(A,B) 0 1 1 0 NAND(A,B) 0 1 1 1 AND(A,B) 1 0 0 0 OR(A,B) 1 1 1 0 Implementation with n-mos and p-mos transistors Implementation with n-mos transistors (Disadvantage: Noise-margin of high level reduced by V th,n ) The pass-transistor logic has a good implementation density, but may have slow switching speed. Mattausch, CMOS Design, H20/4/25 21
Dynamic CMOS-Logic - Precharge-Evaluate (PE) Logic - NP Domino Logic - CMOS Domino Logic Mattausch, CMOS Design, H20/4/25 22
Precharge-Evaluate (PE) Logic Principle: Use only the pull-down network. clock=0: Precharge output to 1. clock=1: Evaluate pull-down network. Example with fan-in equal 5 Z = A (B+ C) + (D E) A B N clock Pull-Down F d (A,B,,N) VSS F d (A,B,,N) Pull-Down Advantage: Low power dissipation and high speed. Disadvantage: Low reliability and difficult design. Mattausch, CMOS Design, H20/4/25 23
NP Domino Logic Alternating cascade of PE-logic with pull-up/pull-down networks. A B N Pull-Down F 1 Pull-Up F 2 Pull-Down F 3 clock clock clock VSS VSS VSS Low power and high speed, but difficult to design. Mattausch, CMOS Design, H20/4/25 24
CMOS Domino Logic Gate A B N Pull-Down F d (A,B,,N) Buffer and high level restoring elements F d (A,B,,N) clock VSS CMOS domino logic achieves a good balance of switching speed, area/power consumption and design reliability. Mattausch, CMOS Design, H20/4/25 25
CMOS Domino Logic Circuit A B Pull-Down Pull-Down Pull-Down N F d1 F d2 F d3 clock clock clock VSS VSS VSS A CMOS domino logic circuit uses only pull-down networks. Mattausch, CMOS Design, H20/4/25 26