4-1 STRUCTURE OF A FIELD-EFFECT TRANSISTOR (FET S)

4-1 STRUCTURE OF A FIELD-EFFECT TRANSISTOR (FET S) Recall that the bipolar junction transistor (BJT) is a current-controlled device; that is; the base current controls the amount of collector current. The field-effect transistor (FET) is a voltage-controlled device in which the voltage at the gate terminal controls the amount of current through the device. Both the BJT and the FET can be used as an amplifier and in switching applications In this section, you will learn the basic classifications for field-effect transistors The FET Family Field-effect transistors (FETS) are a class of semiconductors that operate on an entirely different principle than BJT s. In a FET, a narrow conducting channel is connected to two leads called the source and the drain. This channel is made from either an n-type or p-type material. As the name field-effect implies, conduction in the channel is controlled by an electric field, established by a voltage applied to a third lead called the gate. FETs are divided into two classes. In a junction FET (or JFET), the gate forms a junction with the channel. The other type of FET, called the MOSFET (for Metal Oxide Semiconductor FET), uses an insulated gate to control conduction in the channel. (The terms insulated gate and MOSFET refer to the same type of device.) The insulation is an extremely thin layer (<1 um) of glass (typically SiO 2 ). Figure 4-1 is an overview of the FET family, showing the various types. There are limited applications for depletion-mode MOSFETs (the exception is some high frequency specialized types). Of the few that are available, all are n-channel. The p-channel type is shown as generic only because you can experiment with it in simulations like Multisim. Figure 4-1 FETs are used in most computer integrated circuits (ICs) because of several important advantages they have over BJTS, particularly with respect to manufacturing of large-scale ICs. For digital circuits, MOSFETs have become the dominant type of transistor for several reasons. They can be fabricated in much smaller areas than BJTS, they are relatively easy to manufacture on ICs, and they produce simpler circuits with no resistors or diodes. Most microprocessors and computer memories use FET technology. Compared to the BJT, the FET family is more diverse. A characteristic that differs between various types of FETs is their dc behavior. Therefore, JFETs are biased differently than E-MOSFETS. Fortunately, bias circuits are fairly easy to 1 OF 10

understand. Before proceeding to bias circuits, the characteristics of the transistors that make up the FET family will be discussed. Common to all FET s is very high input resistance and low electrical noise. In addition, both JFET s and MOSFET s respond the same way to ac signals and have similar ac equivalent circuits. JFETs achieve their high input resistance because the input pn junction is always operated with reverse bias; MOSFETs achieve their high input resistance because of the insulated gate. Although all FET s have high input resistance, they do not have the high gain of bipolar junction transistors. BJT s are also inherently more linear than FETS. For certain applications, FETs are superior; for other applications, BJTs are superior. Many designs take advantage of both types and include a mix of FET s and BJT s. 4-2 JFET CHARACTERISTICS The JFET characteristic curve is divided into the ohmic region, the constant-current region and the breakdown region. It is normally operated in either the ohmic region or the constant-current region. In this section, you will learn how to interpret the characteristic curve and explain common JFET parameters. JFET Operation Figure 4-2(a) shows the basic structure of an n-channel junction field-effect transistor (JFET). Wire leads are connected to each end of the n channel; the drain is shown at the upper end, and the source is at the lower end. This channel is a conductor: for an n-channel JFET, electrons are the carrier; for a p-channel JFET, holes are the carrier. With no external voltages, the channel can conduct current in either direction. Fig. 4-2 In an n-channel device, a p material is diffused into the n-channel to form a pn junction and is connected to the gate lead. The diagram in Figure 4-2(a) shows p-material diffused into two regions that are normally connected internally by the manufacturer to form a single gate. (A special-purpose JFET, called a dual-gate JFET, has a separate lead to each of these regions.) In the structure diagrams, the interconnection of both p regions is omitted for simplicity, with a connection to only one shown. A p-channel JFET is shown in Figure 4-2(b). 2 OF 10

To illustrate JFET operation, Figure 4-3(a) shows normal operating voltages applied to an n-channel device. V DD provides a positive drain-to-source voltage, causing electrons to flow from the source to the drain. For an n-channel JFET, reversebiasing of the gate-source junction is done with a negative gate voltage. VGG sets the reverse-biased voltage between the gate and the source, as shown. Notice that there should never be any forward-biased junctions in a FET; this is one of the principal differences between FETs and BJTs. The channel width, and thus the channel resistance, is controlled by varying the gate voltage, thereby controlling the amount of drain current, I D. This concept is illustrated in Figure 4-3(b) and (c). The white areas represent the depletion region created by the reverse bias. The key idea is that the channel width is controlled by the gate voltage. JFET Symbols The schematic symbols for both n-channel and p-channel JFET s are shown in Figure 4-4. Notice that the arrow on the gate points "in" for n channel and "out for p channel. 3 OF 10

Drain Characteristic Curve Field Effect Transistors (FET) The drain characteristic curve is a plot of the drain current, I D, versus the drain-to-source voltage, VDs, which corresponds to a BJT's collector current, Ic, versus collector-to- emitter voltage, V CE. There are, however, some significant differences between BJT characteristics and FET characteristics. Since the FET is a voltage-controlled device, the third variable on the FET characteristic (V RS ) has units of gate voltage instead of base current (IB) in the case of the BJT. The characteristics for n-channel devices are introduced in this section. P-channel devices operate in the same way but with opposite polarities. Generally, n-channel JFETs have better specifications than their p-channel counterparts, so they are more popular. Consider an n-channel JFET where the gate-to-source voltage is zero (V QS 0 V). This zero voltage is produced by shorting the gate to the source, as in Figure 4-5(a) where both are grounded. As V DD (and thus V DS ) is increased from 0 to V P, I D will increase proportionally, as shown in the graph of Figure 4-5(b) between points A and B. In this region, the channel resistance is essentially constant because the depletion region is not large enough to have a significant effect. This region is called the ohmic region because V DS and I D are related by Ohm's law. The value of the resistance can be changed by the gate voltage; thus, it is possible to use a JFET as a voltage-controlled resistor when it is operated in this region. An application will be shown in Figure 10-10 (Wienbridge). The drain characteristic curve of a JFET for V GS =0V showing pinch off. Figure 4-5 At point B in Figure 4-5(b), the curve levels off and I D becomes essentially constant. As V DS increases from point B to point C, the reverse-bias voltage from gate to drain (V GD ) produces a depletion region large enough to offset the increase in V DS, thus keeping I D relatively constant. This region is called the constant-current region. Pinch-Off Voltage For V GS = 0 V, the value of V DS at which I D becomes essentially constant (point B on the curve in Figure 4-5 (b)) is the pinch-off voltage, Vp. Notice that the pinch-off voltage is a positive value for an n-channel JFET. For a given JFET, Vp has a fixed value. As you can see, a continued increase in V DS above the pinch-off voltage produces an almost constant drain current. This value of drain current is I DSS (Drain to Source current with gate Shorted) and is always specified on JFET data sheets. I DSS is the maximum drain current that a specific JFET can produce regardless of the external circuit, and it is always specified for the condition, V GS = 0 V. Continuing along the graph in Figure 4-5(b), breakdown occurs at point C when I D begins to increase very rapidly with any further increase in V DS. Breakdown can result in irreversible damage to the device, so JFETs are always operated below breakdown and usually within the constant-current region (between points B and C on the graph). 4 OF 10

V GS Controls I D Let's connect a bias voltage, V GG, from gate to source as shown in Figure 4-6(a). As V GS is set to increasingly more negative values by adjusting V GG, a family of drain characteristic curves is produced, as shown in Figure 4-6(b). Notice that I D decreases as the magnitude of V GS is increased to larger negative values because of the narrowing of the channel. Also notice that, for each increase in V GS, the JFET reaches pinch-off (where constant current begins) at values of V DS less than Vp. So, the amount of drain current is controlled by V GS. Cutoff Voltage The value of V GS that makes I D approximately zero is the cutoff voltage, V GS(off) The JFET must be operated between V GS = 0 V and V GS(off). For this range of gate-to-source voltages, I D will vary from a maximum of I DSS to a minimum of almost zero. As you have seen, for an n-channel JFET, the more negative V GS is, the smaller I D becomes in the constant-current region. When V GS has a sufficiently large negative value, I D is reduced to zero. This cutoff effect is caused by the widening of the depletion region to a point where it completely closes the channel. The bottom line on the characteristic curve represents this condition. Comparison of Pinch-Off and Cutoff The pinch-off voltage is measured on the drain characteristic. For an n-channel device, it is the positive voltage at which the drain current becomes constant when V GS = 0 V. Cutoff can also be measured on the drain characteristic and represents the negative gate-to-source voltage that reduces the drain current to zero. V GS(off) and Vp are always equal in magnitude but opposite in sign. A data sheet usually will give either V GS(off) or Vp, but not both. However, when you know one, you have the other. For example, if V GS(off) = - 5 V, then Vp = + 5 V. 5 OF 10

Problem For the n-channel JFET in Figure 4-7, VGS(off) = -4 V and IDss = 12 ma. Determine the minimum value of VDD required to put the device in the constant-current region of operation. FIGURE 4-7 Solution Since V GS(off) = -4 V, V p = 4 V. The minimum value of V DS for the JFET to be in its constant-current region is V DS = Vp = 4 V In the constant-current region with V GS = 0 V, I D = I DSS = 12 ma The drop across the drain resistor is V RD = (12 ma)(560 Ω) = 6.7 V Applying Kirchhoff's law around the drain circuit gives V DD = V DS + V RD = 4 V + 6.7 V = 10.7 V This is the minimum value of V DD to make V DS = Vp and to put the device in the constant current region. Question* If V DD is increased to 15 V, what is the drain current? JFET Transconductance Curves A useful way of looking at any circuit is to show the output for a given input. This characteristic is called a transfer curve. Since the JFET is controlled by a negative voltage on the input (gate) and the output is drain current, the transfer curve is a plot of I D, plotted on the y-axis, as a function of V GS, plotted on the x-axis. When the output unit (ma) is divided by the input unit (V), the result is the unit of conductance (ms). You can think of a voltage at the input being transferred to the output as a current; thus, the prefix "trans" is added to the word conductance forming the word transconductance. The transconductance curve is a plot of the transfer characteristic (I D versus V GS ) of a FET. Transconductance is listed on data sheets as g m or y fs. A representative curve for an n-channel JFET is shown in Figure 4-8(a). Generally, all types of FETs have a transconductance curve with this same basic shape. The curves shown are typical for a general-purpose n-channel JFET. Fig. 4-8 6 OF 10

The transconductance characteristic is directly related to the drain characteristic as shown in Figure 4-8(b). Notice that both plots have the same vertical axis, representing I D. Transconductance is an ac parameter so its value is found at any point on the curve by dividing a small change in drain current by a small change in gate-to-source voltage. This equation can be written with ac notation as simply: g m = I V D GS I d g m = Vgs The transconductance curve is not a straight line, implying that the relation between the output current and the input voltage is nonlinear. This is an important point: FET s have a nonlinear transconductance curve. This means that they tend to add distortion to an input signal. Distortion is not always a bad thing; for example, in radio frequency mixers, JFET s have an advantage over BJT s because of this characteristic. Problem For the curve in Figure 4-9, determine the transconductance at I D = 1.0 ma. FIGURE 4-9 Solution Select a small change in I D and divide it by the corresponding change in V GS at 1.0 ma. The graphical method is shown in Figure 4-9. From the graph, the transconductance is Question What is the transconductance at. I D = 1.5 ma? I D 1.25mA 0.75mA gm = = = 0. 714mS V 1.1V ( 1.8V ) GS 7 OF 10

JFET Input Resistance As you know, a pn junction has a very high resistance when it is reverse-biased. A JFET operates with its gate-source junction reverse-biased; therefore, the input resistance at the gate is very high. This very high input resistance is a major advantage of the JFET over the bipolar junction transistor with its forward-biased base-emitter junction. JFET data sheets often specify the input resistance by giving a value for the gate reverse current, I GSS, at a certain gate-tosource voltage. The input resistance can then be deter- mined using the following equation. The vertical lines indicate an absolute value (an unsigned value). VGS R N = IGS For example, the 2N5457 data sheet lists a maximum I GSS of I ma for V GS =-15 V. Using these values, you find that the input resistance is VGS 15V RIN = = = 15GΩ I 1nA GSS As you can see from this result, the input resistance of this JFET is incredibly high. How ever, in a typical application, the total input resistance will include a resistor connected to the gate. The result is a total input resistance in the 1-10 MΩ range. 4-3 JFET BIASING Using some of the JFET characteristics discussed in the previous section, we will now see how to dc bias JFET s. The purpose of biasing is to select a proper dc gate-to-source voltage to establish a desired value of drain current. Because the gate is reversebiased, the methods for applying bias with a bipolar junction transistor do not work with JFET s. In this section, you will learn how to bias a JFET using self-bias and voltage-divider bias. Self-Biasing a JFET Biasing a FET is relatively easy. An n-channel JFET is shown for the following examples. Keep in mind that a p-channel JFET just reverses the polarities. To set up reverse bias requires a negative V GS for an n-channel JFET. This can be achieved using the self-bias arrangement shown in Figure 4-10. Notice that the gate is biased at 0 V by resistor R G connected to ground. Although reverse leakage current, I GSS, does produce a very tiny voltage across R G, it is neglected in most cases; it can be assumed that R G has no current and no voltage drop across it. The purpose of R G is to tie the gate to a solid 0 V without affecting any ac signal that will be added later. Since the gate current is negligible, R G can be large (typically 1.0 MΩ or more), resulting in very high input resistance to low frequency ac signals. If the gate is at zero volts, how do you obtain the required negative bias on the gate-source junction? The answer is that you make the source positive with respect to the gate, producing the required reverse bias. For the n-channel JFET in Figure 4-10, I D produces a voltage drop across R S with the polarity shown, making the source terminal positive with respect to ground. Since V G = 0 V, and V s = I D R S, the gate-to-source voltage is V GS =V G -V S =0-I D R S Thus, V GS =-I D R S This result shows that the gate-to-source voltage is negative, producing the required reverse bias. In this analysis, an n- channel JFET was used for illustration. Again, the p-channel JFET also requires reverse bias, but the polarity of all voltages is opposite those of the n-channel JFET. 8 OF 10

The drain voltage with respect to ground is determined as follows: V D =V DD -I D R D Self-biased n-channel JFET Fig. 4-10 Since V S =I D R S, the drain-to-source voltage is : V DS =V D -V S V DS =V DD -I D (R D -R S ) Problem Find V DS and V GS in Figure 4-11. For the particular JFET in this circuit, assume that the internal parameters are such that a drain current (I D ) of approximately 5.0 ma is produced. Another JFET, even of the same type, may not produce the same results when connected in this circuit due to variations in parameter values. Solution Figure 4-11 V S = I D R S = (5.0 ma) (68 Ω) = 0.34 V V D = V DD I D R D = 15 V - (5.0 ma) (1.0 kω) = 10.0 V Therefore, V DS = V D V S =10.0V-0.34V=9.66V and 9 OF 10

V GS = V G - V S =0V-0.34V= -0.34V Question What is V DS and V GS in Figure 4-11 if I D = 3.0 ma? Graphical Methods Recall that the IV characteristic curve for a resistor, R, is a straight line with a slope of I/R. To compare the plot of the selfbias resistor with the transconductance curve, both lines are plotted in the second quadrant; the resistance is plotted with a slope of I/R. The transconductance curve for a typical JFET can be used to illustrate how a reasonable value of a self-bias resistor (R S ) is selected. Assume the transconductance curve is as shown in Figure 4-12. Draw a straight line from the origin to the point where V GS(off) (-4 V) intersects I DSS (2.5 ma). The reciprocal of the slope of this line represents a reasonable choice for R S. R VGS ( off ) 4V = = = 1. KΩ I 2.5mA S 6 DSS The absolute (unsigned) value of V GS(off) is used. The resulting 1.6 kω resistor is available as a standard 5 % value, or you could select a 1.5 kω standard 10% resistor instead. The point where the two lines cross represents the Q-point for determining bias. This Q- point represents V GS and I D for this particular case; it shows that V GS = - 1.5 V at I D = 0.95 ma. Graphical analysis of self-bias 10 OF 10

Self-bias helps compensate for different device characteristics between various JFET s. For instance, assume the transistor is replaced with one with a lower transconductance. As a result, the new drain current will be less, causing a smaller voltage drop across R S. This reduced voltage tends to turn the JFET on more, compensating for the lower transconductance of the new transistor. The effect of a range of transconductance curves is best illustrated by an example. Problem A 2N5457 general-purpose JFET has the following specifications: I DSS(min) =1mA, I DSS(max) =5mA, V GS(off)(min) ==-0.5V, V GS(off)(max) =-6V. Select a self-bias resistor for this JFET. Solution Typical of small-signal JFETS, the range of I DSS and V GS(off) is very large. To select the best resistor, check the extremes of the specified values V GS(off) and I DSS. R R S VGS ( off )(min) 0.5v = = = 500Ω I 1.0mA DSS (min) VGS ( off )(max) 6V = = = 1. KΩ I 5.0mA S 2 DSS (max) A good choice is 820 Ω, a standard value between these extremes. To see what this looks like on the transconductance curve, sketch the curves with this resistor and plot the maximum and minimum Q-points. This is done in Figure 4-13. Despite the extreme variation between the minimum and maximum specification, the 820 Ω resistor represents a good choice for either. FIGURE 4-13 Effect of a wide range of transconductance curves on the Q-point Question What is the largest and smallest I D expected for a 2N5457 that is self-biased with an 820 Ω resistor? 11 OF 10

Voltage-Divider Bias Field Effect Transistors (FET) Although self-bias is satisfactory for many applications, the operating point is dependent on the transconductance curve as you have seen. The bias can be made more stable with the addition of a voltage divider on the gate circuit, forcing the gate to a positive voltage. Since the JFET must still operate with a negative gate-source bias, a larger source resistor is used than in normal self-bias. The circuit is shown in Figure 4-14. Typical values are shown on the schematic. The gate voltage is found by applying the voltage-divider rule to R1 and R2. V = R 2 G V DD R1 + R2 To illustrate how the voltage-divider bias works, find the gate voltage from Equation 4-5. R1 2.2MΩ VG = VDD 12V = 2. 2V R1 R = + 2 10MΩ + 2.2MΩ The source resistor is generally larger than one used in basic self-bias because it must develop at least 2.2 V to produce the required negative bias between the gate and source. Because of the wide variation of FETs, it is not possible to predict the exact source voltage; about 3 V is expected on the source for the 2N5458. Remember, if you are troubleshooting any JFET circuit, the source voltage has to be equal or larger than the gate voltage. The drain current is in both R D and R S. Since I D is dependent on the transconductance of the JFET, the precise value of V D and V S cannot be determined from the circuit values alone because of the manufacturing spread of FETS. In general, a JFET linear amplifier should be designed such that VDS is in the range from about 25% to 50% of V DD. Even without knowing the parameters for the transistor, you can verify that the bias is set up correctly by checking V DS. Figure 4-14 Voltage divider bias and self-bias 12 OF 10